diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 12a7af0750813..47d6a5f4f95df 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -437,6 +437,11 @@ void RISCVInstrInfo::copyPhysRegVector(
       MIB.addReg(RISCV::VL, RegState::Implicit);
       MIB.addReg(RISCV::VTYPE, RegState::Implicit);
     }
+    // Add an implicit read of the original source to silence the verifier
+    // in the cases where some of the smaller VRs we're copying from might be
+    // undef, caused by the fact that the original, larger source VR might not
+    // be fully initialized at the time this COPY happens.
+    MIB.addReg(SrcReg, RegState::Implicit);
 
     // If we are copying reversely, we should decrease the encoding.
     SrcEncoding += (ReversedCopy ? -NumCopied : NumCopied);
diff --git a/llvm/test/CodeGen/RISCV/postra-copy-expand.mir b/llvm/test/CodeGen/RISCV/postra-copy-expand.mir
new file mode 100644
index 0000000000000..e5b85659a0340
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/postra-copy-expand.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=postrapseudos %s -o - | FileCheck %s
+
+---
+name:            copy
+isSSA:           false
+noVRegs:         true
+liveins:
+  - { reg: '$v0', virtual-reg: '' }
+body:             |
+  bb.0:
+    liveins: $v0
+
+    ; CHECK-LABEL: name: copy
+    ; CHECK: liveins: $v0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $v20m2 = VMV2R_V $v14m2, implicit $vtype, implicit $v14_v15_v16_v17_v18
+    ; CHECK-NEXT: $v22m2 = VMV2R_V $v16m2, implicit $vtype, implicit $v14_v15_v16_v17_v18
+    ; CHECK-NEXT: $v24 = VMV1R_V $v18, implicit $vtype, implicit $v14_v15_v16_v17_v18, implicit $vtype
+    ; CHECK-NEXT: PseudoRET implicit $v0
+    renamable $v20_v21_v22_v23_v24 = COPY renamable $v14_v15_v16_v17_v18, implicit $vtype
+    PseudoRET implicit $v0
+
+...