diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index c308ec332e844..26e9b4b9facec 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -895,6 +895,20 @@ PPCTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
   return BaseT::getIntrinsicInstrCost(ICA, CostKind);
 }
 
+bool PPCTTIImpl::areInlineCompatible(const Function *Caller,
+                                     const Function *Callee) const {
+  const TargetMachine &TM = getTLI()->getTargetMachine();
+
+  const FeatureBitset &CallerBits =
+      TM.getSubtargetImpl(*Caller)->getFeatureBits();
+  const FeatureBitset &CalleeBits =
+      TM.getSubtargetImpl(*Callee)->getFeatureBits();
+
+  // Check that targets features are exactly the same. We can revisit to see if
+  // we can improve this.
+  return CallerBits == CalleeBits;
+}
+
 bool PPCTTIImpl::areTypesABICompatible(const Function *Caller,
                                        const Function *Callee,
                                        const ArrayRef<Type *> &Types) const {
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
index 3cb60d7a1785a..bf3ddad134e14 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
@@ -139,6 +139,8 @@ class PPCTTIImpl : public BasicTTIImplBase<PPCTTIImpl> {
       bool UseMaskForCond = false, bool UseMaskForGaps = false);
   InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
                                         TTI::TargetCostKind CostKind);
+  bool areInlineCompatible(const Function *Caller,
+                           const Function *Callee) const;
   bool areTypesABICompatible(const Function *Caller, const Function *Callee,
                              const ArrayRef<Type *> &Types) const;
   bool hasActiveVectorLength(unsigned Opcode, Type *DataType,
diff --git a/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
new file mode 100644
index 0000000000000..b7086199e6f7d
--- /dev/null
+++ b/llvm/test/Transforms/Inline/PowerPC/inline-target-attr.ll
@@ -0,0 +1,63 @@
+; RUN: opt < %s -mtriple=powerpc64le-ibm-linux-gnu -S -passes=inline | FileCheck %s
+; RUN: opt < %s -mtriple=powerpc64le-ibm-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s
+
+target datalayout = "E-m:e-i64:64-n32:64"
+target triple = "powerpc64le-ibm-linux-gnu"
+
+declare void @inlined()
+
+define void @explicit() #0 {
+; CHECK-LABEL: explicit
+; CHECK: entry
+; CHECK-NEXT: call void @not_compatible1()
+; CHECK-NEXT: call void @inlined()
+entry:
+    call void @not_compatible1()
+    call void @compatible1()
+    ret void
+}
+
+define void @not_compatible1() #1 {
+entry:
+    call i32 @inlined()
+    ret void
+}
+
+define void @compatible1() #0 {
+entry:
+    call void @inlined()
+    ret void 
+}
+
+define void @default() #3 {
+; CHECK-LABEL: default
+; CHECK: entry
+; CHECK-NEXT: call void @not_compatible2()
+; CHECK-NEXT: call void @inlined()
+entry:
+    call void @not_compatible2()
+    call void @compatible2()
+    ret void
+}
+
+define void @not_compatible2() #4 {
+entry:
+    call void @inlined()
+    ret void
+}
+
+define void @compatible2() #5 {
+entry:
+    call void @inlined()
+    ret void 
+}
+
+; explicit
+attributes #0 = { "target-cpu"="pwr7" "target-features"="+allow-unaligned-fp-access" }
+attributes #1 = { "target-cpu"="pwr7" "target-features"="-allow-unaligned-fp-access" }
+
+; pwr7 by default implies +vsx
+attributes #3 = { "target-cpu"="pwr7" }
+attributes #4 = { "target-cpu"="pwr7" "target-features"="-vsx" }
+attributes #5 = { "target-cpu"="pwr7" "target-features"="+vsx" }
+