diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 87c07c3cd505f..1e7ce136dc327 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -46,6 +46,7 @@ include "RISCVMacroFusion.td"
 // RISC-V Scheduling Models
 //===----------------------------------------------------------------------===//
 
+include "RISCVSchedGeneric.td"
 include "RISCVSchedMIPSP8700.td"
 include "RISCVSchedRocket.td"
 include "RISCVSchedSiFive7.td"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index c54afa1e6e72e..05fcbfd42b092 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -88,15 +88,6 @@ class RISCVTuneProcessorModel<string n,
 
 defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
 
-// Adjust the default cost model to enable all heuristics, not just latency
-// In particular, this enables register pressure heustics which are very
-// important for high LMUL vector code, and have little negative impact
-// on other configurations,
-def GenericModel : SchedMachineModel {
-  let MicroOpBufferSize = 1;
-  let CompleteModel = 0;
-}
-
 def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
                                        GenericModel,
                                        [Feature32Bit,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedGeneric.td b/llvm/lib/Target/RISCV/RISCVSchedGeneric.td
new file mode 100644
index 0000000000000..a10cf624aa3a4
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedGeneric.td
@@ -0,0 +1,18 @@
+//===-- RISCVSchedGeneric.td - Generic In-order Processor --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// Adjust the default cost model to enable all scheduling heuristics, not just
+// latency.
+//
+// In particular, this enables register pressure heuristics which are very
+// important for vector code with high LMULs, and have little negative impact
+// on other configurations.
+def GenericModel : SchedMachineModel {
+  let MicroOpBufferSize = 1;
+  let CompleteModel = 0;
+}