diff --git a/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll b/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
index 5e9c75283105c..2c2855c860ebb 100644
--- a/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
+++ b/llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
@@ -80,7 +80,7 @@ define amdgpu_kernel void @mul_32bit_ptr(ptr addrspace(1) %out, ptr addrspace(3)
   ret void
 }
 
-@g_lds = addrspace(3) global float undef, align 4
+@g_lds = addrspace(3) global float poison, align 4
 
 ; FUNC-LABEL: {{^}}infer_ptr_alignment_global_offset:
 ; SI: v_mov_b32_e32 [[PTR:v[0-9]+]], 0{{$}}
@@ -93,7 +93,7 @@ define amdgpu_kernel void @infer_ptr_alignment_global_offset(ptr addrspace(1) %o
 
 
 @ptr = addrspace(3) global ptr addrspace(3) poison
-@dst = addrspace(3) global [16383 x i32] undef
+@dst = addrspace(3) global [16383 x i32] poison
 
 ; FUNC-LABEL: {{^}}global_ptr:
 ; SI: ds_write_b32
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
index b96fc71be057e..dce4048a4b87e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_udec_wrap.ll
@@ -8,8 +8,8 @@
 ; FIXME: Merge with other test. DS offset folding doesn't work due to
 ; register bank copies, and no return optimization is missing.
 
-@lds0 = internal addrspace(3) global [512 x i32] undef
-@lds1 = internal addrspace(3) global [512 x i64] undef, align 8
+@lds0 = internal addrspace(3) global [512 x i32] poison
+@lds1 = internal addrspace(3) global [512 x i64] poison, align 8
 
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
index e1397e7331d3c..af21a07a4c3a1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomicrmw_uinc_wrap.ll
@@ -9,8 +9,8 @@
 ; FIXME: Merge with other test. DS offset folding doesn't work due to
 ; register bank copies, and no return optimization is missing.
 
-@lds0 = internal addrspace(3) global [512 x i32] undef, align 4
-@lds1 = internal addrspace(3) global [512 x i64] undef, align 8
+@lds0 = internal addrspace(3) global [512 x i32] poison, align 4
+@lds1 = internal addrspace(3) global [512 x i64] poison, align 8
 
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
index 4eddf087bbec2..1d65096c2e5c9 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.illegal.ll
@@ -4,7 +4,7 @@
 ; ERR: LLVM ERROR: unable to legalize instruction: %{{[0-9]+}}:_(p5) = G_GLOBAL_VALUE @external_private (in function: fn_external_private)
 
 @external_private = external addrspace(5) global i32, align 4
-@internal_private = internal addrspace(5) global i32 undef, align 4
+@internal_private = internal addrspace(5) global i32 poison, align 4
 
 define ptr addrspace(5) @fn_external_private() {
   ret ptr addrspace(5) @external_private
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
index 21fa4afb374cd..831ca4d7857eb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/hip.extern.shared.array.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck %s
 
-@lds0 = addrspace(3) global [512 x float] undef
-@lds1 = addrspace(3) global [256 x float] undef
-@lds2 = addrspace(3) global [4096 x float] undef
-@lds3 = addrspace(3) global [67 x i8] undef
+@lds0 = addrspace(3) global [512 x float] poison
+@lds1 = addrspace(3) global [256 x float] poison
+@lds2 = addrspace(3) global [4096 x float] poison
+@lds3 = addrspace(3) global [67 x i8] poison
 
 @dynamic_shared0 = external addrspace(3) global [0 x float]
 @dynamic_shared1 = external addrspace(3) global [0 x double]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
index c7870d98d4ca1..aa63e593f9dc1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constantexpr.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stop-after=irtranslator -o - %s | FileCheck %s
 
-@var = global i32 undef
+@var = global i32 poison
 
 define i32 @test() {
   ; CHECK-LABEL: name: test
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
index b250e016492bc..a6a7f35a774db 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll
@@ -2,8 +2,8 @@
 ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s
 ; TODO: Replace with existing DAG tests
 
-@lds_512_4 = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4
-@lds_4_8 = addrspace(3) global i32 undef, align 8
+@lds_512_4 = internal unnamed_addr addrspace(3) global [128 x i32] poison, align 4
+@lds_4_8 = addrspace(3) global i32 poison, align 8
 
 define amdgpu_kernel void @use_lds_globals(ptr addrspace(1) %out, ptr addrspace(3) %in) #0 {
 ; CHECK-LABEL: use_lds_globals:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
index cd536e2336cac..0b9f31e3a765e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/lds-relocs.ll
@@ -2,7 +2,7 @@
 ; FIXME: Merge with DAG test
 
 @lds.external = external unnamed_addr addrspace(3) global [0 x i32]
-@lds.defined = unnamed_addr addrspace(3) global [8 x i32] undef, align 8
+@lds.defined = unnamed_addr addrspace(3) global [8 x i32] poison, align 8
 
 ; GCN-LABEL: {{^}}test_basic:
 ; GCN: s_add_u32 s0, lds.defined@abs32@lo, s0 ; encoding: [0xff,0x00,0x00,0x80,A,A,A,A]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
index e75898e0f440f..a354c072aa150 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
@@ -87,10 +87,10 @@ bb2:
 
 ; FIXME: These aren't localized because thesee were legalized before
 ; the localizer, and are no longer G_GLOBAL_VALUE.
-@gv0 = addrspace(1) global i32 undef, align 4
-@gv1 = addrspace(1) global i32 undef, align 4
-@gv2 = addrspace(1) global i32 undef, align 4
-@gv3 = addrspace(1) global i32 undef, align 4
+@gv0 = addrspace(1) global i32 poison, align 4
+@gv1 = addrspace(1) global i32 poison, align 4
+@gv2 = addrspace(1) global i32 poison, align 4
+@gv3 = addrspace(1) global i32 poison, align 4
 
 define amdgpu_kernel void @localize_globals(i1 %cond) {
 ; GFX9-LABEL: localize_globals:
@@ -159,10 +159,10 @@ bb2:
   ret void
 }
 
-@static.gv0 = internal addrspace(1) global i32 undef, align 4
-@static.gv1 = internal addrspace(1) global i32 undef, align 4
-@static.gv2 = internal addrspace(1) global i32 undef, align 4
-@static.gv3 = internal addrspace(1) global i32 undef, align 4
+@static.gv0 = internal addrspace(1) global i32 poison, align 4
+@static.gv1 = internal addrspace(1) global i32 poison, align 4
+@static.gv2 = internal addrspace(1) global i32 poison, align 4
+@static.gv3 = internal addrspace(1) global i32 poison, align 4
 
 define void @localize_internal_globals(i1 %cond) {
 ; GFX9-LABEL: localize_internal_globals:
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
index 0f5028fd82296..59bd4e9ac8ce6 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll
@@ -4,17 +4,17 @@
 
 declare void @llvm.memcpy.p1.p4.i32(ptr addrspace(1) nocapture, ptr addrspace(4) nocapture, i32, i1) #0
 
-@lds.i32 = unnamed_addr addrspace(3) global i32 undef, align 4
-@lds.arr = unnamed_addr addrspace(3) global [256 x i32] undef, align 4
+@lds.i32 = unnamed_addr addrspace(3) global i32 poison, align 4
+@lds.arr = unnamed_addr addrspace(3) global [256 x i32] poison, align 4
 
-@global.i32 = unnamed_addr addrspace(1) global i32 undef, align 4
-@global.arr = unnamed_addr addrspace(1) global [256 x i32] undef, align 4
+@global.i32 = unnamed_addr addrspace(1) global i32 poison, align 4
+@global.arr = unnamed_addr addrspace(1) global [256 x i32] poison, align 4
 
 ;.
-; HSA: @lds.i32 = unnamed_addr addrspace(3) global i32 undef, align 4
-; HSA: @lds.arr = unnamed_addr addrspace(3) global [256 x i32] undef, align 4
-; HSA: @global.i32 = unnamed_addr addrspace(1) global i32 undef, align 4
-; HSA: @global.arr = unnamed_addr addrspace(1) global [256 x i32] undef, align 4
+; HSA: @lds.i32 = unnamed_addr addrspace(3) global i32 poison, align 4
+; HSA: @lds.arr = unnamed_addr addrspace(3) global [256 x i32] poison, align 4
+; HSA: @global.i32 = unnamed_addr addrspace(1) global i32 poison, align 4
+; HSA: @global.arr = unnamed_addr addrspace(1) global [256 x i32] poison, align 4
 ;.
 define amdgpu_kernel void @store_cast_0_flat_to_group_addrspacecast() #1 {
 ; HSA-LABEL: define {{[^@]+}}@store_cast_0_flat_to_group_addrspacecast
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
index b2a6600eeff15..ba8398ea227ca 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer-unsupported.ll
@@ -2,6 +2,6 @@
 
 ; ERROR: LLVM ERROR: Unsupported expression in static initializer: addrspacecast (ptr addrspace(3) @lds.arr to ptr addrspace(4))
 
-@lds.arr = unnamed_addr addrspace(3) global [256 x i32] undef, align 4
+@lds.arr = unnamed_addr addrspace(3) global [256 x i32] poison, align 4
 
 @gv_flatptr_from_lds = unnamed_addr addrspace(2) global ptr addrspace(4) getelementptr ([256 x i32], ptr addrspace(4) addrspacecast (ptr addrspace(3) @lds.arr to ptr addrspace(4)), i64 0, i64 8), align 4
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
index 013b9f265267b..ab73b51e9dab2 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-initializer.ll
@@ -16,7 +16,7 @@
 ; CHECK: .quad constant.arr+32
 ; CHECK: .size	gv_flatptr_from_constant, 8
 
-@global.arr = unnamed_addr addrspace(1) global [256 x i32] undef, align 4
+@global.arr = unnamed_addr addrspace(1) global [256 x i32] poison, align 4
 @constant.arr = external unnamed_addr addrspace(4) global [256 x i32], align 4
 
 @gv_flatptr_from_global = unnamed_addr addrspace(4) global ptr addrspace(0) getelementptr ([256 x i32], ptr addrspace(0) addrspacecast (ptr addrspace(1) @global.arr to ptr addrspace(0)), i64 0, i64 8), align 4
diff --git a/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll b/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
index 7cf56489155e0..37f2b8f41c22c 100644
--- a/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
+++ b/llvm/test/CodeGen/AMDGPU/addrspacecast-known-non-null.ll
@@ -21,7 +21,7 @@ define void @cast_alloca() {
   ret void
 }
 
-@lds = internal unnamed_addr addrspace(3) global i8 undef, align 4
+@lds = internal unnamed_addr addrspace(3) global i8 poison, align 4
 
 ; CHECK-LABEL: {{^}}cast_lds_gv:
 ; CHECK: s_mov_b64 s[{{[0-9]+}}:[[HIREG:[0-9]+]]], src_shared_base
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
index 5d438887cbc91..32f3da6d5ea9c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll
@@ -220,7 +220,7 @@ define void @test_8_3(ptr %p) {
   ret void
 }
 
-@shm = internal addrspace(3) global [2 x i8] undef, align 4
+@shm = internal addrspace(3) global [2 x i8] poison, align 4
 
 ; CHECK-LABEL: Function: test_8_4
 ; CHECK: NoAlias:   i8* %p, i8 addrspace(3)* %p1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
index 6be31eab37945..3e232bb1914f8 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
@@ -41,7 +41,7 @@ define amdgpu_kernel void @constant_from_offset_cast_global_null() {
   ret void
 }
 
-@gv = unnamed_addr addrspace(1) global [64 x i8] undef, align 4
+@gv = unnamed_addr addrspace(1) global [64 x i8] poison, align 4
 
 define amdgpu_kernel void @constant_from_offset_cast_global_gv() {
 ; GFX9-LABEL: @constant_from_offset_cast_global_gv(
diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll b/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
index a5f915c48ebee..f4d17e50cf18c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
@@ -125,7 +125,7 @@ define amdgpu_gfx float @simple_stack_recurse(float %arg0) #0 {
   ret float %add
 }
 
-@lds = internal addrspace(3) global [64 x float] undef
+@lds = internal addrspace(3) global [64 x float] poison
 
 define amdgpu_gfx float @simple_lds(float %arg0) #0 {
   %val = load float, ptr addrspace(3) @lds
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 3c0646c46efd0..cd4e5a5730459 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -16,8 +16,8 @@
 
 declare i32 @llvm.amdgcn.workitem.id.x()
 
-@local_var32 = addrspace(3) global i32 undef, align 4
-@local_var64 = addrspace(3) global i64 undef, align 8
+@local_var32 = addrspace(3) global i32 poison, align 4
+@local_var64 = addrspace(3) global i64 poison, align 8
 
 ; Show what the atomic optimization pass will do for local pointers.
 
diff --git a/llvm/test/CodeGen/AMDGPU/divergence-at-use.ll b/llvm/test/CodeGen/AMDGPU/divergence-at-use.ll
index 422be3fa18e97..955b5389c0dcd 100644
--- a/llvm/test/CodeGen/AMDGPU/divergence-at-use.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergence-at-use.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 - < %s | FileCheck %s
 
-@local = addrspace(3) global i32 undef
+@local = addrspace(3) global i32 poison
 
 define amdgpu_kernel void @reducible() {
 ; CHECK-LABEL: reducible:
diff --git a/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll b/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
index 30fe881d41367..8f702da64c508 100644
--- a/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
@@ -6,7 +6,7 @@
 
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
-@lds.obj = addrspace(3) global [256 x i32] undef, align 4
+@lds.obj = addrspace(3) global [256 x i32] poison, align 4
 
 define amdgpu_kernel void @write_ds_sub0_offset0_global() #0 {
 ; CI-LABEL: write_ds_sub0_offset0_global:
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2.ll b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
index c37c7777f617f..7bfd9ab8cadb2 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
@@ -6,8 +6,8 @@
 ; FIXME: We don't get cases where the address was an SGPR because we
 ; get a copy to the address register for each one.
 
-@lds = addrspace(3) global [512 x float] undef, align 4
-@lds.f64 = addrspace(3) global [512 x double] undef, align 8
+@lds = addrspace(3) global [512 x float] poison, align 4
+@lds.f64 = addrspace(3) global [512 x double] poison, align 8
 
 define amdgpu_kernel void @simple_read2_f32(ptr addrspace(1) %out) #0 {
 ; CI-LABEL: simple_read2_f32:
@@ -921,7 +921,7 @@ define amdgpu_kernel void @misaligned_read2_f64(ptr addrspace(1) %out, ptr addrs
   ret void
 }
 
-@foo = addrspace(3) global [4 x i32] undef, align 4
+@foo = addrspace(3) global [4 x i32] poison, align 4
 
 define amdgpu_kernel void @load_constant_adjacent_offsets(ptr addrspace(1) %out) {
 ; CI-LABEL: load_constant_adjacent_offsets:
@@ -983,7 +983,7 @@ define amdgpu_kernel void @load_constant_disjoint_offsets(ptr addrspace(1) %out)
   ret void
 }
 
-@bar = addrspace(3) global [4 x i64] undef, align 4
+@bar = addrspace(3) global [4 x i64] poison, align 4
 
 define amdgpu_kernel void @load_misaligned64_constant_offsets(ptr addrspace(1) %out) {
 ; CI-LABEL: load_misaligned64_constant_offsets:
@@ -1017,7 +1017,7 @@ define amdgpu_kernel void @load_misaligned64_constant_offsets(ptr addrspace(1) %
   ret void
 }
 
-@bar.large = addrspace(3) global [4096 x i64] undef, align 4
+@bar.large = addrspace(3) global [4096 x i64] poison, align 4
 
 define amdgpu_kernel void @load_misaligned64_constant_large_offsets(ptr addrspace(1) %out) {
 ; CI-LABEL: load_misaligned64_constant_large_offsets:
@@ -1053,8 +1053,8 @@ define amdgpu_kernel void @load_misaligned64_constant_large_offsets(ptr addrspac
   ret void
 }
 
-@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] undef, align 4
-@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4
+@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] poison, align 4
+@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] poison, align 4
 
 define amdgpu_kernel void @sgemm_inner_loop_read2_sequence(ptr addrspace(1) %C, i32 %lda, i32 %ldb) #0 {
 ; CI-LABEL: sgemm_inner_loop_read2_sequence:
@@ -1440,7 +1440,7 @@ define amdgpu_ps <2 x float> @ds_read_interp_read(i32 inreg %prims, ptr addrspac
   ret <2 x float> %r1
 }
 
-@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] undef, align 1
+@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] poison, align 1
 
 define amdgpu_kernel void @read2_v2i32_align1_odd_offset(ptr addrspace(1) %out) {
 ; CI-LABEL: read2_v2i32_align1_odd_offset:
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll b/llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
index 3b9e47b75a563..9b85ad219c7f4 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI %s
 
-@lds = addrspace(3) global [512 x float] undef, align 4
+@lds = addrspace(3) global [512 x float] poison, align 4
 
 ; offset0 is larger than offset1
 
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll b/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
index bdc31d9161388..5a8521b2221f6 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
@@ -1,11 +1,11 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt,-enable-ds128 < %s | FileCheck --check-prefix=CI %s
 
-@lds = addrspace(3) global [512 x float] undef, align 4
-@lds.v2 = addrspace(3) global [512 x <2 x float>] undef, align 4
-@lds.v3 = addrspace(3) global [512 x <3 x float>] undef, align 4
-@lds.v4 = addrspace(3) global [512 x <4 x float>] undef, align 4
-@lds.v8 = addrspace(3) global [512 x <8 x float>] undef, align 4
-@lds.v16 = addrspace(3) global [512 x <16 x float>] undef, align 4
+@lds = addrspace(3) global [512 x float] poison, align 4
+@lds.v2 = addrspace(3) global [512 x <2 x float>] poison, align 4
+@lds.v3 = addrspace(3) global [512 x <3 x float>] poison, align 4
+@lds.v4 = addrspace(3) global [512 x <4 x float>] poison, align 4
+@lds.v8 = addrspace(3) global [512 x <8 x float>] poison, align 4
+@lds.v16 = addrspace(3) global [512 x <16 x float>] poison, align 4
 
 ; CI-LABEL: {{^}}simple_read2_v2f32_superreg_align4:
 ; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2st64.ll b/llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
index d15183e57c938..cc68ff3dfb82a 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
@@ -1,8 +1,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
 
-@lds = addrspace(3) global [512 x float] undef, align 4
-@lds.f64 = addrspace(3) global [512 x double] undef, align 8
+@lds = addrspace(3) global [512 x float] poison, align 4
+@lds.f64 = addrspace(3) global [512 x double] poison, align 8
 
 
 ; GCN-LABEL: @simple_read2st64_f32_0_1
diff --git a/llvm/test/CodeGen/AMDGPU/ds_write2.ll b/llvm/test/CodeGen/AMDGPU/ds_write2.ll
index e49b181049cc5..41e3d5f10f6dd 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_write2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_write2.ll
@@ -3,8 +3,8 @@
 ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,-unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-ALIGNED %s
 ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt,+unaligned-access-mode < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GFX9-UNALIGNED %s
 
-@lds = addrspace(3) global [512 x float] undef, align 4
-@lds.f64 = addrspace(3) global [512 x double] undef, align 8
+@lds = addrspace(3) global [512 x float] poison, align 4
+@lds.f64 = addrspace(3) global [512 x double] poison, align 8
 
 define amdgpu_kernel void @simple_write2_one_val_f32(ptr addrspace(1) %C, ptr addrspace(1) %in) #0 {
 ; CI-LABEL: simple_write2_one_val_f32:
@@ -764,7 +764,7 @@ define amdgpu_kernel void @simple_write2_two_val_f64(ptr addrspace(1) %C, ptr ad
   ret void
 }
 
-@foo = addrspace(3) global [4 x i32] undef, align 4
+@foo = addrspace(3) global [4 x i32] poison, align 4
 
 define amdgpu_kernel void @store_constant_adjacent_offsets() {
 ; CI-LABEL: store_constant_adjacent_offsets:
@@ -808,7 +808,7 @@ define amdgpu_kernel void @store_constant_disjoint_offsets() {
   ret void
 }
 
-@bar = addrspace(3) global [4 x i64] undef, align 4
+@bar = addrspace(3) global [4 x i64] poison, align 4
 
 define amdgpu_kernel void @store_misaligned64_constant_offsets() {
 ; CI-LABEL: store_misaligned64_constant_offsets:
@@ -834,7 +834,7 @@ define amdgpu_kernel void @store_misaligned64_constant_offsets() {
   ret void
 }
 
-@bar.large = addrspace(3) global [4096 x i64] undef, align 4
+@bar.large = addrspace(3) global [4096 x i64] poison, align 4
 
 define amdgpu_kernel void @store_misaligned64_constant_large_offsets() {
 ; CI-LABEL: store_misaligned64_constant_large_offsets:
@@ -862,8 +862,8 @@ define amdgpu_kernel void @store_misaligned64_constant_large_offsets() {
   ret void
 }
 
-@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] undef, align 4
-@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4
+@sgemm.lA = internal unnamed_addr addrspace(3) global [264 x float] poison, align 4
+@sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] poison, align 4
 
 define amdgpu_kernel void @write2_sgemm_sequence(ptr addrspace(1) %C, i32 %lda, i32 %ldb, ptr addrspace(1) %in) #0 {
 ; CI-LABEL: write2_sgemm_sequence:
@@ -1000,7 +1000,7 @@ define amdgpu_kernel void @simple_write2_v4f32_superreg_align4(ptr addrspace(3)
   ret void
 }
 
-@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] undef, align 1
+@v2i32_align1 = internal addrspace(3) global [100 x <2 x i32>] poison, align 1
 
 define amdgpu_kernel void @write2_v2i32_align1_odd_offset() {
 ; CI-LABEL: write2_v2i32_align1_odd_offset:
diff --git a/llvm/test/CodeGen/AMDGPU/ds_write2st64.ll b/llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
index 26ccc32e1bf67..b2f6f245f4dd5 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
 
-@lds = addrspace(3) global [512 x float] undef, align 4
+@lds = addrspace(3) global [512 x float] poison, align 4
 
 ; GCN-LABEL: @simple_write2st64_one_val_f32_0_1
 ; CI-DAG: s_mov_b32 m0
diff --git a/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
index 318ecd16a2ccb..e1ce5341efdd1 100644
--- a/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
@@ -29,7 +29,7 @@
 ; GFX1200-MESA: .long 45100
 ; GFX1200-MESA-NEXT: .long 1024
 
-@lds = internal addrspace(3) global [4096 x i8] undef
+@lds = internal addrspace(3) global [4096 x i8] poison
 
 define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset) {
   %ptr = getelementptr [4096 x i8], ptr addrspace(3) @lds, i32 0, i32 %voffset
diff --git a/llvm/test/CodeGen/AMDGPU/fence-barrier.ll b/llvm/test/CodeGen/AMDGPU/fence-barrier.ll
index e61f60f0fea55..9f2332c4be58b 100644
--- a/llvm/test/CodeGen/AMDGPU/fence-barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/fence-barrier.ll
@@ -7,8 +7,8 @@ declare i32 @llvm.amdgcn.workitem.id.x()
 declare i32 @llvm.amdgcn.workgroup.id.x()
 declare void @llvm.amdgcn.s.barrier()
 
-@test_local.temp = internal addrspace(3) global [1 x i32] undef, align 4
-@test_global_local.temp = internal addrspace(3) global [1 x i32] undef, align 4
+@test_local.temp = internal addrspace(3) global [1 x i32] poison, align 4
+@test_global_local.temp = internal addrspace(3) global [1 x i32] poison, align 4
 
 
 ; GCN-LABEL: {{^}}test_local
diff --git a/llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll b/llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
index 8155ac7eb256e..78bcda7041c5c 100644
--- a/llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
+++ b/llvm/test/CodeGen/AMDGPU/fence-lds-read2-write2.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 
-@lds = internal addrspace(3) global [576 x double] undef, align 16
+@lds = internal addrspace(3) global [576 x double] poison, align 16
 
 ; Stores to the same address appear multiple places in the same
 ; block. When sorted by offset, the merges would fail. We should form
diff --git a/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll b/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
index 54e3ec0ef990c..14059ccd738a9 100644
--- a/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address-codegen.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-stress-function-calls -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-lower-module-lds=false < %s | FileCheck -check-prefix=GCN %s
 
-@lds0 = addrspace(3) global i32 undef, align 4
+@lds0 = addrspace(3) global i32 poison, align 4
 
 ; GCN-NOT: load_lds_simple
 
diff --git a/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll b/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll
index f97e3f94cc0f4..fb819e4092134 100644
--- a/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll
+++ b/llvm/test/CodeGen/AMDGPU/force-alwaysinline-lds-global-address.ll
@@ -5,10 +5,10 @@
 
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
 
-@lds0 = addrspace(3) global i32 undef, align 4
-@lds1 = addrspace(3) global [512 x i32] undef, align 4
+@lds0 = addrspace(3) global i32 poison, align 4
+@lds1 = addrspace(3) global [512 x i32] poison, align 4
 @nested.lds.address = addrspace(1) global ptr addrspace(3) @lds0, align 4
-@gds0 = addrspace(2) global i32 undef, align 4
+@gds0 = addrspace(2) global i32 poison, align 4
 
 @alias.lds0 = alias i32, ptr addrspace(3) @lds0
 @lds.cycle = addrspace(3) global i32 ptrtoint (ptr addrspace(3) @lds.cycle to i32), align 4
diff --git a/llvm/test/CodeGen/AMDGPU/gds-allocation.ll b/llvm/test/CodeGen/AMDGPU/gds-allocation.ll
index 85967f5717830..f787a40021025 100644
--- a/llvm/test/CodeGen/AMDGPU/gds-allocation.ll
+++ b/llvm/test/CodeGen/AMDGPU/gds-allocation.ll
@@ -2,9 +2,9 @@
 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -amdgpu-atomic-optimizer-strategy=None -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx9-generic --amdhsa-code-object-version=6 -amdgpu-atomic-optimizer-strategy=None -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 
-@gds0 = internal addrspace(2) global [4 x i32] undef, align 4
-@lds0 = internal addrspace(3) global [4 x i32] undef, align 128
-@lds1 = internal addrspace(3) global [4 x i32] undef, align 256
+@gds0 = internal addrspace(2) global [4 x i32] poison, align 4
+@lds0 = internal addrspace(3) global [4 x i32] poison, align 128
+@lds1 = internal addrspace(3) global [4 x i32] poison, align 256
 
 ; These two objects should be allocated at the same constant offsets
 ; from the base.
@@ -55,8 +55,8 @@ define amdgpu_kernel void @alloc_lds_gds_align(ptr addrspace(1) %out) #1 {
   ret void
 }
 
-@gds_align8 = internal addrspace(2) global [4 x i32] undef, align 8
-@gds_align32 = internal addrspace(2) global [4 x i32] undef, align 32
+@gds_align8 = internal addrspace(2) global [4 x i32] poison, align 8
+@gds_align32 = internal addrspace(2) global [4 x i32] poison, align 32
 
 define amdgpu_kernel void @gds_global_align(ptr addrspace(1) %out) {
 ; GCN-LABEL: gds_global_align:
@@ -100,7 +100,7 @@ define amdgpu_kernel void @gds_global_align_plus_attr(ptr addrspace(1) %out) #0
   ret void
 }
 
-@small.gds = internal addrspace(2) global i8 undef, align 1
+@small.gds = internal addrspace(2) global i8 poison, align 1
 @gds.external = external unnamed_addr addrspace(3) global [0 x i32], align 4
 
 define amdgpu_kernel void @gds_extern_align(ptr addrspace(1) %out, ptr addrspace(2) %gds.arg) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll b/llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll
index 492d3ba7b0fcb..9a9fd361a2128 100644
--- a/llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll
+++ b/llvm/test/CodeGen/AMDGPU/hip.extern.shared.array.ll
@@ -1,9 +1,9 @@
 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs -o - %s | FileCheck %s
 
-@lds0 = addrspace(3) global [512 x float] undef
-@lds1 = addrspace(3) global [256 x float] undef
-@lds2 = addrspace(3) global [4096 x float] undef
-@lds3 = addrspace(3) global [67 x i8] undef
+@lds0 = addrspace(3) global [512 x float] poison
+@lds1 = addrspace(3) global [256 x float] poison
+@lds2 = addrspace(3) global [4096 x float] poison
+@lds3 = addrspace(3) global [67 x i8] poison
 
 @dynamic_shared0 = external addrspace(3) global [0 x float]
 @dynamic_shared1 = external addrspace(3) global [0 x double]
diff --git a/llvm/test/CodeGen/AMDGPU/hsa-group-segment.ll b/llvm/test/CodeGen/AMDGPU/hsa-group-segment.ll
index 04e580c6e118a..7a6743b9bddba 100644
--- a/llvm/test/CodeGen/AMDGPU/hsa-group-segment.ll
+++ b/llvm/test/CodeGen/AMDGPU/hsa-group-segment.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
 
-@internal_group = internal addrspace(3) global i32 undef
-@external_group = addrspace(3) global i32 undef
+@internal_group = internal addrspace(3) global i32 poison
+@external_group = addrspace(3) global i32 poison
 
 define amdgpu_kernel void @test() {
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/internalize.ll b/llvm/test/CodeGen/AMDGPU/internalize.ll
index 6b2a4d5fc328b..fcc8ce1f71251 100644
--- a/llvm/test/CodeGen/AMDGPU/internalize.ll
+++ b/llvm/test/CodeGen/AMDGPU/internalize.ll
@@ -5,10 +5,10 @@
 
 ; OPT-NOT: gvar_unused
 ; OPTNONE: gvar_unused
-@gvar_unused = addrspace(1) global i32 undef, align 4
+@gvar_unused = addrspace(1) global i32 poison, align 4
 
 ; ALL: gvar_used
-@gvar_used = addrspace(1) global i32 undef, align 4
+@gvar_used = addrspace(1) global i32 poison, align 4
 
 ; OPT: define internal fastcc void @func_used_noinline(
 ; OPT-NONE: define fastcc void @func_used_noinline(
diff --git a/llvm/test/CodeGen/AMDGPU/lds-alignment.ll b/llvm/test/CodeGen/AMDGPU/lds-alignment.ll
index 8c23ace9b014b..2a3359585b969 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-alignment.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-alignment.ll
@@ -1,13 +1,13 @@
 ; RUN: llc -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA %s
 
-@lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
-@lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
+@lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] poison, align 16
+@lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] poison, align 16
 
-@lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8
-@lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32
+@lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] poison, align 8
+@lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] poison, align 32
 
-@lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef
-@lds.missing.align.1 = internal unnamed_addr addrspace(3) global [7 x i64] undef
+@lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] poison
+@lds.missing.align.1 = internal unnamed_addr addrspace(3) global [7 x i64] poison
 
 declare void @llvm.memcpy.p3.p1.i32(ptr addrspace(3) nocapture, ptr addrspace(1) nocapture readonly, i32, i1) #0
 declare void @llvm.memcpy.p1.p3.i32(ptr addrspace(1) nocapture, ptr addrspace(3) nocapture readonly, i32, i1) #0
diff --git a/llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll b/llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
index a744e82c54384..2f694def5396b 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
@@ -10,7 +10,7 @@
 ; External LDS is checked because it influences LDS padding in general and because it will
 ; not be moved into either module or kernel struct
 
-@module_variable = addrspace(3) global i16 undef
+@module_variable = addrspace(3) global i16 poison
 
 ; Variables are allocated into module scope block when used by a non-kernel function
 define void @use_module() #0 {
@@ -26,8 +26,8 @@ define void @use_module() #0 {
 }
 
 ; Variables only used by kernels are specialised and allocated per-kernel
-@kernel_normal = addrspace(3) global i16 undef
-@kernel_overalign = addrspace(3) global i16 undef, align 4
+@kernel_normal = addrspace(3) global i16 poison
+@kernel_overalign = addrspace(3) global i16 poison, align 4
 
 ; External LDS shall not introduce padding between module and kernel scope variables
 @extern_normal = external addrspace(3) global [0 x float]
diff --git a/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll b/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll
index 0d06eb59e7bfc..771590f4df8dc 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-output-queue.ll
@@ -8,7 +8,7 @@
 ; CHECK-NOT: ALU clause
 ; CHECK: MOV * T{{[0-9]\.[XYZW]}}, OQAP
 
-@local_mem = internal unnamed_addr addrspace(3) global [2 x i32] undef, align 4
+@local_mem = internal unnamed_addr addrspace(3) global [2 x i32] poison, align 4
 
 define amdgpu_kernel void @lds_input_queue(ptr addrspace(1) %out, ptr addrspace(1) %in, i32 %index) {
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll b/llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll
index 8ab5b9d70d237..9648cb12186bd 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-reject-anonymous-kernels.ll
@@ -1,7 +1,7 @@
 ; RUN: not --crash opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s 2>&1 | FileCheck %s
 ; RUN: not --crash opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s 2>&1 | FileCheck %s
 
-@var1 = addrspace(3) global i32 undef, align 8
+@var1 = addrspace(3) global i32 poison, align 8
 
 ; CHECK: LLVM ERROR: Anonymous kernels cannot use LDS variables
 define amdgpu_kernel void @0() {
diff --git a/llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll b/llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll
index b1f4f2ef1ef53..e1ee9b2df9fa8 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-reject-mixed-absolute-addresses.ll
@@ -1,8 +1,8 @@
 ; RUN: not --crash opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s 2>&1 | FileCheck %s
 ; RUN: not --crash opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s 2>&1 | FileCheck %s
 
-@var1 = addrspace(3) global i32 undef, !absolute_symbol !0
-@var2 = addrspace(3) global i32 undef
+@var1 = addrspace(3) global i32 poison, !absolute_symbol !0
+@var2 = addrspace(3) global i32 poison
 
 ; CHECK: Module cannot mix absolute and non-absolute LDS GVs
 define amdgpu_kernel void @kern() {
diff --git a/llvm/test/CodeGen/AMDGPU/lds-relocs.ll b/llvm/test/CodeGen/AMDGPU/lds-relocs.ll
index 60dbd1c082a24..455bb6b96a06f 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-relocs.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-relocs.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -amdgpu-enable-lower-module-lds=0 -filetype=obj < %s | llvm-readobj -r --syms - | FileCheck -check-prefixes=ELF %s
 
 @lds.external = external unnamed_addr addrspace(3) global [0 x i32]
-@lds.defined = unnamed_addr addrspace(3) global [8 x i32] undef, align 8
+@lds.defined = unnamed_addr addrspace(3) global [8 x i32] poison, align 8
 
 ; ELF:      Relocations [
 ; ELF-NEXT:   Section (3) .rel.text {
diff --git a/llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll b/llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll
index 51e10d9037970..3f1dda53ef1b6 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-run-twice-absolute-md.ll
@@ -7,7 +7,7 @@
 ; Check AMDGPULowerModuleLDS can run more than once on the same module, and that
 ; the second run is a no-op.
 
-@lds = internal unnamed_addr addrspace(3) global i32 undef, align 4, !absolute_symbol !0
+@lds = internal unnamed_addr addrspace(3) global i32 poison, align 4, !absolute_symbol !0
 
 define amdgpu_kernel void @test() {
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/lds-run-twice.ll b/llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
index 615f1e3b7fb38..55280129c49ad 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-run-twice.ll
@@ -8,7 +8,7 @@
 ; the second run is a no-op.
 
 @dynlds = external addrspace(3) global [0 x i32], align 4
-@lds = internal unnamed_addr addrspace(3) global i32 undef, align 4
+@lds = internal unnamed_addr addrspace(3) global i32 poison, align 4
 
 define amdgpu_kernel void @test() {
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/lds-size.ll b/llvm/test/CodeGen/AMDGPU/lds-size.ll
index 1a9d15a00297f..655475c6543e2 100644
--- a/llvm/test/CodeGen/AMDGPU/lds-size.ll
+++ b/llvm/test/CodeGen/AMDGPU/lds-size.ll
@@ -16,7 +16,7 @@
 ; HSA: .amdhsa_group_segment_fixed_size 4
 
 ; GCN: ; LDSByteSize: 4 bytes/workgroup (compile time only)
-@lds = internal unnamed_addr addrspace(3) global i32 undef, align 4
+@lds = internal unnamed_addr addrspace(3) global i32 poison, align 4
 
 define amdgpu_kernel void @test(ptr addrspace(1) %out, i32 %cond) {
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
index 49e272bed9cef..75d2f156bdd2c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
@@ -269,7 +269,7 @@ define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(ptr %ptr) #0
   ret void
 }
 
-@lds0 = addrspace(3) global [512 x i32] undef
+@lds0 = addrspace(3) global [512 x i32] poison
 
 ; GCN-LABEL: {{^}}atomic_dec_shl_base_lds_0:
 ; CIVI-DAG: s_mov_b32 m0
@@ -418,7 +418,7 @@ define amdgpu_kernel void @global_atomic_dec_noret_i64_offset_addr64(ptr addrspa
   ret void
 }
 
-@lds1 = addrspace(3) global [512 x i64] undef, align 8
+@lds1 = addrspace(3) global [512 x i64] poison, align 8
 
 ; GCN-LABEL: {{^}}atomic_dec_shl_base_lds_0_i64:
 ; CIVI-DAG: s_mov_b32 m0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
index 2ed61352f4592..b28405f4ff113 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
@@ -128,7 +128,7 @@ define amdgpu_kernel void @global_atomic_inc_noret_i32_offset_addr64(ptr addrspa
   ret void
 }
 
-@lds0 = addrspace(3) global [512 x i32] undef, align 4
+@lds0 = addrspace(3) global [512 x i32] poison, align 4
 
 ; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i32:
 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}
@@ -326,7 +326,7 @@ define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(ptr %ptr) #0
   ret void
 }
 
-@lds1 = addrspace(3) global [512 x i64] undef, align 8
+@lds1 = addrspace(3) global [512 x i64] poison, align 8
 
 ; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i64:
 ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 3, {{v[0-9]+}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
index ad5e9f4eb6a63..a6fd38cab13d0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
@@ -127,7 +127,7 @@ define amdgpu_kernel void @gws_barrier_vgpr_offset_add(i32 %val) #0 {
   ret void
 }
 
-@lds = internal unnamed_addr addrspace(3) global i32 undef
+@lds = internal unnamed_addr addrspace(3) global i32 poison
 
 ; Check if m0 initialization is shared
 ; GCN-LABEL: {{^}}gws_barrier_save_m0_barrier_constant_offset:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
index f658ab39f771f..5db68e3a6c202 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
@@ -120,7 +120,7 @@ define amdgpu_kernel void @gws_init_vgpr_offset_add(i32 %val) #0 {
   ret void
 }
 
-@lds = internal unnamed_addr addrspace(3) global i32 undef
+@lds = internal unnamed_addr addrspace(3) global i32 poison
 
 ; Check if m0 initialization is shared.
 ; GCN-LABEL: {{^}}gws_init_save_m0_init_constant_offset:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
index da4950f7b612c..f8a71775bf6d6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticsize.ll
@@ -6,10 +6,10 @@
 ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,HSA %s
 ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,HSA %s
 
-@lds0 = addrspace(3) global [512 x float] undef, align 4
-@lds1 = addrspace(3) global [256 x float] undef, align 4
+@lds0 = addrspace(3) global [512 x float] poison, align 4
+@lds1 = addrspace(3) global [256 x float] poison, align 4
 
-@large = addrspace(3) global [4096 x i32] undef, align 4
+@large = addrspace(3) global [4096 x i32] poison, align 4
 
 ; CHECK-LABEL: {{^}}groupstaticsize_test0:
 ; NOHSA: v_mov_b32_e32 v{{[0-9]+}}, llvm.amdgcn.groupstaticsize@abs32@lo
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
index a7424831ae5db..2f440d5230b98 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
@@ -37,7 +37,7 @@ define amdgpu_kernel void @dpp_test_bc(ptr addrspace(1) %out, i32 %in1, i32 %in2
 ; GFX8-NOOPT: v_mov_b32_e32 v{{[0-9]+}}, 0
 ; GFX8: s_nop 1
 ; GFX8-NEXT: v_mov_b32_dpp {{v[0-9]+}}, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf
-@0 = internal unnamed_addr addrspace(3) global [448 x i32] undef, align 4
+@0 = internal unnamed_addr addrspace(3) global [448 x i32] poison, align 4
 define weak_odr amdgpu_kernel void @dpp_test1(ptr %arg) local_unnamed_addr {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll b/llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
index 7b919c620f8bf..bcc002fe664c1 100644
--- a/llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
@@ -2,7 +2,7 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=verde -verify-machineinstrs --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s -check-prefixes=GCN,SI
 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s -check-prefixes=GCN,CI
 
-@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4
+@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] poison, align 4
 
 define amdgpu_kernel void @local_memory(ptr addrspace(1) %out) #0 {
 ; GCN-LABEL: local_memory:
@@ -39,8 +39,8 @@ entry:
   ret void
 }
 
-@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
-@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
+@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] poison, align 4
+@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] poison, align 4
 
 ; Check that the LDS size emitted correctly
 define amdgpu_kernel void @local_memory_two_objects(ptr addrspace(1) %out) #0 {
diff --git a/llvm/test/CodeGen/AMDGPU/local-memory.ll b/llvm/test/CodeGen/AMDGPU/local-memory.ll
index 9e3180904cc24..6ba84b29fa9da 100644
--- a/llvm/test/CodeGen/AMDGPU/local-memory.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-memory.ll
@@ -2,9 +2,9 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,FUNC %s
 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=FUNC %s
 
-@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4
+@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] poison, align 4
 
-@lds = addrspace(3) global [512 x i32] undef, align 4
+@lds = addrspace(3) global [512 x i32] poison, align 4
 
 ; On SI we need to make sure that the base offset is a register and
 ; not an immediate.
diff --git a/llvm/test/CodeGen/AMDGPU/local-memory.r600.ll b/llvm/test/CodeGen/AMDGPU/local-memory.r600.ll
index 7db27f5338fed..65f79bc123e58 100644
--- a/llvm/test/CodeGen/AMDGPU/local-memory.r600.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-memory.r600.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
-@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4
+@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] poison, align 4
 
 ; Check that the LDS size emitted correctly
 ; EG: .long 166120
@@ -31,8 +31,8 @@ entry:
   ret void
 }
 
-@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
-@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
+@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] poison, align 4
+@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] poison, align 4
 
 ; Check that the LDS size emitted correctly
 ; EG: .long 166120
diff --git a/llvm/test/CodeGen/AMDGPU/loop_break.ll b/llvm/test/CodeGen/AMDGPU/loop_break.ll
index e90bde0f43f98..fcae73c763682 100644
--- a/llvm/test/CodeGen/AMDGPU/loop_break.ll
+++ b/llvm/test/CodeGen/AMDGPU/loop_break.ll
@@ -169,7 +169,7 @@ bb9:                                              ; preds = %Flow
 }
 
 ; FIXME: ConstantExpr compare of address to null folds away
-@lds = addrspace(3) global i32 undef
+@lds = addrspace(3) global i32 poison
 
 define amdgpu_kernel void @constexpr_phi_cond_break_loop(i32 %arg) #0 {
 ; OPT-LABEL: define amdgpu_kernel void @constexpr_phi_cond_break_loop(
diff --git a/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll b/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
index d2d15f5ca4577..bb09d3a670bc9 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa-merge.ll
@@ -2,8 +2,8 @@
 ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s
 ; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s
 
-@a = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
-@b = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
+@a = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 4
+@b = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 4
 
 define amdgpu_kernel void @no_clobber_ds_load_stores_x2_preexisting_aa(ptr addrspace(1) %arg, i32 %i) {
 ; CHECK-LABEL: define amdgpu_kernel void @no_clobber_ds_load_stores_x2_preexisting_aa(
diff --git a/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll b/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
index bf26344a1af79..24c1bfb8d50f0 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-lds-struct-aa.ll
@@ -2,9 +2,9 @@
 ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds < %s | FileCheck %s
 ; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds < %s | FileCheck %s
 
-@a = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
-@b = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
-@c = internal unnamed_addr addrspace(3) global [64 x i32] undef, align 4
+@a = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 4
+@b = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 4
+@c = internal unnamed_addr addrspace(3) global [64 x i32] poison, align 4
 
 ; FIXME: Should combine the DS instructions into ds_write2 and ds_read2. This
 ; does not happen because when SILoadStoreOptimizer is run, the reads and writes
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
index d96805656f72c..252c49eaa87b2 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-check-metadata.ll
@@ -6,7 +6,7 @@ target triple = "amdgcn-amd-amdhsa"
 ; CHECK:       .amdhsa_group_segment_fixed_size 4
 ; CHECK:       .end_amdhsa_kernel
 
-@global_barrier_state = hidden addrspace(3) global i32 undef, align 4
+@global_barrier_state = hidden addrspace(3) global i32 poison, align 4
 
 define i32 @rw() #0 {
 entry:
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll
index c81ea7fe3d2f7..1378cf1453693 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-constantexpr-phi.ll
@@ -2,7 +2,7 @@
 ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s
 ; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-module-lds --amdgpu-lower-module-lds-strategy=module < %s | FileCheck %s
 
-@var = addrspace(3) global i32 undef, align 4
+@var = addrspace(3) global i32 poison, align 4
 
 ; Regression test. Duplicate constantexpr in phi nodes shall not emit broken IR
 define amdgpu_kernel void @func(i32 %c) {
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll
index b5876204b3ffa..b2c30cd174c78 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-inactive.ll
@@ -8,9 +8,9 @@
 
 ; var1 is removed, var2 stays because it's in compiler.used
 ; CHECK-NOT: @var1
-; CHECK: @var2 = addrspace(3) global float undef
-@var1 = addrspace(3) global i32 undef
-@var2 = addrspace(3) global float undef
+; CHECK: @var2 = addrspace(3) global float poison
+@var1 = addrspace(3) global i32 poison
+@var2 = addrspace(3) global float poison
 
 ; constant variables are left to the optimizer / error diagnostics
 ; CHECK: @const_undef = addrspace(3) constant i32 undef
@@ -24,8 +24,8 @@
 @with_init = addrspace(3) global i64 0
 
 ; Only local addrspace variables are transformed
-; CHECK: @addr4 = addrspace(4) global i64 undef
-@addr4 = addrspace(4) global i64 undef
+; CHECK: @addr4 = addrspace(4) global i64 poison
+@addr4 = addrspace(4) global i64 poison
 
 ; Assign to self is treated as any other initializer, i.e. ignored by this pass
 ; CHECK: @toself = addrspace(3) global ptr addrspace(3) @toself, align 8
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
index b508ffff8050a..dba93a6b6069c 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll
@@ -6,8 +6,8 @@
 ; Check that module LDS is allocated at address 0 and kernel starts its
 ; allocation past module LDS when a call is present.
 
-@lds.size.1.align.1 = internal unnamed_addr addrspace(3) global [1 x i8] undef, align 1
-@lds.size.16.align.16 = internal unnamed_addr addrspace(3) global [16 x i8] undef, align 16
+@lds.size.1.align.1 = internal unnamed_addr addrspace(3) global [1 x i8] poison, align 1
+@lds.size.16.align.16 = internal unnamed_addr addrspace(3) global [16 x i8] poison, align 16
 
 ; GCN-LABEL: {{^}}f0:
 ; GCN-DAG: v_mov_b32_e32 [[NULL:v[0-9]+]], 0
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll
index bb2fc02f5af5e..bd95cdddd4613 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-ambiguous.ll
@@ -6,7 +6,7 @@
 
 ;; Two kernels access the same variable, specialisation gives them each their own copy of it
 
-@kernel.lds = addrspace(3) global i8 undef
+@kernel.lds = addrspace(3) global i8 poison
 define amdgpu_kernel void @k0() {
 ; CHECK-LABEL: @k0(
 ; CHECK-NEXT:    [[LD:%.*]] = load i8, ptr addrspace(3) @llvm.amdgcn.kernel.k0.lds, align 1
@@ -38,7 +38,7 @@ define amdgpu_kernel void @k1() {
 
 ; KERNEL: LLVM ERROR: cannot lower LDS 'function.lds' to kernel access as it is reachable from multiple kernels
 
-@function.lds = addrspace(3) global i16 undef
+@function.lds = addrspace(3) global i16 poison
 define void @f0() {
 ; M_OR_HY-LABEL: @f0(
 ; M_OR_HY-NEXT:    [[LD:%.*]] = load i16, ptr addrspace(3) @llvm.amdgcn.module.lds, align 2
diff --git a/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll b/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll
index 007e777d0a61d..96e8099ed59e1 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-module-lds-single-var-unambiguous.ll
@@ -9,7 +9,7 @@
 
 ;; Single kernel is sole user of single variable, all options codegen as direct access to kernel struct
 
-@k0.lds = addrspace(3) global i8 undef
+@k0.lds = addrspace(3) global i8 poison
 define amdgpu_kernel void @k0() {
 ; CHECK-LABEL: @k0(
 ; CHECK-NEXT:    [[LD:%.*]] = load i8, ptr addrspace(3) @llvm.amdgcn.kernel.k0.lds, align 1
@@ -25,7 +25,7 @@ define amdgpu_kernel void @k0() {
 
 ;; Function is reachable from one kernel. Variable goes in module lds or the kernel struct, but never both.
 
-@f0.lds = addrspace(3) global i16 undef
+@f0.lds = addrspace(3) global i16 poison
 define void @f0() {
 ; MODULE-LABEL: @f0(
 ; MODULE-NEXT:    [[LD:%.*]] = load i16, ptr addrspace(3) getelementptr inbounds ([[LLVM_AMDGCN_MODULE_LDS_T:%.*]], ptr addrspace(3) @llvm.amdgcn.module.lds, i32 0, i32 1), align 4, !alias.scope [[META1:![0-9]+]], !noalias [[META4:![0-9]+]]
@@ -80,7 +80,7 @@ define amdgpu_kernel void @k_f0() {
 
 ;; As above, but with the kernel also uing the variable.
 
-@both.lds = addrspace(3) global i32 undef
+@both.lds = addrspace(3) global i32 poison
 define void @f_both() {
 ; MODULE-LABEL: @f_both(
 ; MODULE-NEXT:    [[LD:%.*]] = load i32, ptr addrspace(3) @llvm.amdgcn.module.lds, align 4, !alias.scope [[META5]], !noalias [[META4]]
diff --git a/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll b/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
index 127656f7aa626..88ee2a34dd49f 100644
--- a/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
+++ b/llvm/test/CodeGen/AMDGPU/memcpy-libcall.ll
@@ -3,7 +3,7 @@
 
 %struct.S = type { [32 x i32] }
 
-@shared = addrspace(3) global %struct.S undef, align 4
+@shared = addrspace(3) global %struct.S poison, align 4
 
 define amdgpu_kernel void @memcpy_p0_p0_minsize(ptr %dest, ptr readonly %src) #0 {
 ; CHECK-LABEL: memcpy_p0_p0_minsize:
diff --git a/llvm/test/CodeGen/AMDGPU/missing-store.ll b/llvm/test/CodeGen/AMDGPU/missing-store.ll
index b97b852363393..4f066fdc858ef 100644
--- a/llvm/test/CodeGen/AMDGPU/missing-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/missing-store.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
 
-@ptr_load = addrspace(3) global ptr addrspace(4) undef, align 8
+@ptr_load = addrspace(3) global ptr addrspace(4) poison, align 8
 
 ; Make sure when the load from %ptr2 is folded the chain isn't lost,
 ; resulting in losing the store to gptr
diff --git a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
index 43e3a1fa29483..11d73732bbbc7 100644
--- a/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
+++ b/llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll
@@ -7,9 +7,9 @@
 ; Test case looks at the allocated offset of @used_by_both. It's at zero when
 ; allocated by itself, but at 8 when allocated in combination with the double.
 ; Redundantly also checks LDSByteSize.
-@used_by_both = addrspace(3) global i32 undef
-@used_by_kernel = addrspace(3) global i32 undef
-@used_by_function = addrspace(3) global double undef
+@used_by_both = addrspace(3) global i32 poison
+@used_by_kernel = addrspace(3) global i32 poison
+@used_by_function = addrspace(3) global double poison
 
 ; kernel that calls no functions and uses an LDS variable allocates only that
 ; variable, so accesses at at offset 0 and LDSByteSize is 4
diff --git a/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll b/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
index 7152ed4eb8d46..f731ed1e01ae3 100644
--- a/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
+++ b/llvm/test/CodeGen/AMDGPU/noclobber-barrier.ll
@@ -5,7 +5,7 @@
 ; Check that barrier or fence in between of loads is not considered a clobber
 ; for the purpose of converting vector loads into scalar.
 
-@LDS = linkonce_odr hidden local_unnamed_addr addrspace(3) global i32 undef
+@LDS = linkonce_odr hidden local_unnamed_addr addrspace(3) global i32 poison
 
 ; GCN-LABEL: {{^}}simple_barrier:
 ; GCN: s_load_dword s
diff --git a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
index f57fdf51e07d3..d1ab92e1d48ff 100644
--- a/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
+++ b/llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
@@ -343,7 +343,7 @@ define amdgpu_kernel void @used_101_sgprs() #10 {
 ; GFX1030W64: ; Occupancy: 16
 ; GFX10W32:   ; Occupancy: 16
 ; GFX1100:    ; Occupancy: 16
-@lds6552 = internal addrspace(3) global [6552 x i8] undef, align 4
+@lds6552 = internal addrspace(3) global [6552 x i8] poison, align 4
 define amdgpu_kernel void @used_lds_6552() {
   store volatile i8 1, ptr addrspace(3) @lds6552
   ret void
@@ -355,7 +355,7 @@ define amdgpu_kernel void @used_lds_6552() {
 ; GFX1030W64: ; Occupancy: 16
 ; GFX10W32:   ; Occupancy: 16
 ; GFX1100:    ; Occupancy: 16
-@lds6556 = internal addrspace(3) global [6556 x i8] undef, align 4
+@lds6556 = internal addrspace(3) global [6556 x i8] poison, align 4
 define amdgpu_kernel void @used_lds_6556() {
   store volatile i8 1, ptr addrspace(3) @lds6556
   ret void
@@ -367,7 +367,7 @@ define amdgpu_kernel void @used_lds_6556() {
 ; GFX1030W64: ; Occupancy: 16
 ; GFX10W32:   ; Occupancy: 16
 ; GFX1100:    ; Occupancy: 16
-@lds13112 = internal addrspace(3) global [13112 x i8] undef, align 4
+@lds13112 = internal addrspace(3) global [13112 x i8] poison, align 4
 define amdgpu_kernel void @used_lds_13112() {
   store volatile i8 1, ptr addrspace(3) @lds13112
   ret void
@@ -379,7 +379,7 @@ define amdgpu_kernel void @used_lds_13112() {
 ; GFX10W32:   ; Occupancy: 8{{$}}
 ; GFX1100W64: ; Occupancy: 4{{$}}
 ; GFX1100W32: ; Occupancy: 8{{$}}
-@lds8252 = internal addrspace(3) global [8252 x i8] undef, align 4
+@lds8252 = internal addrspace(3) global [8252 x i8] poison, align 4
 define amdgpu_kernel void @used_lds_8252_max_group_size_64() #3 {
   store volatile i8 1, ptr addrspace(3) @lds8252
   ret void
diff --git a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
index 538ce15979de8..88d2f6a2e85ef 100644
--- a/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
+++ b/llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
@@ -284,7 +284,7 @@ define amdgpu_gfx float @simple_stack_recurse(float %arg0) #0 {
   ret float %add
 }
 
-@lds = internal addrspace(3) global [64 x float] undef
+@lds = internal addrspace(3) global [64 x float] poison
 
 define amdgpu_gfx float @simple_lds(float %arg0) #0 {
   %val = load float, ptr addrspace(3) @lds
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll
index 86036fbf672b2..0f5bf84bf4b8a 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-globals.ll
@@ -2,8 +2,8 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=ASM %s
 
 
-@global_array0 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4
-@global_array1 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4
+@global_array0 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] poison, align 4
+@global_array1 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] poison, align 4
 
 ; IR-LABEL: define amdgpu_kernel void @promote_alloca_size_256(ptr addrspace(1) captures(none) %out, ptr addrspace(1) captures(none) %in) {
 ; IR-NOT: alloca [10 x i32]
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
index 20a8cfc2a2799..e29552a9e4f5a 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll
@@ -25,9 +25,9 @@
 ; optimally packed, this requires
 
 
-@lds0 = internal unnamed_addr addrspace(3) global [32 x <4 x i32>] undef, align 16
-@lds2 = internal unnamed_addr addrspace(3) global [32 x i64] undef, align 8
-@lds1 = internal unnamed_addr addrspace(3) global [73 x i32] undef, align 4
+@lds0 = internal unnamed_addr addrspace(3) global [32 x <4 x i32>] poison, align 16
+@lds2 = internal unnamed_addr addrspace(3) global [32 x i64] poison, align 8
+@lds1 = internal unnamed_addr addrspace(3) global [73 x i32] poison, align 4
 
 
 ; GCN-LABEL: {{^}}promote_alloca_size_order_0:
@@ -92,8 +92,8 @@ entry:
   ret void
 }
 
-@lds3 = internal unnamed_addr addrspace(3) global [13 x i32] undef, align 4
-@lds4 = internal unnamed_addr addrspace(3) global [63 x <4 x i32>] undef, align 16
+@lds3 = internal unnamed_addr addrspace(3) global [13 x i32] poison, align 4
+@lds4 = internal unnamed_addr addrspace(3) global [63 x <4 x i32>] poison, align 16
 
 ; The guess from the alignment padding pushes this over the determined
 ; size limit, so it isn't promoted
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll
index 01d3f2cf08276..25fa469371d80 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-to-lds-constantexpr-use.ll
@@ -3,8 +3,8 @@
 
 target datalayout = "A5"
 
-@all_lds = internal unnamed_addr addrspace(3) global [16384 x i32] undef, align 4
-@some_lds = internal unnamed_addr addrspace(3) global [32 x i32] undef, align 4
+@all_lds = internal unnamed_addr addrspace(3) global [16384 x i32] poison, align 4
+@some_lds = internal unnamed_addr addrspace(3) global [32 x i32] poison, align 4
 @some_dynamic_lds = external hidden addrspace(3) global [0 x i32], align 4
 
 @initializer_user_some = addrspace(1) global i32 ptrtoint (ptr addrspace(3) @some_lds to i32), align 4
diff --git a/llvm/test/CodeGen/AMDGPU/promote-kernel-arguments.ll b/llvm/test/CodeGen/AMDGPU/promote-kernel-arguments.ll
index 8247f883661af..0696cbe5aa891 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-kernel-arguments.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-kernel-arguments.ll
@@ -72,7 +72,7 @@ entry:
   ret void
 }
 
-@LDS = internal unnamed_addr addrspace(3) global [4 x float] undef, align 16
+@LDS = internal unnamed_addr addrspace(3) global [4 x float] poison, align 16
 
 ; GCN-LABEL: flat_ptr_arg:
 ; GCN-COUNT-2: global_load_dwordx2
diff --git a/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll b/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
index cbd1714a5e375..ef91be9366b02 100644
--- a/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
+++ b/llvm/test/CodeGen/AMDGPU/resource-optimization-remarks.ll
@@ -103,7 +103,7 @@
 ; REMARK-NEXT:   - BytesLDS:        '512'
 ; REMARK-NEXT: ...
 
-@lds = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4
+@lds = internal unnamed_addr addrspace(3) global [128 x i32] poison, align 4
 
 define amdgpu_kernel void @test_kernel() !dbg !3 {
   call void asm sideeffect "; clobber v8", "~{v8}"()
diff --git a/llvm/test/CodeGen/AMDGPU/s_addk_i32.ll b/llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
index 78ea3b3699f2a..3140511f99678 100644
--- a/llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/s_addk_i32.ll
@@ -103,7 +103,7 @@ define amdgpu_kernel void @no_s_addk_i32_k0(ptr addrspace(1) %out, i32 %b) #0 {
   ret void
 }
 
-@lds = addrspace(3) global [512 x i32] undef, align 4
+@lds = addrspace(3) global [512 x i32] poison, align 4
 
 ; SI-LABEL: {{^}}commute_s_addk_i32:
 ; SI: s_addk_i32 s{{[0-9]+}}, 0x800{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll b/llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
index b00e9dacfde36..d54edbc3d5ebd 100644
--- a/llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll
@@ -118,7 +118,7 @@ define amdgpu_kernel void @no_s_mulk_i32_k0(ptr addrspace(1) %out, i32 %b) {
   ret void
 }
 
-@lds = addrspace(3) global [512 x i32] undef, align 4
+@lds = addrspace(3) global [512 x i32] poison, align 4
 
 define amdgpu_kernel void @commute_s_mulk_i32(ptr addrspace(1) %out, i32 %b) #0 {
 ; GFX6-LABEL: commute_s_mulk_i32:
diff --git a/llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll b/llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
index 12f86cd064ffa..b3eb3056fdd94 100644
--- a/llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
+++ b/llvm/test/CodeGen/AMDGPU/schedule-regpressure-lds.ll
@@ -7,7 +7,7 @@
 ; which (incorrectly) used to look to the scheduler like an occupancy reduction.
 
 ; 6 kB of LDS, allows 10 workgroups
-@lds = internal addrspace(3) global [384 x <4 x i32>] undef
+@lds = internal addrspace(3) global [384 x <4 x i32>] poison
 
 define internal amdgpu_gfx void @copy(ptr addrspace(1) %src, i32 %ofs) alwaysinline {
   %src.gep = getelementptr <4 x i32>, ptr addrspace(1) %src, i32 %ofs
diff --git a/llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll b/llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
index 9127cc3ffb34e..fe838872169c6 100644
--- a/llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
@@ -9,8 +9,8 @@
 
 declare i32 @llvm.amdgcn.workitem.id.x() #1
 
-@lds0 = addrspace(3) global [512 x float] undef, align 4
-@lds1 = addrspace(3) global [512 x float] undef, align 4
+@lds0 = addrspace(3) global [512 x float] poison, align 4
+@lds1 = addrspace(3) global [512 x float] poison, align 4
 
 
 ; Make sure the (add tid, 2) << 2 gets folded into the ds's offset as (tid << 2) + 8
@@ -50,7 +50,7 @@ define amdgpu_kernel void @load_shl_base_lds_1(ptr addrspace(1) %out, ptr addrsp
   ret void
 }
 
-@maxlds = addrspace(3) global [65536 x i8] undef, align 4
+@maxlds = addrspace(3) global [65536 x i8] poison, align 4
 
 ; GCN-LABEL: {{^}}load_shl_base_lds_max_offset
 ; GCN: ds_read_u8 v{{[0-9]+}}, v{{[0-9]+}} offset:65535
@@ -102,7 +102,7 @@ define amdgpu_kernel void @store_shl_base_lds_0(ptr addrspace(1) %out, ptr addrs
 ; --------------------------------------------------------------------------------
 ; Atomics.
 
-@lds2 = addrspace(3) global [512 x i32] undef, align 4
+@lds2 = addrspace(3) global [512 x i32] poison, align 4
 
 ; define amdgpu_kernel void @atomic_load_shl_base_lds_0(ptr addrspace(1) %out, ptr addrspace(1) %add_use) #0 {
 ;   %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
diff --git a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
index 96757d39fc8f5..db7ab57d80ed9 100644
--- a/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
+++ b/llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
@@ -2,9 +2,9 @@
 ; RUN: llc -amdgpu-scalarize-global-loads=false  -mtriple=amdgcn -mcpu=gfx900 -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
 
 %struct.lds = type { [64 x ptr], [16 x i8] }
-@stored_lds_struct = addrspace(3) global %struct.lds undef, align 16
+@stored_lds_struct = addrspace(3) global %struct.lds poison, align 16
 @stored_lds_ptr = addrspace(3) global ptr addrspace(3) poison, align 4
-@stored_constant_ptr = addrspace(3) global ptr addrspace(4) undef, align 8
+@stored_constant_ptr = addrspace(3) global ptr addrspace(4) poison, align 8
 @stored_global_ptr = addrspace(3) global ptr addrspace(1) poison, align 8
 
 ; GCN-LABEL: {{^}}no_reorder_flat_load_local_store_local_load:
diff --git a/llvm/test/CodeGen/AMDGPU/sopk-compares.ll b/llvm/test/CodeGen/AMDGPU/sopk-compares.ll
index c54832d778434..84aab5229abab 100644
--- a/llvm/test/CodeGen/AMDGPU/sopk-compares.ll
+++ b/llvm/test/CodeGen/AMDGPU/sopk-compares.ll
@@ -5,7 +5,7 @@
 ; defeat the DAG's compare with constant canonicalizations.
 declare i32 @llvm.amdgcn.groupstaticsize() #1
 
-@lds = addrspace(3) global [512 x i32] undef, align 4
+@lds = addrspace(3) global [512 x i32] poison, align 4
 
 ; GCN-LABEL: {{^}}br_scc_eq_i32_inline_imm:
 ; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 4{{$}}
diff --git a/llvm/test/CodeGen/AMDGPU/spill-m0.ll b/llvm/test/CodeGen/AMDGPU/spill-m0.ll
index 808e356580891..775a5aed95a73 100644
--- a/llvm/test/CodeGen/AMDGPU/spill-m0.ll
+++ b/llvm/test/CodeGen/AMDGPU/spill-m0.ll
@@ -48,7 +48,7 @@ endif:
   ret void
 }
 
-@lds = internal addrspace(3) global [64 x float] undef
+@lds = internal addrspace(3) global [64 x float] poison
 
 ; m0 is killed, so it isn't necessary during the entry block spill to preserve it
 ; GCN-LABEL: {{^}}spill_kill_m0_lds:
diff --git a/llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll b/llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
index a5dcd9284edd0..a6366cc78f85a 100644
--- a/llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
+++ b/llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -mtriple=amdgcn -mcpu=hawaii -enable-amdgpu-aa=0 -verify-machineinstrs -mattr=-promote-alloca,-load-store-opt,-enable-ds128 < %s | FileCheck -check-prefix=GCN %s
 
-@sPrivateStorage = internal addrspace(3) global [256 x [8 x <4 x i64>]] undef
+@sPrivateStorage = internal addrspace(3) global [256 x [8 x <4 x i64>]] poison
 
 ; GCN-LABEL: {{^}}ds_reorder_vector_split:
 
diff --git a/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll b/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
index ef11bfdc992e4..16ac8da7305c1 100644
--- a/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
@@ -20,7 +20,7 @@ entry:
 
 
 declare i32 @llvm.amdgcn.workitem.id.x()
-@lds0 = addrspace(3) global [512 x i32] undef, align 4
+@lds0 = addrspace(3) global [512 x i32] poison, align 4
 
 ; To check that %arrayidx0 is not marked as amdgpu.noclobber.
 
diff --git a/llvm/test/CodeGen/AMDGPU/sub.i16.ll b/llvm/test/CodeGen/AMDGPU/sub.i16.ll
index 2b1577e832051..93a71082b345e 100644
--- a/llvm/test/CodeGen/AMDGPU/sub.i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sub.i16.ll
@@ -144,7 +144,7 @@ define amdgpu_kernel void @v_test_sub_i16_sext_to_i64(ptr addrspace(1) %out, ptr
   ret void
 }
 
-@lds = addrspace(3) global [512 x i32] undef, align 4
+@lds = addrspace(3) global [512 x i32] poison, align 4
 
 ; GCN-LABEL: {{^}}v_test_sub_i16_constant_commute:
 ; VI: v_subrev_u16_e32 v{{[0-9]+}}, 0x800, v{{[0-9]+}}