diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 5f268006c6fdd..099490173bf08 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -197,6 +197,16 @@ DecodeGPRNoX0X2RegisterClass(MCInst &Inst, uint64_t RegNo, uint32_t Address, return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder); } +static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo, + uint64_t Address, + const MCDisassembler *Decoder) { + if (RegNo == 31) { + return MCDisassembler::Fail; + } + + return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); +} + static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 23feb52a0c2ca..2479bbd1258a4 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -584,15 +584,15 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { def QC_INSBPR : QCIRVInstRR<0b00010, GPR, "qc.insbpr">; def QC_INSBPRH : QCIRVInstRR<0b00011, GPR, "qc.insbprh">; def QC_EXTU : QCIBitManipRII<0b010, 0b00, GPRNoX0, "qc.extu">; - def QC_EXTDU : QCIBitManipRII<0b010, 0b10, GPR, "qc.extdu">; - def QC_EXTDUR : QCIRVInstRR<0b00100, GPR, "qc.extdur">; - def QC_EXTDUPR : QCIRVInstRR<0b00110, GPR, "qc.extdupr">; - def QC_EXTDUPRH : QCIRVInstRR<0b00111, GPR, "qc.extduprh">; + def QC_EXTDU : QCIBitManipRII<0b010, 0b10, GPRNoX31, "qc.extdu">; + def QC_EXTDUR : QCIRVInstRR<0b00100, GPRNoX31, "qc.extdur">; + def QC_EXTDUPR : QCIRVInstRR<0b00110, GPRNoX31, "qc.extdupr">; + def QC_EXTDUPRH : QCIRVInstRR<0b00111, GPRNoX31, "qc.extduprh">; def QC_EXT : QCIBitManipRII<0b010, 0b01, GPRNoX0, "qc.ext">; - def QC_EXTD : QCIBitManipRII<0b010, 0b11, GPR, "qc.extd">; - def QC_EXTDR : QCIRVInstRR<0b00101, GPR, "qc.extdr">; - def QC_EXTDPR : QCIRVInstRR<0b01000, GPR, "qc.extdpr">; - def QC_EXTDPRH : QCIRVInstRR<0b01001, GPR, "qc.extdprh">; + def QC_EXTD : QCIBitManipRII<0b010, 0b11, GPRNoX31, "qc.extd">; + def QC_EXTDR : QCIRVInstRR<0b00101, GPRNoX31, "qc.extdr">; + def QC_EXTDPR : QCIRVInstRR<0b01000, GPRNoX31, "qc.extdpr">; + def QC_EXTDPRH : QCIRVInstRR<0b01001, GPRNoX31, "qc.extdprh">; def QC_COMPRESS2 : QCIRVInstI<0b0000, "qc.compress2">; def QC_COMPRESS3 : QCIRVInstI<0b0001, "qc.compress3">; def QC_EXPAND2 : QCIRVInstI<0b0010, "qc.expand2">; diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td index 2332260ff1ca6..8d09caf1da2d5 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td @@ -302,6 +302,11 @@ def GPRX1X5 : GPRRegisterClass<(add X1, X5)> { let DiagnosticString = "register must be ra or t0 (x1 or x5)"; } +def GPRNoX31 : GPRRegisterClass<(sub GPR, X31)> { + let DiagnosticType = "InvalidRegClassGPRX31"; + let DiagnosticString = "register must be a GPR excluding t6 (x31)"; +} + //===----------------------------------------------------------------------===// // Even-Odd GPR Pairs //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir index f65bba1b7b9c7..fc3bb13df77d6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-zve64f.mir @@ -24,7 +24,7 @@ body: | ; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, [[COPY1]], 1, 6 /* e64 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 8) ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, [[COPY]], 8, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 4) - ; CHECK-NEXT: INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3145737 /* reguse:VR */, killed renamable $v10, 3145737 /* reguse:VR */, killed renamable $v11, 3145737 /* reguse:VR */, killed renamable $v8, 3145737 /* reguse:VR */, killed renamable $v9 + ; CHECK-NEXT: INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3997705 /* reguse:VR */, killed renamable $v10, 3997705 /* reguse:VR */, killed renamable $v11, 3997705 /* reguse:VR */, killed renamable $v8, 3997705 /* reguse:VR */, killed renamable $v9 ; CHECK-NEXT: PseudoRET %3:gpr = COPY $x12 %2:gpr = COPY $x11 @@ -34,7 +34,7 @@ body: | renamable $v11 = PseudoVMV_S_X undef renamable $v11, %1, 8, 5 /* e32 */ renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, %2, 1, 6 /* e64 */, 2 /* tu, ma */ :: (load unknown-size, align 8) renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, %3, 8, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 4) - INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3145737 /* reguse:VR */, killed renamable $v10, 3145737 /* reguse:VR */, killed renamable $v11, 3145737 /* reguse:VR */, killed renamable $v8, 3145737 /* reguse:VR */, killed renamable $v9 + INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3997705 /* reguse:VR */, killed renamable $v10, 3997705 /* reguse:VR */, killed renamable $v11, 3997705 /* reguse:VR */, killed renamable $v8, 3997705 /* reguse:VR */, killed renamable $v9 PseudoRET ... diff --git a/llvm/test/MC/RISCV/xqcibm-invalid.s b/llvm/test/MC/RISCV/xqcibm-invalid.s index 7bb305fa9fa30..6ed3ec4c7f65c 100644 --- a/llvm/test/MC/RISCV/xqcibm-invalid.s +++ b/llvm/test/MC/RISCV/xqcibm-invalid.s @@ -269,7 +269,8 @@ qc.ext x27, x6, 31, 41 qc.ext x27, x6, 31, 1 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding t6 (x31) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.extdu x1, 8, 8, 8 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -289,7 +290,8 @@ qc.extdu x1, x8, 8, 78 qc.extdu x1, x8, 8, 8 -# CHECK: :[[@LINE+1]]:14: error: invalid operand for instruction +# CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding t6 (x31) +# CHECK-MINUS: :[[@LINE+1]]:14: error: invalid operand for instruction qc.extd x13, 21, 10, 15 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction @@ -396,6 +398,10 @@ qc.extdur x9, x19 # CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.extdur x0, x19, x29 +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding t6 (x31) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction +qc.extdur x9, x31, x29 + # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) # CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction qc.extdur x9, x19, x0 @@ -406,21 +412,25 @@ qc.extdur x9, x19, x29 # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) # CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction -qc.extdr x12, x31, 30 +qc.extdr x12, x29, 30 # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction -qc.extdr x12, x31 +qc.extdr x12, x29 # CHECK-PLUS: :[[@LINE+2]]:10: error: register must be a GPR excluding zero (x0) # CHECK-MINUS: :[[@LINE+1]]:10: error: invalid operand for instruction -qc.extdr x0, x31, x30 +qc.extdr x0, x29, x30 + +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding t6 (x31) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction +qc.extdr x12, x31, x30 # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) # CHECK-MINUS: :[[@LINE+1]]:20: error: invalid operand for instruction -qc.extdr x12, x31, x0 +qc.extdr x12, x29, x0 # CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcibm' (Qualcomm uC Bit Manipulation Extension) -qc.extdr x12, x31, x30 +qc.extdr x12, x29, x30 # CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero (x0) @@ -434,6 +444,10 @@ qc.extdupr x13, x23 # CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction qc.extdupr x0, x23, x3 +# CHECK-PLUS: :[[@LINE+2]]:17: error: register must be a GPR excluding t6 (x31) +# CHECK-MINUS: :[[@LINE+1]]:17: error: invalid operand for instruction +qc.extdupr x13, x31, x3 + # CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero (x0) # CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction qc.extdupr x13, x23, x0 @@ -453,6 +467,10 @@ qc.extduprh x18, x8 # CHECK-MINUS: :[[@LINE+1]]:13: error: invalid operand for instruction qc.extduprh x0, x8, x9 +# CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding t6 (x31) +# CHECK-MINUS: :[[@LINE+1]]:18: error: invalid operand for instruction +qc.extduprh x18, x31, x9 + # CHECK-PLUS: :[[@LINE+2]]:22: error: register must be a GPR excluding zero (x0) # CHECK-MINUS: :[[@LINE+1]]:22: error: invalid operand for instruction qc.extduprh x18, x8, x0 @@ -472,6 +490,10 @@ qc.extdpr x1, x4 # CHECK-MINUS: :[[@LINE+1]]:11: error: invalid operand for instruction qc.extdpr x0, x4, x15 +# CHECK-PLUS: :[[@LINE+2]]:15: error: register must be a GPR excluding t6 (x31) +# CHECK-MINUS: :[[@LINE+1]]:15: error: invalid operand for instruction +qc.extdpr x1, x31, x15 + # CHECK-PLUS: :[[@LINE+2]]:19: error: register must be a GPR excluding zero (x0) # CHECK-MINUS: :[[@LINE+1]]:19: error: invalid operand for instruction qc.extdpr x1, x4, x0 @@ -491,6 +513,10 @@ qc.extdprh x6, x24 # CHECK-MINUS: :[[@LINE+1]]:12: error: invalid operand for instruction qc.extdprh x0, x24, x25 +# CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding t6 (x31) +# CHECK-MINUS: :[[@LINE+1]]:16: error: invalid operand for instruction +qc.extdprh x6, x31, x25 + # CHECK-PLUS: :[[@LINE+2]]:21: error: register must be a GPR excluding zero (x0) # CHECK-MINUS: :[[@LINE+1]]:21: error: invalid operand for instruction qc.extdprh x6, x24, x0 diff --git a/llvm/test/MC/RISCV/xqcibm-valid.s b/llvm/test/MC/RISCV/xqcibm-valid.s index d5603c6d52c90..70248ad00cb76 100644 --- a/llvm/test/MC/RISCV/xqcibm-valid.s +++ b/llvm/test/MC/RISCV/xqcibm-valid.s @@ -90,9 +90,9 @@ qc.insbprh x2, x3, x11 # CHECK-ENC: encoding: [0x8b,0xb4,0xd9,0x09] qc.extdur x9, x19, x29 -# CHECK-INST: qc.extdr a2, t6, t5 -# CHECK-ENC: encoding: [0x0b,0xb6,0xef,0x0b] -qc.extdr x12, x31, x30 +# CHECK-INST: qc.extdr a2, t4, t5 +# CHECK-ENC: encoding: [0x0b,0xb6,0xee,0x0b] +qc.extdr x12, x29, x30 # CHECK-INST: qc.extdupr a3, s7, gp # CHECK-ENC: encoding: [0x8b,0xb6,0x3b,0x0c]