diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 0eb55daf32089..fd39b8a1350c6 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -842,10 +842,7 @@ bool SIShrinkInstructions::run(MachineFunction &MF) { unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; - for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); - BI != BE; ++BI) { - - MachineBasicBlock &MBB = *BI; + for (MachineBasicBlock &MBB : MF) { MachineBasicBlock::iterator I, Next; for (I = MBB.begin(); I != MBB.end(); I = Next) { Next = std::next(I); diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 8f17c62d4b906..50217c3a047df 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -3126,8 +3126,8 @@ bool ARMBaseInstrInfo::optimizeCompareInstr( // Modify the condition code of operands in OperandsToUpdate. // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc. - for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++) - OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second); + for (auto &[MO, Cond] : OperandsToUpdate) + MO->setImm(Cond); MI->clearRegisterDeads(ARM::CPSR); diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index ca3dc15ff3ad6..e72aa8ef051cd 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -476,8 +476,8 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n'); bool BRChange = false; - for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i) - BRChange |= fixupImmediateBr(ImmBranches[i]); + for (ImmBranch &Br : ImmBranches) + BRChange |= fixupImmediateBr(Br); if (BRChange && ++NoBRIters > 30) report_fatal_error("Branch Fix Up pass failed to converge!"); LLVM_DEBUG(dumpBBs()); diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 80805ff34e1bd..74a75a868cde0 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -1701,8 +1701,8 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, .addReg(ARM::SP) .setMIFlags(MachineInstr::FrameSetup) .add(predOps(ARMCC::AL)); - for (unsigned i = 0, e = Regs.size(); i < e; ++i) - MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); + for (const auto [Reg, Kill] : Regs) + MIB.addReg(Reg, getKillRegState(Kill)); } else if (Regs.size() == 1) { BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP) .addReg(Regs[0].first, getKillRegState(Regs[0].second)) diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index d8fcf9d10d74c..40ca525757adc 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2766,9 +2766,8 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Build a sequence of copy-to-reg nodes chained together with token chain // and flag operands which copy the outgoing args into the appropriate regs. SDValue InGlue; - for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, - RegsToPass[i].second, InGlue); + for (const auto [Reg, N] : RegsToPass) { + Chain = DAG.getCopyToReg(Chain, dl, Reg, N, InGlue); InGlue = Chain.getValue(1); } @@ -2952,9 +2951,8 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Add argument registers to the end of the list so that they are known live // into the call. - for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) - Ops.push_back(DAG.getRegister(RegsToPass[i].first, - RegsToPass[i].second.getValueType())); + for (const auto [Reg, N] : RegsToPass) + Ops.push_back(DAG.getRegister(Reg, N.getValueType())); // Add a register mask operand representing the call-preserved registers. const uint32_t *Mask; diff --git a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp index 1aa00d4f09f75..48f11be135ffe 100644 --- a/llvm/lib/Target/X86/X86ISelLoweringCall.cpp +++ b/llvm/lib/Target/X86/X86ISelLoweringCall.cpp @@ -1929,9 +1929,9 @@ SDValue X86TargetLowering::LowerFormalArguments( } if (CallingConv::PreserveNone == CallConv) - for (unsigned I = 0, E = Ins.size(); I != E; ++I) { - if (Ins[I].Flags.isSwiftSelf() || Ins[I].Flags.isSwiftAsync() || - Ins[I].Flags.isSwiftError()) { + for (const ISD::InputArg &In : Ins) { + if (In.Flags.isSwiftSelf() || In.Flags.isSwiftAsync() || + In.Flags.isSwiftError()) { errorUnsupported(DAG, dl, "Swift attributes can't be used with preserve_none"); break; @@ -2421,9 +2421,8 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Build a sequence of copy-to-reg nodes chained together with token chain // and glue operands which copy the outgoing args into registers. SDValue InGlue; - for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, - RegsToPass[i].second, InGlue); + for (const auto [Reg, N] : RegsToPass) { + Chain = DAG.getCopyToReg(Chain, dl, Reg, N, InGlue); InGlue = Chain.getValue(1); } @@ -2462,9 +2461,8 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Add argument registers to the end of the list so that they are known live // into the call. - for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) - Ops.push_back(DAG.getRegister(RegsToPass[i].first, - RegsToPass[i].second.getValueType())); + for (const auto [Reg, N] : RegsToPass) + Ops.push_back(DAG.getRegister(Reg, N.getValueType())); // Add a register mask operand representing the call-preserved registers. const uint32_t *Mask = [&]() { @@ -2615,9 +2613,9 @@ X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } if (CallingConv::PreserveNone == CallConv) - for (unsigned I = 0, E = Outs.size(); I != E; ++I) { - if (Outs[I].Flags.isSwiftSelf() || Outs[I].Flags.isSwiftAsync() || - Outs[I].Flags.isSwiftError()) { + for (const ISD::OutputArg &Out : Outs) { + if (Out.Flags.isSwiftSelf() || Out.Flags.isSwiftAsync() || + Out.Flags.isSwiftError()) { errorUnsupported(DAG, dl, "Swift attributes can't be used with preserve_none"); break;