diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4f137756d2f48..bc8ed2342930b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -22495,6 +22495,7 @@ RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
            "ReadCounterWide is only to be used on riscv32");
     return emitReadCounterWidePseudo(MI, BB);
   case RISCV::Select_GPR_Using_CC_GPR:
+  case RISCV::Select_GPR_Using_CC_Imm5_Zibi:
   case RISCV::Select_GPR_Using_CC_SImm5_CV:
   case RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC:
   case RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index d0bb57a3eaa13..ae5d288d09c52 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -955,6 +955,7 @@ RISCVCC::CondCode RISCVInstrInfo::getCondFromBranchOpc(unsigned Opc) {
   default:
     return RISCVCC::COND_INVALID;
   case RISCV::BEQ:
+  case RISCV::BEQI:
   case RISCV::CV_BEQIMM:
   case RISCV::QC_BEQI:
   case RISCV::QC_E_BEQI:
@@ -962,6 +963,7 @@ RISCVCC::CondCode RISCVInstrInfo::getCondFromBranchOpc(unsigned Opc) {
   case RISCV::NDS_BEQC:
     return RISCVCC::COND_EQ;
   case RISCV::BNE:
+  case RISCV::BNEI:
   case RISCV::QC_BNEI:
   case RISCV::QC_E_BNEI:
   case RISCV::CV_BNEIMM:
@@ -1041,6 +1043,16 @@ unsigned RISCVCC::getBrCond(RISCVCC::CondCode CC, unsigned SelectOpc) {
       return RISCV::BGEU;
     }
     break;
+  case RISCV::Select_GPR_Using_CC_Imm5_Zibi:
+    switch (CC) {
+    default:
+      llvm_unreachable("Unexpected condition code!");
+    case RISCVCC::COND_EQ:
+      return RISCV::BEQI;
+    case RISCVCC::COND_NE:
+      return RISCV::BNEI;
+    }
+    break;
   case RISCV::Select_GPR_Using_CC_SImm5_CV:
     switch (CC) {
     default:
@@ -1359,9 +1371,15 @@ bool RISCVInstrInfo::reverseBranchCondition(
   case RISCV::BEQ:
     Cond[0].setImm(RISCV::BNE);
     break;
+  case RISCV::BEQI:
+    Cond[0].setImm(RISCV::BNEI);
+    break;
   case RISCV::BNE:
     Cond[0].setImm(RISCV::BEQ);
     break;
+  case RISCV::BNEI:
+    Cond[0].setImm(RISCV::BEQI);
+    break;
   case RISCV::BLT:
     Cond[0].setImm(RISCV::BGE);
     break;
@@ -1611,6 +1629,8 @@ bool RISCVInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
   case RISCV::BGE:
   case RISCV::BLTU:
   case RISCV::BGEU:
+  case RISCV::BEQI:
+  case RISCV::BNEI:
   case RISCV::CV_BEQIMM:
   case RISCV::CV_BNEIMM:
   case RISCV::QC_BEQI:
@@ -2859,6 +2879,9 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
         case RISCVOp::OPERAND_FOUR:
           Ok = Imm == 4;
           break;
+        case RISCVOp::OPERAND_IMM5_ZIBI:
+          Ok = (isUInt<5>(Imm) && Imm != 0) || Imm == -1;
+          break;
           // clang-format off
         CASE_OPERAND_SIMM(5)
         CASE_OPERAND_SIMM(6)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
index 1570355e3da54..412bb08b00929 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZibi.td
@@ -42,3 +42,24 @@ let Predicates = [HasStdExtZibi] in {
   def BEQI : Branch_imm<0b010, "beqi">;
   def BNEI : Branch_imm<0b011, "bnei">;
 } // Predicates = [HasStdExtZibi]
+
+multiclass BccImmPat<CondCode Cond, Branch_imm Inst> {
+  def : Pat<(riscv_brcc (XLenVT GPR:$rs1), imm5_zibi:$cimm, Cond, bb:$imm12),
+            (Inst GPR:$rs1, imm5_zibi:$cimm, bare_simm13_lsb0_bb:$imm12)>;
+}
+
+defm CC_Imm5_Zibi : SelectCC_GPR_riirr<GPR, imm5_zibi>;
+
+class SelectZibi<CondCode Cond>
+    : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), imm5_zibi:$cimm, Cond,
+              (XLenVT GPR:$truev), GPR:$falsev),
+          (Select_GPR_Using_CC_Imm5_Zibi GPR:$lhs, imm5_zibi:$cimm,
+              (IntCCtoRISCVCC $cc), GPR:$truev, GPR:$falsev)>;
+
+let Predicates = [HasStdExtZibi] in {
+  def : SelectZibi<SETEQ>;
+  def : SelectZibi<SETNE>;
+
+  defm : BccImmPat<SETEQ, BEQI>;
+  defm : BccImmPat<SETNE, BNEI>;
+} // Predicates = [HasStdExtZibi]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
index 06309262f1b08..6d86aff581604 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -49,6 +49,7 @@ def isSelectPseudo
                    MCReturnStatement<
                      CheckOpcode<[
                        Select_GPR_Using_CC_GPR,
+                       Select_GPR_Using_CC_Imm5_Zibi,
                        Select_GPR_Using_CC_SImm5_CV,
                        Select_GPRNoX0_Using_CC_SImm5NonZero_QC,
                        Select_GPRNoX0_Using_CC_UImm5NonZero_QC,
diff --git a/llvm/test/CodeGen/RISCV/zibi.ll b/llvm/test/CodeGen/RISCV/zibi.ll
new file mode 100644
index 0000000000000..ed6c2e52e0967
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/zibi.ll
@@ -0,0 +1,442 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi -verify-machineinstrs < %s \
+; RUN:     | FileCheck -check-prefixes=ZIBI,ZIBI-RV32 %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zibi -verify-machineinstrs < %s \
+; RUN:     | FileCheck -check-prefixes=ZIBI,ZIBI-RV64 %s
+
+define void @test_bne_neg(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_neg:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    bnei a1, -1, .LBB0_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB0_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp ne i32 %val1, -1
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+
+define void @test_beq_neg(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_neg:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    beqi a1, -1, .LBB1_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB1_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp eq i32 %val1, -1
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+
+define void @test_bne_zero(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_zero:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    bnez a1, .LBB2_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB2_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp ne i32 %val1, 0
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+
+define void @test_beq_zero(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_zero:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    beqz a1, .LBB3_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB3_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp eq i32 %val1, 0
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+
+define void @test_bne_1(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_1:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    bnei a1, 1, .LBB4_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB4_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp ne i32 %val1, 1
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+
+define void @test_beq_1(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_1:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    beqi a1, 1, .LBB5_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB5_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp eq i32 %val1, 1
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+
+define void @test_bne_31(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_31:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    bnei a1, 31, .LBB6_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB6_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp ne i32 %val1, 31
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+
+define void @test_beq_31(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_31:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    beqi a1, 31, .LBB7_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB7_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp eq i32 %val1, 31
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+
+define void @test_bne_32(ptr %b) nounwind {
+; ZIBI-LABEL: test_bne_32:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    li a2, 32
+; ZIBI-NEXT:    bne a1, a2, .LBB8_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB8_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp ne i32 %val1, 32
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+
+define void @test_beq_32(ptr %b) nounwind {
+; ZIBI-LABEL: test_beq_32:
+; ZIBI:       # %bb.0:
+; ZIBI-NEXT:    lw a1, 0(a0)
+; ZIBI-NEXT:    li a2, 32
+; ZIBI-NEXT:    beq a1, a2, .LBB9_2
+; ZIBI-NEXT:  # %bb.1: # %test2
+; ZIBI-NEXT:    lw zero, 0(a0)
+; ZIBI-NEXT:  .LBB9_2: # %end
+; ZIBI-NEXT:    ret
+  %val1 = load volatile i32, ptr %b
+  %tst1 = icmp eq i32 %val1, 32
+  br i1 %tst1, label %end, label %test2, !prof !0
+test2:
+  %val2 = load volatile i32, ptr %b
+  br label %end
+end:
+  ret void
+}
+!0 = !{!"branch_weights", i32 1, i32 99}
+
+define i32 @test_select_beq_neg(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_beq_neg:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    beqi a0, -1, .LBB10_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB10_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_beq_neg:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    beqi a3, -1, .LBB10_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB10_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp eq i32 %a, -1
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}
+
+define i32 @test_select_bne_neg(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_bne_neg:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    bnei a0, -1, .LBB11_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB11_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_bne_neg:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    bnei a3, -1, .LBB11_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB11_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp ne i32 %a, -1
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}
+
+define i32 @test_select_beq_zero(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_beq_zero:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    beqz a0, .LBB12_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB12_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_beq_zero:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    beqz a3, .LBB12_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB12_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp eq i32 %a, 0
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}
+
+define i32 @test_select_bne_zero(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_bne_zero:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    bnez a0, .LBB13_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB13_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_bne_zero:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    bnez a3, .LBB13_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB13_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp ne i32 %a, 0
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}
+
+define i32 @test_select_beq_1(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_beq_1:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    beqi a0, 1, .LBB14_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB14_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_beq_1:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    beqi a3, 1, .LBB14_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB14_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp eq i32 %a, 1
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}
+
+define i32 @test_select_bne_1(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_bne_1:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    bnei a0, 1, .LBB15_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB15_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_bne_1:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    bnei a3, 1, .LBB15_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB15_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp ne i32 %a, 1
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}
+
+define i32 @test_select_beq_31(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_beq_31:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    beqi a0, 31, .LBB16_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB16_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_beq_31:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    beqi a3, 31, .LBB16_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB16_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp eq i32 %a, 31
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}
+
+define i32 @test_select_bne_31(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_bne_31:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    bnei a0, 31, .LBB17_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB17_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_bne_31:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    bnei a3, 31, .LBB17_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB17_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp ne i32 %a, 31
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}
+
+define i32 @test_select_beq_32(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_beq_32:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    li a3, 32
+; ZIBI-RV32-NEXT:    beq a0, a3, .LBB18_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB18_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_beq_32:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    li a4, 32
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    beq a3, a4, .LBB18_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB18_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp eq i32 %a, 32
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}
+
+define i32 @test_select_bne_32(i32 %a, i32 %b, i32 %c) nounwind {
+; ZIBI-RV32-LABEL: test_select_bne_32:
+; ZIBI-RV32:       # %bb.0:
+; ZIBI-RV32-NEXT:    li a3, 32
+; ZIBI-RV32-NEXT:    bne a0, a3, .LBB19_2
+; ZIBI-RV32-NEXT:  # %bb.1:
+; ZIBI-RV32-NEXT:    mv a1, a2
+; ZIBI-RV32-NEXT:  .LBB19_2:
+; ZIBI-RV32-NEXT:    mv a0, a1
+; ZIBI-RV32-NEXT:    ret
+;
+; ZIBI-RV64-LABEL: test_select_bne_32:
+; ZIBI-RV64:       # %bb.0:
+; ZIBI-RV64-NEXT:    sext.w a3, a0
+; ZIBI-RV64-NEXT:    li a4, 32
+; ZIBI-RV64-NEXT:    mv a0, a1
+; ZIBI-RV64-NEXT:    bne a3, a4, .LBB19_2
+; ZIBI-RV64-NEXT:  # %bb.1:
+; ZIBI-RV64-NEXT:    mv a0, a2
+; ZIBI-RV64-NEXT:  .LBB19_2:
+; ZIBI-RV64-NEXT:    ret
+  %tst = icmp ne i32 %a, 32
+  %ret = select i1 %tst, i32 %b, i32 %c
+  ret i32 %ret
+}