diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 86f95488e6bb7..d98c235dab15e 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -40,6 +40,8 @@ include "AArch64SchedPredExynos.td" include "AArch64SchedPredNeoverse.td" include "AArch64Combine.td" +defm : RemapAllTargetPseudoPointerOperands; + def AArch64InstrInfo : InstrInfo; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AMDGPU/R600.td b/llvm/lib/Target/AMDGPU/R600.td index 9148edb92b084..bdfaac9f42ea7 100644 --- a/llvm/lib/Target/AMDGPU/R600.td +++ b/llvm/lib/Target/AMDGPU/R600.td @@ -8,15 +8,6 @@ include "llvm/Target/Target.td" -def R600InstrInfo : InstrInfo { - let guessInstructionProperties = 1; -} - -def R600 : Target { - let InstructionSet = R600InstrInfo; - let AllowRegisterRenaming = 1; -} - let Namespace = "R600" in { foreach Index = 0-15 in { @@ -27,6 +18,18 @@ include "R600RegisterInfo.td" } +defm : RemapAllTargetPseudoPointerOperands; + +def R600InstrInfo : InstrInfo { + let guessInstructionProperties = 1; +} + +def R600 : Target { + let InstructionSet = R600InstrInfo; + let AllowRegisterRenaming = 1; +} + + def NullALU : InstrItinClass; def ALU_NULL : FuncUnit; diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 88a26832980d6..eecccd2e0e395 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -4745,3 +4745,14 @@ def V_ILLEGAL : Enc32, InstSI<(outs), (ins), "v_illegal"> { let hasSideEffects = 1; let SubtargetPredicate = isGFX10Plus; } + +defvar VGPR32_Ptr_Opcodes = [LOAD_STACK_GUARD]; +defvar VGPR64_Ptr_Opcodes = !listremove(PseudosWithPtrOps, VGPR32_Ptr_Opcodes); + +foreach inst = VGPR32_Ptr_Opcodes in { + def : RemapPointerOperands; +} + +foreach inst = VGPR64_Ptr_Opcodes in { + def : RemapPointerOperands; +} diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 570aae9b3c7a7..1f71d810983db 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -38,6 +38,14 @@ include "ARMSchedule.td" //===----------------------------------------------------------------------===// include "ARMInstrInfo.td" + +def Thumb1OnlyMode : HwMode<[IsThumb1Only]>; +def arm_ptr_rc : RegClassByHwMode< + [DefaultMode, Thumb1OnlyMode], + [GPR, tGPR]>; + +defm : RemapAllTargetPseudoPointerOperands; + def ARMInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AVR/AVR.td b/llvm/lib/Target/AVR/AVR.td index 22ffc4a368ad6..f4ee11984cb73 100644 --- a/llvm/lib/Target/AVR/AVR.td +++ b/llvm/lib/Target/AVR/AVR.td @@ -32,6 +32,8 @@ include "AVRRegisterInfo.td" include "AVRInstrInfo.td" +defm : RemapAllTargetPseudoPointerOperands; + def AVRInstrInfo : InstrInfo; //===---------------------------------------------------------------------===// diff --git a/llvm/lib/Target/BPF/BPF.td b/llvm/lib/Target/BPF/BPF.td index dff76ca07af51..399be731b44f6 100644 --- a/llvm/lib/Target/BPF/BPF.td +++ b/llvm/lib/Target/BPF/BPF.td @@ -13,6 +13,9 @@ include "BPFCallingConv.td" include "BPFInstrInfo.td" include "GISel/BPFRegisterBanks.td" + +defm : RemapAllTargetPseudoPointerOperands; + def BPFInstrInfo : InstrInfo; class Proc Features> diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td index b5df93a9d464c..45ef9441b0a41 100644 --- a/llvm/lib/Target/CSKY/CSKY.td +++ b/llvm/lib/Target/CSKY/CSKY.td @@ -671,6 +671,8 @@ def : CK860V<"ck860fv", NoSchedModel, // Define the CSKY target. //===----------------------------------------------------------------------===// +defm : RemapAllTargetPseudoPointerOperands; + def CSKYInstrInfo : InstrInfo; diff --git a/llvm/lib/Target/DirectX/DirectX.td b/llvm/lib/Target/DirectX/DirectX.td index 4d1d45b84a683..1717d533d90fa 100644 --- a/llvm/lib/Target/DirectX/DirectX.td +++ b/llvm/lib/Target/DirectX/DirectX.td @@ -22,6 +22,8 @@ include "DXILStubs.td" // DirectX Subtarget features. //===----------------------------------------------------------------------===// +defm : RemapAllTargetPseudoPointerOperands; + def DirectXInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td index 6d0529fb42779..332ce14504281 100644 --- a/llvm/lib/Target/Hexagon/Hexagon.td +++ b/llvm/lib/Target/Hexagon/Hexagon.td @@ -408,6 +408,8 @@ include "HexagonPatternsV65.td" include "HexagonDepMappings.td" include "HexagonIntrinsics.td" +defm : RemapAllTargetPseudoPointerOperands; + def HexagonInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Lanai/Lanai.td b/llvm/lib/Target/Lanai/Lanai.td index c6d949f42047e..9a5422db5feeb 100644 --- a/llvm/lib/Target/Lanai/Lanai.td +++ b/llvm/lib/Target/Lanai/Lanai.td @@ -21,6 +21,8 @@ include "LanaiRegisterInfo.td" include "LanaiCallingConv.td" include "LanaiInstrInfo.td" +defm : RemapAllTargetPseudoPointerOperands; + def LanaiInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td index 6497ff999f6fa..67f07f0a0370e 100644 --- a/llvm/lib/Target/LoongArch/LoongArch.td +++ b/llvm/lib/Target/LoongArch/LoongArch.td @@ -202,6 +202,8 @@ def : ProcessorModel<"la664", NoSchedModel, [Feature64Bit, // Define the LoongArch target. //===----------------------------------------------------------------------===// +defm : RemapAllTargetPseudoPointerOperands; + def LoongArchInstrInfo : InstrInfo { let guessInstructionProperties = 0; } diff --git a/llvm/lib/Target/M68k/M68k.td b/llvm/lib/Target/M68k/M68k.td index dab66d1022955..dfa44a423ae25 100644 --- a/llvm/lib/Target/M68k/M68k.td +++ b/llvm/lib/Target/M68k/M68k.td @@ -95,6 +95,8 @@ include "GISel/M68kRegisterBanks.td" include "M68kInstrInfo.td" +defm : RemapAllTargetPseudoPointerOperands; + def M68kInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/MSP430/MSP430.td b/llvm/lib/Target/MSP430/MSP430.td index 38aa30fcf4dd1..cb3949838f6f2 100644 --- a/llvm/lib/Target/MSP430/MSP430.td +++ b/llvm/lib/Target/MSP430/MSP430.td @@ -61,6 +61,8 @@ include "MSP430CallingConv.td" include "MSP430InstrInfo.td" +defm : RemapAllTargetPseudoPointerOperands; + def MSP430InstrInfo : InstrInfo; //===---------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td index e18388c179108..6c8d177093c76 100644 --- a/llvm/lib/Target/Mips/Mips.td +++ b/llvm/lib/Target/Mips/Mips.td @@ -244,6 +244,8 @@ include "MipsScheduleI6400.td" include "MipsScheduleP5600.td" include "MipsScheduleGeneric.td" +defm : RemapAllTargetPseudoPointerOperands; + def MipsInstrInfo : InstrInfo { } diff --git a/llvm/lib/Target/NVPTX/NVPTX.td b/llvm/lib/Target/NVPTX/NVPTX.td index 31c117a8c0fee..d41a43de95098 100644 --- a/llvm/lib/Target/NVPTX/NVPTX.td +++ b/llvm/lib/Target/NVPTX/NVPTX.td @@ -150,6 +150,16 @@ def : Proc<"sm_121", [SM121, PTX88]>; def : Proc<"sm_121a", [SM121a, PTX88]>; def : Proc<"sm_121f", [SM121f, PTX88]>; + +def Is64Bit : Predicate<"Subtarget->getTargetTriple().getArch() == Triple::nvptx64">; +def NVPTX64 : HwMode<[Is64Bit]>; + +def nvptx_ptr_rc : RegClassByHwMode< + [DefaultMode, NVPTX64], + [B32, B64]>; + +defm : RemapAllTargetPseudoPointerOperands; + def NVPTXInstrInfo : InstrInfo { } diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index d491e88b66ad8..1b60d297588e5 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -793,6 +793,8 @@ def PPCAsmParserVariant : AsmParserVariant { string BreakCharacters = "."; } +defm : RemapAllTargetPseudoPointerOperands; + def PPC : Target { // Information about the instructions. let InstructionSet = PPCInstrInfo; diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 6d8c1223adf78..4544de2ba3146 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -869,6 +869,10 @@ def PPCRegGxRCNoR0Operand : AsmOperandClass { let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; } +def ppc_ptr_rc : RegClassByHwMode< + [PPC32, PPC64], + [GPRC, G8RC]>; + def ptr_rc_nor0_by_hwmode : RegClassByHwMode< [PPC32, PPC64], [GPRC_NOR0, G8RC_NOX0]>; diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index b24d8637cb27f..f6f82fd9bb55f 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -96,6 +96,8 @@ def RISCVAsmWriter : AsmWriter { int PassSubtarget = 1; } +defm : RemapAllTargetPseudoPointerOperands; + def RISCV : Target { let InstructionSet = RISCVInstrInfo; let AssemblyParsers = [RISCVAsmParser]; diff --git a/llvm/lib/Target/SPIRV/SPIRV.td b/llvm/lib/Target/SPIRV/SPIRV.td index 39a4131c7f1bd..cc9c7913af427 100644 --- a/llvm/lib/Target/SPIRV/SPIRV.td +++ b/llvm/lib/Target/SPIRV/SPIRV.td @@ -14,6 +14,8 @@ include "SPIRVInstrInfo.td" include "SPIRVCombine.td" include "SPIRVBuiltins.td" +defm : RemapAllTargetPseudoPointerOperands; + def SPIRVInstrInfo : InstrInfo; class Proc Features> diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td index 7137e5fbff4ff..70160f5b91dee 100644 --- a/llvm/lib/Target/Sparc/Sparc.td +++ b/llvm/lib/Target/Sparc/Sparc.td @@ -123,6 +123,8 @@ include "SparcCallingConv.td" include "SparcSchedule.td" include "SparcInstrInfo.td" +defm : RemapAllTargetPseudoPointerOperands; + def SparcInstrInfo : InstrInfo; def SparcAsmParser : AsmParser { diff --git a/llvm/lib/Target/SystemZ/SystemZ.td b/llvm/lib/Target/SystemZ/SystemZ.td index ec110645c62dd..070a4fbde1f06 100644 --- a/llvm/lib/Target/SystemZ/SystemZ.td +++ b/llvm/lib/Target/SystemZ/SystemZ.td @@ -57,6 +57,9 @@ include "SystemZInstrHFP.td" include "SystemZInstrDFP.td" include "SystemZInstrSystem.td" + +defm : RemapAllTargetPseudoPointerOperands; + def SystemZInstrInfo : InstrInfo { let guessInstructionProperties = 0; } //===----------------------------------------------------------------------===// @@ -98,7 +101,6 @@ def HLASMAsmWriter : AsmWriter { //===----------------------------------------------------------------------===// // Top-level target declaration //===----------------------------------------------------------------------===// - def SystemZ : Target { let InstructionSet = SystemZInstrInfo; let AssemblyParsers = [SystemZAsmParser]; diff --git a/llvm/lib/Target/VE/VE.td b/llvm/lib/Target/VE/VE.td index bb076bd9f6d41..aedce0f4ebc8f 100644 --- a/llvm/lib/Target/VE/VE.td +++ b/llvm/lib/Target/VE/VE.td @@ -30,6 +30,7 @@ include "VERegisterInfo.td" include "VECallingConv.td" include "VEInstrInfo.td" +defm : RemapAllTargetPseudoPointerOperands; def VEInstrInfo : InstrInfo {} def VEAsmParser : AsmParser { diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td index 089be5f1dc70e..67015ffcfc760 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.td +++ b/llvm/lib/Target/WebAssembly/WebAssembly.td @@ -108,6 +108,14 @@ include "WebAssemblyRegisterInfo.td" include "WebAssemblyInstrInfo.td" +def WASM64 : HwMode<[HasAddr64]>; + +def wasm_ptr_rc : RegClassByHwMode< + [DefaultMode, WASM64], + [I32, I64]>; + +defm : RemapAllTargetPseudoPointerOperands; + def WebAssemblyInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index 3af8b3e060a16..9fd8db2adc51e 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -798,6 +798,8 @@ include "X86Schedule.td" include "X86InstrInfo.td" include "X86SchedPredicates.td" +defm : RemapAllTargetPseudoPointerOperands; + def X86InstrInfo : InstrInfo; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/XCore/XCore.td b/llvm/lib/Target/XCore/XCore.td index a97b3dd1d0a2b..fa8b9fe26bbe1 100644 --- a/llvm/lib/Target/XCore/XCore.td +++ b/llvm/lib/Target/XCore/XCore.td @@ -24,6 +24,8 @@ include "XCoreRegisterInfo.td" include "XCoreInstrInfo.td" include "XCoreCallingConv.td" +defm : RemapAllTargetPseudoPointerOperands; + def XCoreInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index 4ef885e19101e..eecf42f46f88b 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -44,6 +44,8 @@ include "XtensaCallingConv.td" include "XtensaInstrInfo.td" +defm : RemapAllTargetPseudoPointerOperands; + def XtensaInstrInfo : InstrInfo; //===----------------------------------------------------------------------===//