From dcd039addb7659758bd0faeb5b63b73dbd8dbdfe Mon Sep 17 00:00:00 2001
From: Evgenii Kudriashov <evgenii.kudriashov@intel.com>
Date: Wed, 4 Oct 2023 06:34:52 -0700
Subject: [PATCH] [X86] Add combine tests for pointers of mixed sizes (NFC)

---
 llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll | 36 +++++++++++++++++++
 llvm/test/CodeGen/X86/mixed-ptr-sizes.ll      | 32 +++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
index 0817211f50937..c997d314a50ae 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll
@@ -341,3 +341,39 @@ entry:
   store i32 %i, ptr addrspace(272) %s, align 8
   ret void
 }
+
+define i64 @test_load_sptr32_zext_i64(ptr addrspace(270) %i) {
+; ALL-LABEL: test_load_sptr32_zext_i64:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; ALL-NEXT:    movl (%eax), %eax
+; ALL-NEXT:    xorl %edx, %edx
+; ALL-NEXT:    retl
+entry:
+  %0 = load i32, ptr addrspace(270) %i, align 4
+  %1 = zext i32 %0 to i64
+  ret i64 %1
+}
+
+define void @test_store_sptr32_trunc_i1(ptr addrspace(270) %s, i32 %i) {
+; CHECK-LABEL: test_store_sptr32_trunc_i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    andl $1, %ecx
+; CHECK-NEXT:    movb %cl, (%eax)
+; CHECK-NEXT:    retl
+;
+; CHECK-O0-LABEL: test_store_sptr32_trunc_i1:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-O0-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-O0-NEXT:    andl $1, %ecx
+; CHECK-O0-NEXT:    # kill: def $cl killed $cl killed $ecx
+; CHECK-O0-NEXT:    movb %cl, (%eax)
+; CHECK-O0-NEXT:    retl
+entry:
+  %0 = trunc i32 %i to i1
+  store i1 %0, ptr addrspace(270) %s
+  ret void
+}
diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
index e88a494908701..2dd6011f36b77 100644
--- a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
+++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll
@@ -256,3 +256,35 @@ entry:
   store i32 %i, ptr addrspace(272) %s, align 8
   ret void
 }
+
+define i64 @test_load_sptr32_zext_i64(ptr addrspace(270) %i) {
+; CHECK-LABEL: test_load_sptr32_zext_i64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    movq (%rax), %rax
+; CHECK-NEXT:    retq
+;
+; CHECK-O0-LABEL: test_load_sptr32_zext_i64:
+; CHECK-O0:       # %bb.0: # %entry
+; CHECK-O0-NEXT:    movslq %ecx, %rax
+; CHECK-O0-NEXT:    movl (%rax), %eax
+; CHECK-O0-NEXT:    movl %eax, %eax
+; CHECK-O0-NEXT:    # kill: def $rax killed $eax
+; CHECK-O0-NEXT:    retq
+entry:
+  %0 = load i32, ptr addrspace(270) %i, align 4
+  %1 = zext i32 %0 to i64
+  ret i64 %1
+}
+
+define void @test_store_sptr32_trunc_i1(ptr addrspace(270) %s, i32 %i) {
+; ALL-LABEL: test_store_sptr32_trunc_i1:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    movslq %ecx, %rax
+; ALL-NEXT:    movl %edx, (%rax)
+; ALL-NEXT:    retq
+entry:
+  %0 = trunc i32 %i to i1
+  store i1 %0, ptr addrspace(270) %s
+  ret void
+}