From 7ef1d3e57d8935b6c32d52fc659cc9eae969e581 Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra Date: Wed, 1 Nov 2023 11:53:18 +0000 Subject: [PATCH] ISel/RISCV: restrict custom lowering of ISD::LRINT, ISD::LLRINT To follow up on 7a76038 (CodeGen/RISCV: increase test coverage of lrint, llrint), it is clear that the custom lowering of ISD::LRINT always works for i32, and only works for i64 if the subtarget is 64-bit. ISD::LLRINT custom-lowering works for i32 and i64. Hence, guard the appropriate setOperationAction() calls with these checks. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index e9f80432ab190..479937f83cffa 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -731,7 +731,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, VT, Custom); setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT, Custom); - setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom); + if (VT.getVectorElementType() == MVT::i32 || + (VT.getVectorElementType() == MVT::i64 && Subtarget.is64Bit())) + setOperationAction({ISD::LRINT}, VT, Custom); + if (VT.getVectorElementType() == MVT::i64 || + VT.getVectorElementType() == MVT::i32) + setOperationAction({ISD::LLRINT}, VT, Custom); setOperationAction( {ISD::SADDSAT, ISD::UADDSAT, ISD::SSUBSAT, ISD::USUBSAT}, VT, Legal);