From 62dd95bf22e3662ab0abae5d2178e796a8cc583c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= Date: Thu, 18 Jul 2024 17:49:48 +0200 Subject: [PATCH 1/3] [GlobalIsel] import G_SCMP and G_UCMP See https://github.com/llvm/llvm-project/pull/98894 --- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 12 +++++ .../AArch64/GlobalISel/irtranslator-sucmp.ll | 54 +++++++++++++++++++ 2 files changed, 66 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 72dff12423ced..a6b454d41a76f 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -2561,6 +2561,18 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, MIRBuilder.buildVScale(getOrCreateVReg(CI), 1); return true; } + case Intrinsic::scmp: { + MIRBuilder.buildSCmp(getOrCreateVReg(CI), + getOrCreateVReg(*CI.getOperand(0)), + getOrCreateVReg(*CI.getOperand(1))); + return true; + } + case Intrinsic::ucmp: { + MIRBuilder.buildUCmp(getOrCreateVReg(CI), + getOrCreateVReg(*CI.getOperand(0)), + getOrCreateVReg(*CI.getOperand(1))); + return true; + } case Intrinsic::prefetch: { Value *Addr = CI.getOperand(0); unsigned RW = cast(CI.getOperand(1))->getZExtValue(); diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll new file mode 100644 index 0000000000000..8ceac0dc21f2d --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll @@ -0,0 +1,54 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s + +define void @scmp_i32(i32 %arg1, i32 %arg2) { + ; CHECK-LABEL: name: scmp_i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 + ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(s4) = G_SCMP [[COPY1]](s32), [[COPY1]] + ; CHECK-NEXT: RET_ReallyLR + %res4 = call i4 @llvm.scmp.i4.i32(i32 %arg2, i32 %arg2) + ret void +} + +define void @scmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) { + ; CHECK-LABEL: name: scmp_4_32i + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $q0, $q1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 + ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(<4 x s32>) = G_SCMP [[COPY1]](<4 x s32>), [[COPY1]] + ; CHECK-NEXT: RET_ReallyLR + %res4 = call <4 x i32> @llvm.scmp.v4i32.i32(<4 x i32> %arg2, <4 x i32> %arg2) + ret void +} + +define void @ucmp_i32(i32 %arg1, i32 %arg2) { + ; CHECK-LABEL: name: ucmp_i32 + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $w0, $w1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 + ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(s4) = G_UCMP [[COPY1]](s32), [[COPY1]] + ; CHECK-NEXT: RET_ReallyLR + %res4 = call i4 @llvm.ucmp.i4.i32(i32 %arg2, i32 %arg2) + ret void +} + +define void @ucmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) { + ; CHECK-LABEL: name: ucmp_4_32i + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $q0, $q1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 + ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(<4 x s32>) = G_UCMP [[COPY1]](<4 x s32>), [[COPY1]] + ; CHECK-NEXT: RET_ReallyLR + %res4 = call <4 x i32> @llvm.ucmp.v4i32.i32(<4 x i32> %arg2, <4 x i32> %arg2) + ret void +} From ff0d6c53691554df55f4a3e3be353c984a6bd071 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= Date: Thu, 18 Jul 2024 20:07:47 +0200 Subject: [PATCH 2/3] remove braces --- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index a6b454d41a76f..40a691af22748 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -2561,18 +2561,16 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, MIRBuilder.buildVScale(getOrCreateVReg(CI), 1); return true; } - case Intrinsic::scmp: { + case Intrinsic::scmp: MIRBuilder.buildSCmp(getOrCreateVReg(CI), getOrCreateVReg(*CI.getOperand(0)), getOrCreateVReg(*CI.getOperand(1))); return true; - } - case Intrinsic::ucmp: { + case Intrinsic::ucmp: MIRBuilder.buildUCmp(getOrCreateVReg(CI), getOrCreateVReg(*CI.getOperand(0)), getOrCreateVReg(*CI.getOperand(1))); return true; - } case Intrinsic::prefetch: { Value *Addr = CI.getOperand(0); unsigned RW = cast(CI.getOperand(1))->getZExtValue(); From 717ab6ef57d30a8dc088220b436a4d00f78c02e3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= Date: Fri, 19 Jul 2024 05:31:05 +0200 Subject: [PATCH 3/3] fix test --- .../AArch64/GlobalISel/irtranslator-sucmp.ll | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll index 8ceac0dc21f2d..1fa21bfb733e8 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll @@ -8,9 +8,9 @@ define void @scmp_i32(i32 %arg1, i32 %arg2) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 - ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(s4) = G_SCMP [[COPY1]](s32), [[COPY1]] + ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(s4) = G_SCMP [[COPY]](s32), [[COPY1]] ; CHECK-NEXT: RET_ReallyLR - %res4 = call i4 @llvm.scmp.i4.i32(i32 %arg2, i32 %arg2) + %res4 = call i4 @llvm.scmp.i4.i32(i32 %arg1, i32 %arg2) ret void } @@ -21,9 +21,9 @@ define void @scmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 - ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(<4 x s32>) = G_SCMP [[COPY1]](<4 x s32>), [[COPY1]] + ; CHECK-NEXT: [[SCMP:%[0-9]+]]:_(<4 x s32>) = G_SCMP [[COPY]](<4 x s32>), [[COPY1]] ; CHECK-NEXT: RET_ReallyLR - %res4 = call <4 x i32> @llvm.scmp.v4i32.i32(<4 x i32> %arg2, <4 x i32> %arg2) + %res4 = call <4 x i32> @llvm.scmp.v4i32.i32(<4 x i32> %arg1, <4 x i32> %arg2) ret void } @@ -34,9 +34,9 @@ define void @ucmp_i32(i32 %arg1, i32 %arg2) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 - ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(s4) = G_UCMP [[COPY1]](s32), [[COPY1]] + ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(s4) = G_UCMP [[COPY]](s32), [[COPY1]] ; CHECK-NEXT: RET_ReallyLR - %res4 = call i4 @llvm.ucmp.i4.i32(i32 %arg2, i32 %arg2) + %res4 = call i4 @llvm.ucmp.i4.i32(i32 %arg1, i32 %arg2) ret void } @@ -47,8 +47,8 @@ define void @ucmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) { ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 - ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(<4 x s32>) = G_UCMP [[COPY1]](<4 x s32>), [[COPY1]] + ; CHECK-NEXT: [[UCMP:%[0-9]+]]:_(<4 x s32>) = G_UCMP [[COPY]](<4 x s32>), [[COPY1]] ; CHECK-NEXT: RET_ReallyLR - %res4 = call <4 x i32> @llvm.ucmp.v4i32.i32(<4 x i32> %arg2, <4 x i32> %arg2) + %res4 = call <4 x i32> @llvm.ucmp.v4i32.i32(<4 x i32> %arg1, <4 x i32> %arg2) ret void }