Reapply peripherals/rcc/rcc_h7.yaml to stm32h7b3.yaml with new SVDs

There's many case of renames like D3 -> SRD and D1/D2 -> CD, handle these with
new match options

Requires rust-embedded/svdtools#57 for _clear statements

Author: richardeoin

devices/common_patches/h7_common_highmemory.yaml

@@ -473,6 +473,8 @@ RCC:
         name: D3PPRE
 
   CR:
+    _clear:
+      "*"
     _modify:
       RC48ON:
         name: HSI48ON
@@ -483,12 +485,16 @@ RCC:
       RC48CAL:
         name: HSI48CAL
   CFGR:
+    _clear:
+      "*"
     _modify:
       MCO1SEL:
         name: MCO1
       MCO2SEL:
         name: MCO2
   CIER:
+    _clear:
+      "*"
     _modify:
       RC48RDYIE:
         name: HSI48RDYIE
@@ -497,16 +503,25 @@ RCC:
       RC48RDYF:
         name: HSI48RDYF
   CICR:
+    _clear:
+      "*"
     _modify:
       RC48RDYC:
         name: HSI48RDYC
   BDCR:
+    _clear:
+      "*"
     _modify:
       VSWRST:
         name: BDRST
       RTCSRC:
         name: RTCSEL
+  CSR:
+    _clear:
+      "*"
   PLL2DIVR:
+    _clear:
+      "*"
     _modify:
       DIVR1:
         name: DIVR2
@@ -516,6 +531,15 @@ RCC:
         name: DIVP2
       DIVN1:
         name: DIVN2
+  "A?B?RSTR,A?B??RSTR":
+    _clear:
+      "*RST"
+  "A?B?ENR,A?B??ENR,C1_A?B?ENR,C1_A?B??ENR":
+    _clear:
+      "*EN"
+  "A?B?LPENR,A?B??LPENR,C1_A?B?LPENR,C1_A?B??LPENR":
+    _clear:
+      "*LPEN"
   APB1LRSTR:
     _modify:
       USART7RST:
@@ -587,6 +611,16 @@ RCC:
       FLITFLPEN:
         name: FLASHPREN
         description: "Flash interface clock enable during csleep mode"
+  RSR:
+    _clear:
+      "*RSTF"
+  PLLCKSELR,PLLCFGR,PLL1DIVR,CDCFGR?,CDCCIPR,CDCCIP?R:
+    _clear:
+      "*"
+  SRDAMR,SRDCCIPR:
+    _clear:
+      "*"
+
 
 TIM1,TIM8:
   DMAR:

devices/stm32h735.yaml

@@ -88,6 +88,7 @@ _include:
  - ../peripherals/gpio/gpio_v2.yaml
  - ../peripherals/lptim/lptim_v1.yaml
  - ../peripherals/ltdc/ltdc.yaml
+ - ../peripherals/rcc/rcc_v3_hrtim.yaml
  - ../peripherals/rcc/rcc_h7_revision_v.yaml
  - ../peripherals/rng/rng_v1.yaml
  - ../peripherals/rng/rng_v1_ced.yaml

devices/stm32h743.yaml

@@ -49,6 +49,7 @@ _include:
  - ../peripherals/lptim/lptim_v1.yaml
  - ../peripherals/ltdc/ltdc.yaml
  - ../peripherals/rcc/rcc_h7.yaml
+ - ../peripherals/rcc/rcc_v3_hrtim.yaml
  - ../peripherals/rcc/rcc_h7_revision_y.yaml
  - ../peripherals/rng/rng_v1.yaml
  - ../peripherals/rng/rng_v1_ced.yaml

devices/stm32h743v.yaml

@@ -51,6 +51,7 @@ _include:
  - ../peripherals/lptim/lptim_v1.yaml
  - ../peripherals/ltdc/ltdc.yaml
  - ../peripherals/rcc/rcc_h7.yaml
+ - ../peripherals/rcc/rcc_v3_hrtim.yaml
  - ../peripherals/rcc/rcc_h7_revision_v.yaml
  - ../peripherals/rng/rng_v1.yaml
  - ../peripherals/rng/rng_v1_ced.yaml

devices/stm32h747cm4.yaml

@@ -64,6 +64,7 @@ _include:
  - ../peripherals/lptim/lptim_v1.yaml
  - ../peripherals/ltdc/ltdc.yaml
  - ../peripherals/rcc/rcc_h7.yaml
+ - ../peripherals/rcc/rcc_v3_hrtim.yaml
  - ../peripherals/rcc/rcc_h7_revision_v.yaml
  - ../peripherals/rng/rng_v1.yaml
  - ../peripherals/rng/rng_v1_ced.yaml

devices/stm32h747cm7.yaml

@@ -65,6 +65,7 @@ _include:
  - ../peripherals/lptim/lptim_v1.yaml
  - ../peripherals/ltdc/ltdc.yaml
  - ../peripherals/rcc/rcc_h7.yaml
+ - ../peripherals/rcc/rcc_v3_hrtim.yaml
  - ../peripherals/rcc/rcc_h7_revision_v.yaml
  - ../peripherals/rng/rng_v1.yaml
  - ../peripherals/rng/rng_v1_ced.yaml

devices/stm32h753.yaml

@@ -59,6 +59,7 @@ _include:
  - ../peripherals/lptim/lptim_v1.yaml
  - ../peripherals/ltdc/ltdc.yaml
  - ../peripherals/rcc/rcc_h7.yaml
+ - ../peripherals/rcc/rcc_v3_hrtim.yaml
  - ../peripherals/rcc/rcc_h7_revision_y.yaml
  - ../peripherals/rng/rng_v1.yaml
  - ../peripherals/rng/rng_v1_ced.yaml

devices/stm32h753v.yaml

@@ -61,6 +61,7 @@ _include:
  - ../peripherals/lptim/lptim_v1.yaml
  - ../peripherals/ltdc/ltdc.yaml
  - ../peripherals/rcc/rcc_h7.yaml
+ - ../peripherals/rcc/rcc_v3_hrtim.yaml
  - ../peripherals/rcc/rcc_h7_revision_v.yaml
  - ../peripherals/rng/rng_v1.yaml
  - ../peripherals/rng/rng_v1_ced.yaml

devices/stm32h7b3.yaml

@@ -116,6 +116,7 @@ _include:
  - ../peripherals/gpio/gpio_v2.yaml
  - ../peripherals/lptim/lptim_v1.yaml
  - ../peripherals/ltdc/ltdc.yaml
+ - ../peripherals/rcc/rcc_h7.yaml
  - ../peripherals/rcc/rcc_h7_revision_v.yaml
  - ../peripherals/rng/rng_v1.yaml
  - ../peripherals/rng/rng_v1_ced.yaml

peripherals/rcc/rcc_v3.yaml

@@ -44,9 +44,6 @@ RCC:
     TIMPRE:
       DefaultX2: [0, "Timer kernel clock equal to 2x pclk by default"]
       DefaultX4: [1, "Timer kernel clock equal to 4x pclk by default"]
-    HRTIMSEL:
-      TIMY_KER: [0, "The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck)"]
-      C_CK: [1, "The HRTIM prescaler clock source is the CPU clock (c_ck)"]
     RTCPRE: [0, 63]
     STOPWUCK,STOPKERWUCK:
       HSI: [0, "HSI selected as wake up clock from system Stop"]
@@ -117,7 +114,7 @@ RCC:
     WW1RSC:
       Clear: [0, "Clear WWDG1 scope control"]
       Set: [1, "Set WWDG1 scope control"]
-  D3AMR:
+  D3AMR,SRDAMR:
     "*AMEN":
       Disabled: [0, "Clock disabled in autonomous mode"]
       Enabled: [1, "Clock enabled in autonomous mode"]

peripherals/rcc/rcc_v3_h7_ccip.yaml

@@ -4,8 +4,8 @@
 # clock configuration registers (DxCFGR)
 
 RCC:
-  D1CFGR:
-    "D?CPRE,HPRE":
+  D1CFGR,CDCFGR1:
+    "D?CPRE,HPRE,CDCPRE":
       Div1: [0, "sys_ck not divided"]
       Div2: [8, "sys_ck divided by 2"]
       Div4: [9, "sys_ck divided by 4"]
@@ -15,8 +15,8 @@ RCC:
       Div128: [13, "sys_ck divided by 128"]
       Div256: [14, "sys_ck divided by 256"]
       Div512: [15, "sys_ck divided by 512"]
-  D?CFGR:
-    D?PPR*:
+  D?CFGR,CDCFGR?:
+    D?PPR*,CDPPRE*:
       Div1: [0, "rcc_hclk not divided"]
       Div2: [4, "rcc_hclk divided by 2"]
       Div4: [5, "rcc_hclk divided by 4"]
@@ -36,7 +36,7 @@ RCC:
       PLL2_R: [2, "pll2_r selected as peripheral clock"]
       PER: [3, "PER selected as peripheral clock"]
   D2CCIP1R,CDCCIP1R:
-    SWPSEL:
+    SWPSEL,SWPMISEL:
       PCLK: [0, "pclk selected as peripheral clock"]
       HSI_KER: [1, "hsi_ker selected as peripheral clock"]
     FDCANSEL:

peripherals/rcc/rcc_v3_hrtim.yaml

@@ -0,0 +1,7 @@
+# Applicable at least to H7, except RM0455 parts with no HRTIM
+
+RCC:
+  CFGR:
+    HRTIMSEL:
+      TIMY_KER: [0, "The HRTIM prescaler clock source is the same as other timers (rcc_timy_ker_ck)"]
+      C_CK: [1, "The HRTIM prescaler clock source is the CPU clock (c_ck)"]