fix atomic operation and spinlock bug

Signed-off-by: liuyuncheng <[email protected]>

Author: yuncliu

opal/include/opal/sys/arm64/atomic.h

@@ -70,10 +70,10 @@ static inline bool opal_atomic_compare_exchange_strong_32(opal_atomic_int32_t *a
     int32_t prev, tmp;
     bool ret;
 
-    __asm__ __volatile__("1:  ldaxr    %w0, [%2]      \n"
+    __asm__ __volatile__("1:  ldaxr   %w0, [%2]      \n"
                          "    cmp     %w0, %w3        \n"
                          "    bne     2f              \n"
-                         "    stxr    %w1, %w4, [%2]  \n"
+                         "    stlxr   %w1, %w4, [%2]  \n"
                          "    cbnz    %w1, 1b         \n"
                          "2:                          \n"
                          : "=&r"(prev), "=&r"(tmp)
@@ -99,7 +99,7 @@ static inline bool opal_atomic_compare_exchange_strong_acq_32(opal_atomic_int32_
     __asm__ __volatile__("1:  ldaxr   %w0, [%2]       \n"
                          "    cmp     %w0, %w3        \n"
                          "    bne     2f              \n"
-                         "    stxr    %w1, %w4, [%2]  \n"
+                         "    stlxr   %w1, %w4, [%2]  \n"
                          "    cbnz    %w1, 1b         \n"
                          "2:                          \n"
                          : "=&r"(prev), "=&r"(tmp)
@@ -117,7 +117,7 @@ static inline bool opal_atomic_compare_exchange_strong_rel_32(opal_atomic_int32_
     int32_t prev, tmp;
     bool ret;
 
-    __asm__ __volatile__("1:  ldxr    %w0, [%2]       \n"
+    __asm__ __volatile__("1:  ldaxr   %w0, [%2]       \n"
                          "    cmp     %w0, %w3        \n"
                          "    bne     2f              \n"
                          "    stlxr   %w1, %w4, [%2]  \n"
@@ -139,10 +139,10 @@ static inline bool opal_atomic_compare_exchange_strong_64(opal_atomic_int64_t *a
     int tmp;
     bool ret;
 
-    __asm__ __volatile__("1:  ldaxr    %0, [%2]       \n"
+    __asm__ __volatile__("1:  ldaxr   %0, [%2]       \n"
                          "    cmp     %0, %3          \n"
                          "    bne     2f              \n"
-                         "    stxr    %w1, %4, [%2]   \n"
+                         "    stlxr   %w1, %4, [%2]   \n"
                          "    cbnz    %w1, 1b         \n"
                          "2:                          \n"
                          : "=&r"(prev), "=&r"(tmp)
@@ -169,7 +169,7 @@ static inline bool opal_atomic_compare_exchange_strong_acq_64(opal_atomic_int64_
     __asm__ __volatile__("1:  ldaxr   %0, [%2]        \n"
                          "    cmp     %0, %3          \n"
                          "    bne     2f              \n"
-                         "    stxr    %w1, %4, [%2]   \n"
+                         "    stlxr   %w1, %4, [%2]   \n"
                          "    cbnz    %w1, 1b         \n"
                          "2:                          \n"
                          : "=&r"(prev), "=&r"(tmp)
@@ -188,7 +188,7 @@ static inline bool opal_atomic_compare_exchange_strong_rel_64(opal_atomic_int64_
     int tmp;
     bool ret;
 
-    __asm__ __volatile__("1:  ldxr    %0, [%2]        \n"
+    __asm__ __volatile__("1:  ldaxr   %0, [%2]        \n"
                          "    cmp     %0, %3          \n"
                          "    bne     2f              \n"
                          "    stlxr   %w1, %4, [%2]   \n"
@@ -266,9 +266,9 @@ static inline int64_t opal_atomic_swap_64(opal_atomic_int64_t *addr, int64_t new
         type newval, old;                                                          \
         int32_t tmp;                                                               \
                                                                                    \
-        __asm__ __volatile__("1:  ldxr   %" reg "1, [%3]        \n"                \
+        __asm__ __volatile__("1:  ldaxr  %" reg "1, [%3]        \n"                \
                              "    " inst "   %" reg "0, %" reg "1, %" reg "4 \n"   \
-                             "    stxr   %w2, %" reg "0, [%3]   \n"                \
+                             "    stlxr  %w2, %" reg "0, [%3]   \n"                \
                              "    cbnz   %w2, 1b         \n"                       \
                              : "=&r"(newval), "=&r"(old), "=&r"(tmp)               \
                              : "r"(addr), "r"(value)                               \
@@ -282,9 +282,9 @@ static inline int64_t opal_atomic_swap_64(opal_atomic_int64_t *addr, int64_t new
         type newval, old;                                                          \
         int32_t tmp;                                                               \
                                                                                    \
-        __asm__ __volatile__("1:  ldxr   %" reg "1, [%3]        \n"                \
+        __asm__ __volatile__("1:  ldaxr  %" reg "1, [%3]        \n"                \
                              "    " inst "   %" reg "0, %" reg "1, %" reg "4 \n"   \
-                             "    stxr   %w2, %" reg "0, [%3]   \n"                \
+                             "    stlxr  %w2, %" reg "0, [%3]   \n"                \
                              "    cbnz   %w2, 1b         \n"                       \
                              : "=&r"(newval), "=&r"(old), "=&r"(tmp)               \
                              : "r"(addr), "r"(value)                               \