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[GR-41061] Port BigInteger.multiplyToLen stub.
PullRequest: graal/12724
2 parents 2c3637b + 715a944 commit 0728038

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‎compiler/src/org.graalvm.compiler.asm.aarch64.test/src/org/graalvm/compiler/asm/aarch64/test/TestProtectedAssembler.java‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -135,11 +135,6 @@ protected void movk(int size, Register dst, int uimm16, int pos) {
135135
super.movk(size, dst, uimm16, pos);
136136
}
137137

138-
@Override
139-
protected void extr(int size, Register dst, Register src1, Register src2, int lsb) {
140-
super.extr(size, dst, src1, src2, lsb);
141-
}
142-
143138
@Override
144139
protected void add(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int imm) {
145140
super.add(size, dst, src1, src2, shiftType, imm);

‎compiler/src/org.graalvm.compiler.asm.aarch64/src/org/graalvm/compiler/asm/aarch64/AArch64Assembler.java‎

Lines changed: 79 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,8 @@
6363
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Asserts.verifySizesAndRegistersFF;
6464
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Asserts.verifySizesAndRegistersFZ;
6565
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Asserts.verifySizesAndRegistersRF;
66+
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADC;
67+
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADCS;
6668
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADD;
6769
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADDS;
6870
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.ADR;
@@ -138,6 +140,8 @@
138140
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.REVW;
139141
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.REVX;
140142
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.RORV;
143+
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SBC;
144+
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SBCS;
141145
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SBFM;
142146
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SCVTF;
143147
import static org.graalvm.compiler.asm.aarch64.AArch64Assembler.Instruction.SDIV;
@@ -925,6 +929,11 @@ public enum Instruction {
925929
SUB(0x40000000),
926930
SUBS(SUB.encoding | AddSubSetFlag),
927931

932+
ADC(0b00 << 29),
933+
ADCS(0b01 << 29),
934+
SBC(0b10 << 29),
935+
SBCS(0b11 << 29),
936+
928937
CCMP(0x7A400000),
929938

930939
NOT(0x00200000),
@@ -2351,7 +2360,7 @@ private void bitfieldInstruction(Instruction instr, Register dst, Register src,
23512360
* @param src2 general purpose register. May not be null or stackpointer.
23522361
* @param lsb must be in range 0 to size - 1.
23532362
*/
2354-
protected void extr(int size, Register dst, Register src1, Register src2, int lsb) {
2363+
public void extr(int size, Register dst, Register src1, Register src2, int lsb) {
23552364
assert verifySizeAndRegistersRZZ(size, dst, src1, src2);
23562365

23572366
InstructionType type = generalFromSize(size);
@@ -2736,6 +2745,75 @@ protected void rorv(int size, Register dst, Register src1, Register src2) {
27362745
dataProcessing2SourceOp(RORV, dst, src1, src2, generalFromSize(size));
27372746
}
27382747

2748+
/**
2749+
* C6.2.1 Add with carry.
2750+
*
2751+
* dst = src1 + src2 + PSTATE.C.
2752+
*
2753+
* @param size register size. Has to be 32 or 64.
2754+
* @param dst general purpose register. May not be null or stackpointer.
2755+
* @param src1 general purpose register. May not be null or stackpointer.
2756+
* @param src2 general purpose register. May not be null or stackpointer.
2757+
*/
2758+
public void adc(int size, Register dst, Register src1, Register src2) {
2759+
assert verifySizeAndRegistersZZZ(size, dst, src1, src2);
2760+
2761+
addSubWithCarryOp(ADC, dst, src1, src2, generalFromSize(size));
2762+
}
2763+
2764+
/**
2765+
* C6.2.2 Add with carry & set flags.
2766+
*
2767+
* dst = src1 + src2 + PSTATE.C, and sets condition flags.
2768+
*
2769+
* @param size register size. Has to be 32 or 64.
2770+
* @param dst general purpose register. May not be null or stackpointer.
2771+
* @param src1 general purpose register. May not be null or stackpointer.
2772+
* @param src2 general purpose register. May not be null or stackpointer.
2773+
*/
2774+
public void adcs(int size, Register dst, Register src1, Register src2) {
2775+
assert verifySizeAndRegistersZZZ(size, dst, src1, src2);
2776+
2777+
addSubWithCarryOp(ADCS, dst, src1, src2, generalFromSize(size));
2778+
}
2779+
2780+
/**
2781+
* C6.2.231 Subtract with carry.
2782+
*
2783+
* dst = src1 - src2 + NOT(PSTATE.C).
2784+
*
2785+
* @param size register size. Has to be 32 or 64.
2786+
* @param dst general purpose register. May not be null or stackpointer.
2787+
* @param src1 general purpose register. May not be null or stackpointer.
2788+
* @param src2 general purpose register. May not be null or stackpointer.
2789+
*/
2790+
public void sbc(int size, Register dst, Register src1, Register src2) {
2791+
assert verifySizeAndRegistersZZZ(size, dst, src1, src2);
2792+
2793+
addSubWithCarryOp(SBC, dst, src1, src2, generalFromSize(size));
2794+
}
2795+
2796+
/**
2797+
* C6.2.232 Subtract with carry & set flags.
2798+
*
2799+
* dst = src1 - src2 + NOT(PSTATE.C), and sets condition flags.
2800+
*
2801+
* @param size register size. Has to be 32 or 64.
2802+
* @param dst general purpose register. May not be null or stackpointer.
2803+
* @param src1 general purpose register. May not be null or stackpointer.
2804+
* @param src2 general purpose register. May not be null or stackpointer.
2805+
*/
2806+
public void sbcs(int size, Register dst, Register src1, Register src2) {
2807+
assert verifySizeAndRegistersZZZ(size, dst, src1, src2);
2808+
2809+
addSubWithCarryOp(SBCS, dst, src1, src2, generalFromSize(size));
2810+
}
2811+
2812+
private void addSubWithCarryOp(Instruction instr, Register dst, Register src1, Register src2, InstructionType type) {
2813+
int baseEncoding = 0b0_0_0_11010000_00000_000000_00000_00000;
2814+
emitInt(instr.encoding | type.encoding | baseEncoding | rd(dst) | rs1(src1) | rs2(src2));
2815+
}
2816+
27392817
/* Bit Operations (5.5.5) */
27402818

27412819
/**

‎compiler/src/org.graalvm.compiler.asm.amd64/src/org/graalvm/compiler/asm/amd64/AMD64Assembler.java‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,7 @@
4040
import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseAddressNop;
4141
import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseIntelNops;
4242
import static org.graalvm.compiler.asm.amd64.AMD64AsmOptions.UseNormalNop;
43+
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.ADC;
4344
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.ADD;
4445
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.AND;
4546
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.CMP;
@@ -49,8 +50,14 @@
4950
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64BinaryArithmetic.XOR;
5051
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.DEC;
5152
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.INC;
53+
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.MUL;
5254
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NEG;
5355
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64MOp.NOT;
56+
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64RMOp.ADCX;
57+
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64RMOp.ADOX;
58+
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.AMD64Shift.ROR;
59+
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexGeneralPurposeRVMOp.MULX;
60+
import static org.graalvm.compiler.asm.amd64.AMD64Assembler.VexRMIOp.RORXQ;
5461
import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.EVEXPrefixConfig.B0;
5562
import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.EVEXPrefixConfig.Z0;
5663
import static org.graalvm.compiler.asm.amd64.AMD64BaseAssembler.EVEXPrefixConfig.Z1;
@@ -449,6 +456,10 @@ public static class AMD64RMOp extends AMD64RROp {
449456
// TEST is documented as MR operation, but it's symmetric, and using it as RM operation is more convenient.
450457
public static final AMD64RMOp TESTB = new AMD64RMOp("TEST", 0x84, OpAssertion.ByteAssertion);
451458
public static final AMD64RMOp TEST = new AMD64RMOp("TEST", 0x85, OpAssertion.WordOrLargerAssertion);
459+
460+
// ADX instructions
461+
public static final AMD64RMOp ADCX = new AMD64RMOp("ADCX", 0x66, P_0F38, 0xF6, OpAssertion.DwordOrLargerAssertion, CPUFeature.ADX);
462+
public static final AMD64RMOp ADOX = new AMD64RMOp("ADOX", 0xF3, P_0F38, 0xF6, OpAssertion.DwordOrLargerAssertion, CPUFeature.ADX);
452463
// @formatter:on
453464

454465
protected AMD64RMOp(String opcode, int op, OpAssertion assertion) {
@@ -1412,6 +1423,7 @@ public static final class VexRMIOp extends VexOp implements VexRRIOp {
14121423
public static final VexRMIOp VPSHUFLW = new VexRMIOp("VPSHUFLW", P_F2, M_0F, WIG, 0x70, VEXOpAssertion.AVX1_AVX2_AVX512BW_VL, EVEXTuple.FVM, WIG);
14131424
public static final VexRMIOp VPSHUFHW = new VexRMIOp("VPSHUFHW", P_F3, M_0F, WIG, 0x70, VEXOpAssertion.AVX1_AVX2_AVX512BW_VL, EVEXTuple.FVM, WIG);
14141425
public static final VexRMIOp VPSHUFD = new VexRMIOp("VPSHUFD", P_66, M_0F, WIG, 0x70, VEXOpAssertion.AVX1_AVX2_AVX512F_VL, EVEXTuple.FVM, W0);
1426+
public static final VexRMIOp RORXQ = new VexRMIOp("RORXQ", P_F2, M_0F3A, W1, 0xF0, VEXOpAssertion.BMI2);
14151427
// @formatter:on
14161428

14171429
private VexRMIOp(String opcode, int pp, int mmmmm, int w, int op, VEXOpAssertion assertion) {
@@ -4250,6 +4262,18 @@ public final void addq(AMD64Address dst, Register src) {
42504262
ADD.mrOp.emit(this, QWORD, dst, src);
42514263
}
42524264

4265+
public final void adcq(Register dst, int imm32) {
4266+
ADC.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
4267+
}
4268+
4269+
public final void adcxq(Register dst, Register src) {
4270+
ADCX.emit(this, QWORD, dst, src);
4271+
}
4272+
4273+
public final void adoxq(Register dst, Register src) {
4274+
ADOX.emit(this, QWORD, dst, src);
4275+
}
4276+
42534277
public final void andq(Register dst, int imm32) {
42544278
AND.getMIOpcode(QWORD, isByte(imm32)).emit(this, QWORD, dst, imm32);
42554279
}
@@ -4262,6 +4286,23 @@ public final void andq(Register dst, Register src) {
42624286
AND.getRMOpcode(QWORD).emit(this, QWORD, dst, src);
42634287
}
42644288

4289+
public final void mulq(Register src) {
4290+
MUL.emit(this, QWORD, src);
4291+
}
4292+
4293+
public final void mulxq(Register dst1, Register dst2, Register src) {
4294+
MULX.emit(this, AVXSize.QWORD, dst1, dst2, src);
4295+
}
4296+
4297+
public final void rorq(Register dst, int imm8) {
4298+
assert isByte(imm8);
4299+
ROR.miOp.emit(this, QWORD, dst, (byte) imm8);
4300+
}
4301+
4302+
public final void rorxq(Register dst, Register src, int imm8) {
4303+
RORXQ.emit(this, AVXSize.QWORD, dst, src, (byte) imm8);
4304+
}
4305+
42654306
public final void bsrq(Register dst, Register src) {
42664307
prefixq(dst, src);
42674308
emitByte(0x0F);

‎compiler/src/org.graalvm.compiler.core.aarch64/src/org/graalvm/compiler/core/aarch64/AArch64LIRGenerator.java‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@
5757
import org.graalvm.compiler.lir.aarch64.AArch64AtomicMove;
5858
import org.graalvm.compiler.lir.aarch64.AArch64AtomicMove.AtomicReadAndWriteOp;
5959
import org.graalvm.compiler.lir.aarch64.AArch64AtomicMove.CompareAndSwapOp;
60+
import org.graalvm.compiler.lir.aarch64.AArch64BigIntegerMultiplyToLenOp;
6061
import org.graalvm.compiler.lir.aarch64.AArch64ByteSwap;
6162
import org.graalvm.compiler.lir.aarch64.AArch64CacheWritebackOp;
6263
import org.graalvm.compiler.lir.aarch64.AArch64CacheWritebackPostSyncOp;
@@ -603,6 +604,11 @@ public void emitGHASHProcessBlocks(Value state, Value hashSubkey, Value data, Va
603604
append(new AArch64GHASHProcessBlocksOp(this, asAllocatable(state), asAllocatable(hashSubkey), asAllocatable(data), asAllocatable(blocks)));
604605
}
605606

607+
@Override
608+
public void emitBigIntegerMultiplyToLen(Value x, Value xlen, Value y, Value ylen, Value z, Value zlen) {
609+
append(new AArch64BigIntegerMultiplyToLenOp(asAllocatable(x), asAllocatable(xlen), asAllocatable(y), asAllocatable(ylen), asAllocatable(z), asAllocatable(zlen)));
610+
}
611+
606612
@Override
607613
public void emitStringLatin1Inflate(EnumSet<?> runtimeCheckedCPUFeatures, Value src, Value dst, Value len) {
608614
append(new AArch64StringLatin1InflateOp(this, asAllocatable(src), asAllocatable(dst), asAllocatable(len)));

‎compiler/src/org.graalvm.compiler.core.amd64/src/org/graalvm/compiler/core/amd64/AMD64LIRGenerator.java‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,7 @@
7777
import org.graalvm.compiler.lir.amd64.AMD64ArrayEqualsOp;
7878
import org.graalvm.compiler.lir.amd64.AMD64ArrayIndexOfOp;
7979
import org.graalvm.compiler.lir.amd64.AMD64ArrayRegionCompareToOp;
80+
import org.graalvm.compiler.lir.amd64.AMD64BigIntegerMultiplyToLenOp;
8081
import org.graalvm.compiler.lir.amd64.AMD64Binary;
8182
import org.graalvm.compiler.lir.amd64.AMD64BinaryConsumer;
8283
import org.graalvm.compiler.lir.amd64.AMD64ByteSwapOp;
@@ -785,6 +786,25 @@ public void emitGHASHProcessBlocks(Value state, Value hashSubkey, Value data, Va
785786
append(new AMD64GHASHProcessBlocksOp(this, asAllocatable(state), asAllocatable(hashSubkey), asAllocatable(data), asAllocatable(blocks)));
786787
}
787788

789+
@Override
790+
public void emitBigIntegerMultiplyToLen(Value x, Value xlen, Value y, Value ylen, Value z, Value zlen) {
791+
RegisterValue rX = AMD64.rdi.asValue(x.getValueKind());
792+
RegisterValue rXlen = AMD64.rax.asValue(xlen.getValueKind());
793+
RegisterValue rY = AMD64.rsi.asValue(y.getValueKind());
794+
RegisterValue rYlen = AMD64.rcx.asValue(ylen.getValueKind());
795+
RegisterValue rZ = AMD64.r8.asValue(z.getValueKind());
796+
RegisterValue rZlen = AMD64.r11.asValue(zlen.getValueKind());
797+
798+
emitMove(rX, x);
799+
emitMove(rXlen, xlen);
800+
emitMove(rY, y);
801+
emitMove(rYlen, ylen);
802+
emitMove(rZ, z);
803+
emitMove(rZlen, zlen);
804+
805+
append(new AMD64BigIntegerMultiplyToLenOp(rX, rXlen, rY, rYlen, rZ, rZlen, getHeapBaseRegister()));
806+
}
807+
788808
@SuppressWarnings("unchecked")
789809
protected boolean supports(EnumSet<?> runtimeCheckedCPUFeatures, CPUFeature feature) {
790810
assert runtimeCheckedCPUFeatures == null || runtimeCheckedCPUFeatures.isEmpty() || runtimeCheckedCPUFeatures.iterator().next() instanceof CPUFeature;

‎compiler/src/org.graalvm.compiler.hotspot.aarch64/src/org/graalvm/compiler/hotspot/aarch64/AArch64HotSpotLIRGenerator.java‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -473,4 +473,9 @@ public void emitZeroMemory(Value address, Value length, boolean isAligned) {
473473
public int getArrayLengthOffset() {
474474
return config.arrayOopDescLengthOffset();
475475
}
476+
477+
@Override
478+
public Register getHeapBaseRegister() {
479+
return getProviders().getRegisters().getHeapBaseRegister();
480+
}
476481
}

‎compiler/src/org.graalvm.compiler.hotspot.amd64/src/org/graalvm/compiler/hotspot/amd64/AMD64HotSpotLIRGenerator.java‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -633,4 +633,9 @@ private Value combineLoAndHi(Value lo, Value hi) {
633633
public int getArrayLengthOffset() {
634634
return config.arrayOopDescLengthOffset();
635635
}
636+
637+
@Override
638+
public Register getHeapBaseRegister() {
639+
return getProviders().getRegisters().getHeapBaseRegister();
640+
}
636641
}

‎compiler/src/org.graalvm.compiler.hotspot.amd64/src/org/graalvm/compiler/hotspot/amd64/AMD64X87MathSnippets.java‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -84,9 +84,9 @@ public static class Templates extends AbstractTemplates {
8484
public Templates(OptionValues options, Providers providers) {
8585
super(options, providers);
8686

87-
sin = snippet(AMD64X87MathSnippets.class, "sin");
88-
cos = snippet(AMD64X87MathSnippets.class, "cos");
89-
tan = snippet(AMD64X87MathSnippets.class, "tan");
87+
sin = snippet(providers, AMD64X87MathSnippets.class, "sin");
88+
cos = snippet(providers, AMD64X87MathSnippets.class, "cos");
89+
tan = snippet(providers, AMD64X87MathSnippets.class, "tan");
9090
}
9191

9292
public void lower(UnaryMathIntrinsicNode mathIntrinsicNode, LoweringTool tool) {
@@ -108,7 +108,7 @@ public void lower(UnaryMathIntrinsicNode mathIntrinsicNode, LoweringTool tool) {
108108

109109
Arguments args = new Arguments(info, mathIntrinsicNode.graph().getGuardsStage(), tool.getLoweringStage());
110110
args.add("input", mathIntrinsicNode.getValue());
111-
template(mathIntrinsicNode, args).instantiate(providers.getMetaAccess(), mathIntrinsicNode, DEFAULT_REPLACER, tool, args);
111+
template(tool, mathIntrinsicNode, args).instantiate(tool.getMetaAccess(), mathIntrinsicNode, DEFAULT_REPLACER, tool, args);
112112
mathIntrinsicNode.safeDelete();
113113
}
114114
}

‎compiler/src/org.graalvm.compiler.hotspot/src/org/graalvm/compiler/hotspot/HotSpotBackend.java‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,6 @@
5353
import org.graalvm.compiler.hotspot.meta.HotSpotForeignCallDescriptor;
5454
import org.graalvm.compiler.hotspot.meta.HotSpotProviders;
5555
import org.graalvm.compiler.hotspot.nodes.VMErrorNode;
56-
import org.graalvm.compiler.hotspot.replacements.BigIntegerSnippets;
5756
import org.graalvm.compiler.hotspot.stubs.ExceptionHandlerStub;
5857
import org.graalvm.compiler.hotspot.stubs.Stub;
5958
import org.graalvm.compiler.hotspot.stubs.UnwindExceptionToCallerStub;
@@ -154,20 +153,6 @@ public static class Options {
154153
public static final HotSpotForeignCallDescriptor CIPHER_BLOCK_CHAINING_DECRYPT_AESCRYPT = new HotSpotForeignCallDescriptor(LEAF, NOT_REEXECUTABLE,
155154
NamedLocationIdentity.getArrayLocation(JavaKind.Byte), "cipherBlockChaining_decrypt_aescrypt", int.class, Word.class, Word.class, Pointer.class, Pointer.class, int.class);
156155

157-
/**
158-
* @see BigIntegerSnippets#implMultiplyToLen(int[], int, int[], int, int[])
159-
*/
160-
public static final HotSpotForeignCallDescriptor MULTIPLY_TO_LEN = new HotSpotForeignCallDescriptor(LEAF_NO_VZERO, NOT_REEXECUTABLE, NamedLocationIdentity.getArrayLocation(JavaKind.Int),
161-
"multiplyToLen",
162-
void.class, Word.class, int.class, Word.class, int.class, Word.class, int.class);
163-
164-
public static void multiplyToLenStub(Word xAddr, int xlen, Word yAddr, int ylen, Word zAddr, int zLen) {
165-
multiplyToLenStub(HotSpotBackend.MULTIPLY_TO_LEN, xAddr, xlen, yAddr, ylen, zAddr, zLen);
166-
}
167-
168-
@NodeIntrinsic(ForeignCallNode.class)
169-
private static native void multiplyToLenStub(@ConstantNodeParameter ForeignCallDescriptor descriptor, Word xIn, int xLen, Word yIn, int yLen, Word zIn, int zLen);
170-
171156
public static final HotSpotForeignCallDescriptor MUL_ADD = new HotSpotForeignCallDescriptor(LEAF_NO_VZERO, NOT_REEXECUTABLE, NamedLocationIdentity.getArrayLocation(JavaKind.Int), "mulAdd",
172157
int.class, Word.class, Word.class, int.class, int.class, int.class);
173158

‎compiler/src/org.graalvm.compiler.hotspot/src/org/graalvm/compiler/hotspot/meta/DefaultHotSpotLoweringProvider.java‎

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@@ -77,7 +77,6 @@
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import org.graalvm.compiler.hotspot.nodes.type.KlassPointerStamp;
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import org.graalvm.compiler.hotspot.nodes.type.MethodPointerStamp;
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import org.graalvm.compiler.hotspot.replacements.AssertionSnippets;
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import org.graalvm.compiler.hotspot.replacements.BigIntegerSnippets;
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import org.graalvm.compiler.hotspot.replacements.ClassGetHubNode;
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import org.graalvm.compiler.hotspot.replacements.DigestBaseSnippets;
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import org.graalvm.compiler.hotspot.replacements.FastNotifyNode;
@@ -319,7 +318,6 @@ public void initialize(OptionValues options, Iterable<DebugHandlersFactory> fact
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objectSnippets = new ObjectSnippets.Templates(options, providers);
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unsafeSnippets = new UnsafeSnippets.Templates(options, providers);
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replacements.registerSnippetTemplateCache(new BigIntegerSnippets.Templates(options, providers));
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replacements.registerSnippetTemplateCache(new DigestBaseSnippets.Templates(options, providers));
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initializeExtensions(options, factories, providers, config);

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