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Merge tag 'pull-target-arm-20240701' of https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue: * tests/avocado: update firmware for sbsa-ref and use all cores * hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev * arm: Fix VCMLA Dd, Dn, Dm[idx] * arm: Fix SQDMULH (by element) with Q=0 * arm: Fix FJCVTZS vs flush-to-zero * arm: More conversion of A64 AdvSIMD to decodetree * arm: Enable FEAT_Debugv8p8 for -cpu max * MAINTAINERS: Update family name for Patrick Leis * hw/arm/xilinx_zynq: Add boot-mode property * docs/system/arm: Add a doc for zynq board * hw/misc: In STM32L4x5 EXTI, correct configurable interrupts * tests/qtest: fix minor issues in STM32L4x5 tests # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmaC1BMZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3nDOEACCoewjO2FJ4RFXMSmgr0Zf # jxWliu7osw7oeG4ZNq1+xMiXeW0vyS54eW41TMki1f98N/yK8v55BM8kBBvDvZaz # R5DUXpN+MtwD9A62md3B2c4mFXHqk1UOGbKi4btbtFj4lS8pV51mPmApzBUr2iTj # w6dCLciLOt87NWgtLECXsZ3evn+VlTRc+Hmfp1M/C/Rf2Qx3zis/CFHGQsZLGwzG # 2WhTpU1BKeOfsQa1VbSX6un14d72/JATFZN3rSgMbOEbvsCEeP+rnkzX57ejGyxV # 4DUx69gEAqS5bOfkQHLwy82WsunD/oIgp+GpYaYgINHzh6UkEsPoymrHAaPgV1Vh # g0TaBtbv2p89RFY1C2W2Mi4ICQ14a+oIV9FPvDsOE8Wq+wDAy/ZxZs7G6flxqods # s4JvcMqB3kUNBZaMsFVXTKdqT1PufICS+gx0VsKdKDwXcOHwMS10nTlEOPzqvoBA # phAsEbjnjWVhf03XTfCus+l5NT96lswCzPcUovb3CitSc2A1KUye3TyzHnxIqmOt # Owcl+Oiso++cgYzr/BCveTAYKYoRZzVcq5jCl4bBUH/8sLrRDbT0cpFpcMk72eE9 # VhR00kbkDfL3nKrulLsG8FeUlisX5+oGb3G5AdPtU9sqJPJMmBGaF+KniI0wi7VN # 5teHq08upLMF5JAjiKzZIA== # =faXD # -----END PGP SIGNATURE----- # gpg: Signature made Mon 01 Jul 2024 09:06:43 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "[email protected]" # gpg: Good signature from "Peter Maydell <[email protected]>" [full] # gpg: aka "Peter Maydell <[email protected]>" [full] # gpg: aka "Peter Maydell <[email protected]>" [full] # gpg: aka "Peter Maydell <[email protected]>" [unknown] * tag 'pull-target-arm-20240701' of https://git.linaro.org/people/pmaydell/qemu-arm: (29 commits) tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests hw/misc: In STM32L4x5 EXTI, correct configurable interrupts tests/qtest: Fix STM32L4x5 SYSCFG irq line 15 state assumption docs/system/arm: Add a doc for zynq board hw/arm/xilinx_zynq: Add boot-mode property hw/misc/zynq_slcr: Add boot-mode property MAINTAINERS: Update my family name target/arm: Enable FEAT_Debugv8p8 for -cpu max target/arm: Move initialization of debug ID registers target/arm: Fix indentation target/arm: Delete dead code from disas_simd_indexed target/arm: Convert FCMLA to decodetree target/arm: Convert FCADD to decodetree target/arm: Add data argument to do_fp3_vector target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree target/arm: Convert BFMLALB, BFMLALT to decodetree target/arm: Convert BFDOT to decodetree target/arm: Convert SUDOT, USDOT to decodetree target/arm: Convert SDOT, UDOT to decodetree target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree ... Signed-off-by: Richard Henderson <[email protected]>
2 parents 1152a04 + 58c782d commit c80a339

32 files changed

+967
-641
lines changed

‎MAINTAINERS

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1033,6 +1033,7 @@ F: hw/adc/zynq-xadc.c
10331033
F: include/hw/misc/zynq_slcr.h
10341034
F: include/hw/adc/zynq-xadc.h
10351035
X: hw/ssi/xilinx_*
1036+
F: docs/system/arm/xlnx-zynq.rst
10361037

10371038
Xilinx ZynqMP and Versal
10381039
M: Alistair Francis <[email protected]>
@@ -2496,7 +2497,7 @@ F: hw/net/tulip.c
24962497
F: hw/net/tulip.h
24972498

24982499
pca954x
2499-
M: Patrick Venture <[email protected]>
2500+
M: Patrick Leis <[email protected]>
25002501
S: Maintained
25012502
F: hw/i2c/i2c_mux_pca954x.c
25022503
F: include/hw/i2c/i2c_mux_pca954x.h

‎docs/system/arm/emulation.rst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ the following architecture extensions:
4141
- FEAT_Debugv8p1 (Debug with VHE)
4242
- FEAT_Debugv8p2 (Debug changes for v8.2)
4343
- FEAT_Debugv8p4 (Debug changes for v8.4)
44+
- FEAT_Debugv8p8 (Debug changes for v8.8)
4445
- FEAT_DotProd (Advanced SIMD dot product instructions)
4546
- FEAT_DoubleFault (Double Fault Extension)
4647
- FEAT_E0PD (Preventing EL0 access to halves of address maps)

‎docs/system/arm/xlnx-zynq.rst

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
Xilinx Zynq board (``xilinx-zynq-a9``)
2+
======================================
3+
The Zynq 7000 family is based on the AMD SoC architecture. These products
4+
integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
5+
processing system (PS) and AMD programmable logic (PL) in a single device.
6+
7+
More details here:
8+
https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
9+
10+
QEMU xilinx-zynq-a9 board supports following devices:
11+
- A9 MPCORE
12+
- cortex-a9
13+
- GIC v1
14+
- Generic timer
15+
- wdt
16+
- OCM 256KB
17+
- SMC SRAM@0xe2000000 64MB
18+
- Zynq SLCR
19+
- SPI x2
20+
- QSPI
21+
- UART
22+
- TTC x2
23+
- Gigabit Ethernet Controller x2
24+
- SD Controller x2
25+
- XADC
26+
- Arm PrimeCell DMA Controller
27+
- DDR Memory
28+
- USB 2.0 x2
29+
30+
Running
31+
"""""""
32+
Direct Linux boot of a generic ARM upstream Linux kernel:
33+
34+
.. code-block:: bash
35+
36+
$ qemu-system-aarch64 -M xilinx-zynq-a9 \
37+
-dtb zynq-zc702.dtb -serial null -serial mon:stdio \
38+
-display none -m 1024 \
39+
-initrd rootfs.cpio.gz -kernel zImage
40+
41+
For configuring the boot-mode provide the following on the command line:
42+
43+
.. code-block:: bash
44+
45+
-machine boot-mode=qspi
46+
47+
Supported values are jtag, sd, qspi, nor.

‎docs/system/target-arm.rst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,7 @@ undocumented; you can get a complete list by running
109109
arm/virt
110110
arm/xenpvh
111111
arm/xlnx-versal-virt
112+
arm/xlnx-zynq
112113

113114
Emulated CPU architecture support
114115
=================================

‎hw/arm/bcm2835_peripherals.c

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,10 @@ static void raspi_peripherals_base_init(Object *obj)
116116
object_property_add_const_link(OBJECT(&s->fb), "dma-mr",
117117
OBJECT(&s->gpu_bus_mr));
118118

119+
/* OTP */
120+
object_initialize_child(obj, "bcm2835-otp", &s->otp,
121+
TYPE_BCM2835_OTP);
122+
119123
/* Property channel */
120124
object_initialize_child(obj, "property", &s->property,
121125
TYPE_BCM2835_PROPERTY);
@@ -128,6 +132,8 @@ static void raspi_peripherals_base_init(Object *obj)
128132
OBJECT(&s->fb));
129133
object_property_add_const_link(OBJECT(&s->property), "dma-mr",
130134
OBJECT(&s->gpu_bus_mr));
135+
object_property_add_const_link(OBJECT(&s->property), "otp",
136+
OBJECT(&s->otp));
131137

132138
/* Extended Mass Media Controller */
133139
object_initialize_child(obj, "sdhci", &s->sdhci, TYPE_SYSBUS_SDHCI);
@@ -374,6 +380,14 @@ void bcm_soc_peripherals_common_realize(DeviceState *dev, Error **errp)
374380
sysbus_connect_irq(SYS_BUS_DEVICE(&s->fb), 0,
375381
qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_FB));
376382

383+
/* OTP */
384+
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
385+
return;
386+
}
387+
388+
memory_region_add_subregion(&s->peri_mr, OTP_OFFSET,
389+
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->otp), 0));
390+
377391
/* Property channel */
378392
if (!sysbus_realize(SYS_BUS_DEVICE(&s->property), errp)) {
379393
return;
@@ -500,7 +514,6 @@ void bcm_soc_peripherals_common_realize(DeviceState *dev, Error **errp)
500514
create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100);
501515
create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100);
502516
create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100);
503-
create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
504517
create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
505518
create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
506519
create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000);

‎hw/arm/smmu-common.c

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -620,20 +620,16 @@ static const PCIIOMMUOps smmu_ops = {
620620
.get_address_space = smmu_find_add_as,
621621
};
622622

623-
IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
623+
SMMUDevice *smmu_find_sdev(SMMUState *s, uint32_t sid)
624624
{
625625
uint8_t bus_n, devfn;
626626
SMMUPciBus *smmu_bus;
627-
SMMUDevice *smmu;
628627

629628
bus_n = PCI_BUS_NUM(sid);
630629
smmu_bus = smmu_find_smmu_pcibus(s, bus_n);
631630
if (smmu_bus) {
632631
devfn = SMMU_PCI_DEVFN(sid);
633-
smmu = smmu_bus->pbdev[devfn];
634-
if (smmu) {
635-
return &smmu->iommu;
636-
}
632+
return smmu_bus->pbdev[devfn];
637633
}
638634
return NULL;
639635
}

‎hw/arm/smmuv3.c

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1218,20 +1218,18 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
12181218
case SMMU_CMD_CFGI_STE:
12191219
{
12201220
uint32_t sid = CMD_SID(&cmd);
1221-
IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, sid);
1222-
SMMUDevice *sdev;
1221+
SMMUDevice *sdev = smmu_find_sdev(bs, sid);
12231222

12241223
if (CMD_SSEC(&cmd)) {
12251224
cmd_error = SMMU_CERROR_ILL;
12261225
break;
12271226
}
12281227

1229-
if (!mr) {
1228+
if (!sdev) {
12301229
break;
12311230
}
12321231

12331232
trace_smmuv3_cmdq_cfgi_ste(sid);
1234-
sdev = container_of(mr, SMMUDevice, iommu);
12351233
smmuv3_flush_config(sdev);
12361234

12371235
break;
@@ -1260,20 +1258,18 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
12601258
case SMMU_CMD_CFGI_CD_ALL:
12611259
{
12621260
uint32_t sid = CMD_SID(&cmd);
1263-
IOMMUMemoryRegion *mr = smmu_iommu_mr(bs, sid);
1264-
SMMUDevice *sdev;
1261+
SMMUDevice *sdev = smmu_find_sdev(bs, sid);
12651262

12661263
if (CMD_SSEC(&cmd)) {
12671264
cmd_error = SMMU_CERROR_ILL;
12681265
break;
12691266
}
12701267

1271-
if (!mr) {
1268+
if (!sdev) {
12721269
break;
12731270
}
12741271

12751272
trace_smmuv3_cmdq_cfgi_cd(sid);
1276-
sdev = container_of(mr, SMMUDevice, iommu);
12771273
smmuv3_flush_config(sdev);
12781274
break;
12791275
}

‎hw/arm/xilinx_zynq.c

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,7 @@
3838
#include "qom/object.h"
3939
#include "exec/tswap.h"
4040
#include "target/arm/cpu-qom.h"
41+
#include "qapi/visitor.h"
4142

4243
#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9")
4344
OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE)
@@ -90,6 +91,7 @@ struct ZynqMachineState {
9091
MachineState parent;
9192
Clock *ps_clk;
9293
ARMCPU *cpu[ZYNQ_MAX_CPUS];
94+
uint8_t boot_mode;
9395
};
9496

9597
static void zynq_write_board_setup(ARMCPU *cpu,
@@ -176,6 +178,27 @@ static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
176178
return unit;
177179
}
178180

181+
static void zynq_set_boot_mode(Object *obj, const char *str,
182+
Error **errp)
183+
{
184+
ZynqMachineState *m = ZYNQ_MACHINE(obj);
185+
uint8_t mode = 0;
186+
187+
if (!strncasecmp(str, "qspi", 4)) {
188+
mode = 1;
189+
} else if (!strncasecmp(str, "sd", 2)) {
190+
mode = 5;
191+
} else if (!strncasecmp(str, "nor", 3)) {
192+
mode = 2;
193+
} else if (!strncasecmp(str, "jtag", 4)) {
194+
mode = 0;
195+
} else {
196+
error_setg(errp, "%s boot mode not supported", str);
197+
return;
198+
}
199+
m->boot_mode = mode;
200+
}
201+
179202
static void zynq_init(MachineState *machine)
180203
{
181204
ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine);
@@ -241,6 +264,7 @@ static void zynq_init(MachineState *machine)
241264
/* Create slcr, keep a pointer to connect clocks */
242265
slcr = qdev_new("xilinx-zynq_slcr");
243266
qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk);
267+
qdev_prop_set_uint8(slcr, "boot-mode", zynq_machine->boot_mode);
244268
sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal);
245269
sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000);
246270

@@ -373,13 +397,20 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data)
373397
NULL
374398
};
375399
MachineClass *mc = MACHINE_CLASS(oc);
400+
ObjectProperty *prop;
376401
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
377402
mc->init = zynq_init;
378403
mc->max_cpus = ZYNQ_MAX_CPUS;
379404
mc->no_sdcard = 1;
380405
mc->ignore_memory_transaction_failures = true;
381406
mc->valid_cpu_types = valid_cpu_types;
382407
mc->default_ram_id = "zynq.ext_ram";
408+
prop = object_class_property_add_str(oc, "boot-mode", NULL,
409+
zynq_set_boot_mode);
410+
object_class_property_set_description(oc, "boot-mode",
411+
"Supported boot modes:"
412+
" jtag qspi sd nor");
413+
object_property_set_default_str(prop, "qspi");
383414
}
384415

385416
static const TypeInfo zynq_machine_type = {

‎hw/misc/bcm2835_property.c

Lines changed: 87 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
3232
uint32_t tmp;
3333
int n;
3434
uint32_t offset, length, color;
35+
uint32_t start_num, number, otp_row;
3536

3637
/*
3738
* Copy the current state of the framebuffer config; we will update
@@ -322,6 +323,89 @@ static void bcm2835_property_mbox_push(BCM2835PropertyState *s, uint32_t value)
322323
0);
323324
resplen = VCHI_BUSADDR_SIZE;
324325
break;
326+
327+
/* Customer OTP */
328+
329+
case RPI_FWREQ_GET_CUSTOMER_OTP:
330+
start_num = ldl_le_phys(&s->dma_as, value + 12);
331+
number = ldl_le_phys(&s->dma_as, value + 16);
332+
333+
resplen = 8 + 4 * number;
334+
335+
for (n = start_num; n < start_num + number &&
336+
n < BCM2835_OTP_CUSTOMER_OTP_LEN; n++) {
337+
otp_row = bcm2835_otp_get_row(s->otp,
338+
BCM2835_OTP_CUSTOMER_OTP + n);
339+
stl_le_phys(&s->dma_as,
340+
value + 20 + ((n - start_num) << 2), otp_row);
341+
}
342+
break;
343+
case RPI_FWREQ_SET_CUSTOMER_OTP:
344+
start_num = ldl_le_phys(&s->dma_as, value + 12);
345+
number = ldl_le_phys(&s->dma_as, value + 16);
346+
347+
resplen = 4;
348+
349+
/* Magic numbers to permanently lock customer OTP */
350+
if (start_num == BCM2835_OTP_LOCK_NUM1 &&
351+
number == BCM2835_OTP_LOCK_NUM2) {
352+
bcm2835_otp_set_row(s->otp,
353+
BCM2835_OTP_ROW_32,
354+
BCM2835_OTP_ROW_32_LOCK);
355+
break;
356+
}
357+
358+
/* If row 32 has the lock bit, don't allow further writes */
359+
if (bcm2835_otp_get_row(s->otp, BCM2835_OTP_ROW_32) &
360+
BCM2835_OTP_ROW_32_LOCK) {
361+
break;
362+
}
363+
364+
for (n = start_num; n < start_num + number &&
365+
n < BCM2835_OTP_CUSTOMER_OTP_LEN; n++) {
366+
otp_row = ldl_le_phys(&s->dma_as,
367+
value + 20 + ((n - start_num) << 2));
368+
bcm2835_otp_set_row(s->otp,
369+
BCM2835_OTP_CUSTOMER_OTP + n, otp_row);
370+
}
371+
break;
372+
373+
/* Device-specific private key */
374+
375+
case RPI_FWREQ_GET_PRIVATE_KEY:
376+
start_num = ldl_le_phys(&s->dma_as, value + 12);
377+
number = ldl_le_phys(&s->dma_as, value + 16);
378+
379+
resplen = 8 + 4 * number;
380+
381+
for (n = start_num; n < start_num + number &&
382+
n < BCM2835_OTP_PRIVATE_KEY_LEN; n++) {
383+
otp_row = bcm2835_otp_get_row(s->otp,
384+
BCM2835_OTP_PRIVATE_KEY + n);
385+
stl_le_phys(&s->dma_as,
386+
value + 20 + ((n - start_num) << 2), otp_row);
387+
}
388+
break;
389+
case RPI_FWREQ_SET_PRIVATE_KEY:
390+
start_num = ldl_le_phys(&s->dma_as, value + 12);
391+
number = ldl_le_phys(&s->dma_as, value + 16);
392+
393+
resplen = 4;
394+
395+
/* If row 32 has the lock bit, don't allow further writes */
396+
if (bcm2835_otp_get_row(s->otp, BCM2835_OTP_ROW_32) &
397+
BCM2835_OTP_ROW_32_LOCK) {
398+
break;
399+
}
400+
401+
for (n = start_num; n < start_num + number &&
402+
n < BCM2835_OTP_PRIVATE_KEY_LEN; n++) {
403+
otp_row = ldl_le_phys(&s->dma_as,
404+
value + 20 + ((n - start_num) << 2));
405+
bcm2835_otp_set_row(s->otp,
406+
BCM2835_OTP_PRIVATE_KEY + n, otp_row);
407+
}
408+
break;
325409
default:
326410
qemu_log_mask(LOG_UNIMP,
327411
"bcm2835_property: unhandled tag 0x%08x\n", tag);
@@ -449,6 +533,9 @@ static void bcm2835_property_realize(DeviceState *dev, Error **errp)
449533
s->dma_mr = MEMORY_REGION(obj);
450534
address_space_init(&s->dma_as, s->dma_mr, TYPE_BCM2835_PROPERTY "-memory");
451535

536+
obj = object_property_get_link(OBJECT(dev), "otp", &error_abort);
537+
s->otp = BCM2835_OTP(obj);
538+
452539
/* TODO: connect to MAC address of USB NIC device, once we emulate it */
453540
qemu_macaddr_default_if_unset(&s->macaddr);
454541

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