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amlogic: maintenance
odroid 5.15.y hdmi color correction as reported here: tobetter/linux#37
1 parent 0fa8ace commit 164bb55

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2 files changed

+33
-163
lines changed

2 files changed

+33
-163
lines changed

‎patches/amlogic/all/017-fix-hdmi-colors.patch

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
2+
index 3e1be9894..eee410758 100644
3+
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
4+
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
5+
@@ -2719,6 +2719,9 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
6+
* if supported. In any case the default RGB888 format is added
7+
*/
8+
9+
+ /* Default 8bit RGB fallback */
10+
+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
11+
+
12+
if (max_bpc >= 16 && info->bpc == 16) {
13+
if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
14+
output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48;
15+
@@ -2752,9 +2755,6 @@ static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
16+
if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444)
17+
output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24;
18+
19+
- /* Default 8bit RGB fallback */
20+
- output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24;
21+
-
22+
*num_output_fmts = i;
23+
24+
return output_fmts;

‎patches/amlogic/odroid/5.15/002-linux-odroid-patch-set.patch

Lines changed: 9 additions & 163 deletions
Original file line numberDiff line numberDiff line change
@@ -669,178 +669,24 @@ diff -Naur a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_ve
669669

670670
return MODE_OK;
671671
diff -Naur a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
672-
--- a/drivers/gpu/drm/meson/meson_viu.c 2021-10-18 02:00:13.000000000 -0400
673-
+++ b/drivers/gpu/drm/meson/meson_viu.c 2021-10-19 00:24:08.000000000 -0400
674-
@@ -78,32 +78,52 @@
675-
EOTF_COEFF_RIGHTSHIFT /* right shift */
676-
};
677-
678-
-static void meson_viu_set_g12a_osd1_matrix(struct meson_drm *priv,
679-
- int *m, bool csc_on)
680-
+static void meson_viu_set_g12a_osd_matrix(struct meson_drm *priv,
681-
+ int *m, bool csc_on)
682-
{
683-
/* VPP WRAP OSD1 matrix */
684-
writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
685-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1));
686-
+ writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
687-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1));
688-
writel(m[2] & 0xfff,
689-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2));
690-
+ writel(m[2] & 0xfff,
691-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2));
692-
writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
693-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF00_01));
694-
+ writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
695-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_COEF00_01));
696-
writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
697-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF02_10));
698-
+ writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
699-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_COEF02_10));
700-
writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
701-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF11_12));
702-
+ writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
703-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_COEF11_12));
704-
writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
705-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF20_21));
706-
+ writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
707-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_COEF20_21));
708-
writel((m[11] & 0x1fff) << 16,
709-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_COEF22));
710-
+ writel((m[11] & 0x1fff) << 16,
711-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_COEF22));
712-
713-
writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
714-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET0_1));
715-
+ writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
716-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_OFFSET0_1));
717-
writel(m[20] & 0xfff,
718-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_OFFSET2));
719-
+ writel(m[20] & 0xfff,
720-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_OFFSET2));
721-
722-
writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
723-
priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL));
724-
+ writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
725-
+ priv->io_base + _REG(VPP_WRAP_OSD2_MATRIX_EN_CTRL));
726-
}
727-
728-
static void meson_viu_set_osd_matrix(struct meson_drm *priv,
729-
@@ -114,21 +134,36 @@
730-
/* osd matrix, VIU_MATRIX_0 */
731-
writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
732-
priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET0_1));
733-
+ writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff),
734-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_PRE_OFFSET0_1));
735-
writel(m[2] & 0xfff,
736-
priv->io_base + _REG(VIU_OSD1_MATRIX_PRE_OFFSET2));
737-
+ writel(m[2] & 0xfff,
738-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_PRE_OFFSET2));
739-
writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
740-
priv->io_base + _REG(VIU_OSD1_MATRIX_COEF00_01));
741-
+ writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff),
742-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_COEF00_01));
743-
writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
744-
priv->io_base + _REG(VIU_OSD1_MATRIX_COEF02_10));
745-
+ writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff),
746-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_COEF02_10));
747-
writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
748-
priv->io_base + _REG(VIU_OSD1_MATRIX_COEF11_12));
749-
+ writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff),
750-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_COEF11_12));
751-
writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
752-
priv->io_base + _REG(VIU_OSD1_MATRIX_COEF20_21));
753-
+ writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff),
754-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_COEF20_21));
755-
756-
if (m[21]) {
757-
writel(((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff),
758-
priv->io_base +
759-
_REG(VIU_OSD1_MATRIX_COEF22_30));
760-
+ writel(((m[11] & 0x1fff) << 16),
761-
+ priv->io_base +
762-
+ _REG(VIU_OSD2_MATRIX_COEF22));
763-
writel(((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff),
764-
priv->io_base +
765-
_REG(VIU_OSD1_MATRIX_COEF31_32));
766-
@@ -137,14 +172,21 @@
767-
_REG(VIU_OSD1_MATRIX_COEF40_41));
768-
writel(m[17] & 0x1fff, priv->io_base +
769-
_REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
770-
- } else
771-
+ } else {
772-
writel((m[11] & 0x1fff) << 16, priv->io_base +
773-
_REG(VIU_OSD1_MATRIX_COEF22_30));
774-
+ writel((m[11] & 0x1fff) << 16, priv->io_base +
775-
+ _REG(VIU_OSD2_MATRIX_COEF22));
776-
+ }
777-
778-
writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
779-
priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET0_1));
780-
+ writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff),
781-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_OFFSET0_1));
782-
writel(m[20] & 0xfff,
783-
priv->io_base + _REG(VIU_OSD1_MATRIX_OFFSET2));
784-
+ writel(m[20] & 0xfff,
785-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_OFFSET2));
786-
787-
writel_bits_relaxed(3 << 30, m[21] << 30,
788-
priv->io_base + _REG(VIU_OSD1_MATRIX_COLMOD_COEF42));
789-
@@ -154,8 +196,12 @@
790-
/* 23 reserved for clipping control */
791-
writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
792-
priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
793-
+ writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0,
794-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_CTRL));
795-
writel_bits_relaxed(BIT(1), 0,
796-
priv->io_base + _REG(VIU_OSD1_MATRIX_CTRL));
797-
+ writel_bits_relaxed(BIT(1), 0,
798-
+ priv->io_base + _REG(VIU_OSD2_MATRIX_CTRL));
799-
} else if (m_select == VIU_MATRIX_OSD_EOTF) {
800-
int i;
801-
802-
@@ -425,14 +471,12 @@
672+
--- a/drivers/gpu/drm/meson/meson_viu.c 2022-08-17 09:16:21.000000000 -0400
673+
+++ b/drivers/gpu/drm/meson/meson_viu.c 2022-08-18 21:44:58.000000000 -0400
674+
@@ -425,6 +425,7 @@
803675
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
804676
meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
805677
meson_viu_load_matrix(priv);
806-
- else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
807-
- meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
808678
+#if 0
809-
+ /* FIXME: */
810-
+ else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
811-
+ meson_viu_set_g12a_osd_matrix(priv, RGB709_to_YUV709l_coeff,
679+
else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
680+
meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
812681
true);
813-
- /* fix green/pink color distortion from vendor u-boot */
814-
- writel_bits_relaxed(OSD1_HDR2_CTRL_REG_ONLY_MAT |
815-
- OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0,
816-
- priv->io_base + _REG(OSD1_HDR2_CTRL));
817-
- }
682+
@@ -433,6 +434,7 @@
683+
OSD1_HDR2_CTRL_VDIN0_HDR2_TOP_EN, 0,
684+
priv->io_base + _REG(OSD1_HDR2_CTRL));
685+
}
818686
+#endif
819687

820688
/* Initialize OSD1 fifo control register */
821689
reg = VIU_OSD_DDR_PRIORITY_URGENT |
822-
@@ -469,14 +513,13 @@
823-
priv->io_base + _REG(VD2_IF0_LUMA_FIFO_SIZE));
824-
825-
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
826-
- writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) |
827-
- VIU_OSD_BLEND_REORDER(1, 0) |
828-
- VIU_OSD_BLEND_REORDER(2, 0) |
829-
- VIU_OSD_BLEND_REORDER(3, 0) |
830-
- VIU_OSD_BLEND_DIN_EN(1) |
831-
- VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 |
832-
- VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 |
833-
- VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 |
834-
+ /* setup bypass to have OSD1->DOUT0 + OSD2->DOUT1 */
835-
+ writel_relaxed(VIU_OSD_BLEND_REORDER(0, 1) | /* OSD1 to DIN0 */
836-
+ VIU_OSD_BLEND_REORDER(1, 4) |
837-
+ VIU_OSD_BLEND_REORDER(2, 4) |
838-
+ VIU_OSD_BLEND_REORDER(3, 2) | /* OSD2 to DIN3 */
839-
+ VIU_OSD_BLEND_DIN_EN(9) | /* Enable DIN0 & DIN3 */
840-
+ VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 | /* DIN0 to DOUT0 */
841-
VIU_OSD_BLEND_BLEN2_PREMULT_EN(1) |
842-
VIU_OSD_BLEND_HOLD_LINES(4),
843-
priv->io_base + _REG(VIU_OSD_BLEND_CTRL));
844690
diff -Naur a/drivers/gpu/drm/tiny/ili9341.c b/drivers/gpu/drm/tiny/ili9341.c
845691
--- a/drivers/gpu/drm/tiny/ili9341.c 2021-10-18 02:00:13.000000000 -0400
846692
+++ b/drivers/gpu/drm/tiny/ili9341.c 2021-10-19 00:24:08.000000000 -0400

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