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net: dsa: mt7530: trap link-local frames regardless of ST Port State
In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL) of the Open Systems Interconnection basic reference model (OSI/RM) are described; the medium access control (MAC) and logical link control (LLC) sublayers. The MAC sublayer is the one facing the physical layer. In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A Bridge component comprises a MAC Relay Entity for interconnecting the Ports of the Bridge, at least two Ports, and higher layer entities with at least a Spanning Tree Protocol Entity included. Each Bridge Port also functions as an end station and shall provide the MAC Service to an LLC Entity. Each instance of the MAC Service is provided to a distinct LLC Entity that supports protocol identification, multiplexing, and demultiplexing, for protocol data unit (PDU) transmission and reception by one or more higher layer entities. It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC Entity associated with each Bridge Port is modeled as being directly connected to the attached Local Area Network (LAN). On the switch with CPU port architecture, CPU port functions as Management Port, and the Management Port functionality is provided by software which functions as an end station. Software is connected to an IEEE 802 LAN that is wholly contained within the system that incorporates the Bridge. Software provides access to the LLC Entity associated with each Bridge Port by the value of the source port field on the special tag on the frame received by software. We call frames that carry control information to determine the active topology and current extent of each Virtual Local Area Network (VLAN), i.e., spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration Protocol Data Units (MVRPDUs), and frames from other link constrained protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and Link Layer Discovery Protocol (LLDP), link-local frames. They are not forwarded by a Bridge. Permanently configured entries in the filtering database (FDB) ensure that such frames are discarded by the Forwarding Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail: Each of the reserved MAC addresses specified in Table 8-1 (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be permanently configured in the FDB in C-VLAN components and ERs. Each of the reserved MAC addresses specified in Table 8-2 (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently configured in the FDB in S-VLAN components. Each of the reserved MAC addresses specified in Table 8-3 (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in TPMR components. The FDB entries for reserved MAC addresses shall specify filtering for all Bridge Ports and all VIDs. Management shall not provide the capability to modify or remove entries for reserved MAC addresses. The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of propagation of PDUs within a Bridged Network, as follows: The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN) component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward. PDUs transmitted using this destination address, or any other addresses that appear in Table 8-1, Table 8-2, and Table 8-3 (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can therefore travel no further than those stations that can be reached via a single individual LAN from the originating station. The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an address that no conformant S-VLAN component, C-VLAN component, or MAC Bridge can forward; however, this address is relayed by a TPMR component. PDUs using this destination address, or any of the other addresses that appear in both Table 8-1 and Table 8-2 but not in Table 8-3 (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by any TPMRs but will propagate no further than the nearest S-VLAN component, C-VLAN component, or MAC Bridge. The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address that no conformant C-VLAN component, MAC Bridge can forward; however, it is relayed by TPMR components and S-VLAN components. PDUs using this destination address, or any of the other addresses that appear in Table 8-1 but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]), will be relayed by TPMR components and S-VLAN components but will propagate no further than the nearest C-VLAN component or MAC Bridge. Because the LLC Entity associated with each Bridge Port is provided via CPU port, we must not filter these frames but forward them to CPU port. In a Bridge, the transmission Port is majorly decided by ingress and egress rules, FDB, and spanning tree Port State functions of the Forwarding Process. For link-local frames, only CPU port should be designated as destination port in the FDB, and the other functions of the Forwarding Process must not interfere with the decision of the transmission Port. We call this process trapping frames to CPU port. Therefore, on the switch with CPU port architecture, link-local frames must be trapped to CPU port, and certain link-local frames received by a Port of a Bridge comprising a TPMR component or an S-VLAN component must be excluded from it. A Bridge of the switch with CPU port architecture cannot comprise a Two-Port MAC Relay (TPMR) component as a TPMR component supports only a subset of the functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port doesn't count) of this architecture will either function as a standard MAC Bridge or a standard VLAN Bridge. Therefore, a Bridge of this architecture can only comprise S-VLAN components, C-VLAN components, or MAC Bridge components. Since there's no TPMR component, we don't need to relay PDUs using the destination addresses specified on the Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge section where they must be relayed by TPMR components. One option to trap link-local frames to CPU port is to add static FDB entries with CPU port designated as destination port. However, because that Independent VLAN Learning (IVL) is being used on every VID, each entry only applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC Bridge component or a C-VLAN component, there would have to be 16 times 4096 entries. This switch intellectual property can only hold a maximum of 2048 entries. Using this option, there also isn't a mechanism to prevent link-local frames from being discarded when the spanning tree Port State of the reception Port is discarding. The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4 registers. Whilst this applies to every VID, it doesn't contain all of the reserved MAC addresses without affecting the remaining Standard Group MAC Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF destination addresses which may be relayed by MAC Bridges or VLAN Bridges. The latter option provides better but not complete conformance. This switch intellectual property also does not provide a mechanism to trap link-local frames with specific destination addresses to CPU port by Bridge, to conform to the filtering rules for the distinct Bridge components. Therefore, regardless of the type of the Bridge component, link-local frames with these destination addresses will be trapped to CPU port: 01-80-C2-00-00-[00,01,02,03,0E] In a Bridge comprising a MAC Bridge component or a C-VLAN component: Link-local frames with these destination addresses won't be trapped to CPU port which won't conform to IEEE Std 802.1Q-2022: 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] In a Bridge comprising an S-VLAN component: Link-local frames with these destination addresses will be trapped to CPU port which won't conform to IEEE Std 802.1Q-2022: 01-80-C2-00-00-00 Link-local frames with these destination addresses won't be trapped to CPU port which won't conform to IEEE Std 802.1Q-2022: 01-80-C2-00-00-[04,05,06,07,08,09,0A] Currently on this switch intellectual property, if the spanning tree Port State of the reception Port is discarding, link-local frames will be discarded. To trap link-local frames regardless of the spanning tree Port State, make the switch regard them as Bridge Protocol Data Units (BPDUs). This switch intellectual property only lets the frames regarded as BPDUs bypass the spanning tree Port State function of the Forwarding Process. With this change, the only remaining interference is the ingress rules. When the reception Port has no PVID assigned on software, VLAN-untagged frames won't be allowed in. There doesn't seem to be a mechanism on the switch intellectual property to have link-local frames bypass this function of the Forwarding Process. Fixes: b8f126a ("net-next: dsa: add dsa support for Mediatek MT7530 switch") Reviewed-by: Daniel Golle <[email protected]> Signed-off-by: Arınç ÜNAL <[email protected]> Link: https://lore.kernel.org/r/20240409-b4-for-net-mt7530-fix-link-local-when-stp-discarding-v2-1-07b1150164ac@arinc9.com Signed-off-by: Paolo Abeni <[email protected]>
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‎drivers/net/dsa/mt7530.c

Lines changed: 195 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -950,56 +950,217 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
950950
mutex_unlock(&priv->reg_mutex);
951951
}
952952

953-
/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
954-
* 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
955-
* must only be propagated to C-VLAN and MAC Bridge components. That means
956-
* VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
957-
* these frames are supposed to be processed by the CPU (software). So we make
958-
* the switch only forward them to the CPU port. And if received from a CPU
959-
* port, forward to a single port. The software is responsible of making the
960-
* switch conform to the latter by setting a single port as destination port on
961-
* the special tag.
953+
/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
954+
* of the Open Systems Interconnection basic reference model (OSI/RM) are
955+
* described; the medium access control (MAC) and logical link control (LLC)
956+
* sublayers. The MAC sublayer is the one facing the physical layer.
962957
*
963-
* This switch intellectual property cannot conform to this part of the standard
964-
* fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
965-
* DAs, it also includes :22-FF which the scope of propagation is not supposed
966-
* to be restricted for these MAC DAs.
958+
* In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
959+
* Bridge component comprises a MAC Relay Entity for interconnecting the Ports
960+
* of the Bridge, at least two Ports, and higher layer entities with at least a
961+
* Spanning Tree Protocol Entity included.
962+
*
963+
* Each Bridge Port also functions as an end station and shall provide the MAC
964+
* Service to an LLC Entity. Each instance of the MAC Service is provided to a
965+
* distinct LLC Entity that supports protocol identification, multiplexing, and
966+
* demultiplexing, for protocol data unit (PDU) transmission and reception by
967+
* one or more higher layer entities.
968+
*
969+
* It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
970+
* Entity associated with each Bridge Port is modeled as being directly
971+
* connected to the attached Local Area Network (LAN).
972+
*
973+
* On the switch with CPU port architecture, CPU port functions as Management
974+
* Port, and the Management Port functionality is provided by software which
975+
* functions as an end station. Software is connected to an IEEE 802 LAN that is
976+
* wholly contained within the system that incorporates the Bridge. Software
977+
* provides access to the LLC Entity associated with each Bridge Port by the
978+
* value of the source port field on the special tag on the frame received by
979+
* software.
980+
*
981+
* We call frames that carry control information to determine the active
982+
* topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
983+
* spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
984+
* Protocol Data Units (MVRPDUs), and frames from other link constrained
985+
* protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
986+
* Link Layer Discovery Protocol (LLDP), link-local frames. They are not
987+
* forwarded by a Bridge. Permanently configured entries in the filtering
988+
* database (FDB) ensure that such frames are discarded by the Forwarding
989+
* Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
990+
*
991+
* Each of the reserved MAC addresses specified in Table 8-1
992+
* (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
993+
* permanently configured in the FDB in C-VLAN components and ERs.
994+
*
995+
* Each of the reserved MAC addresses specified in Table 8-2
996+
* (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
997+
* configured in the FDB in S-VLAN components.
998+
*
999+
* Each of the reserved MAC addresses specified in Table 8-3
1000+
* (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
1001+
* TPMR components.
1002+
*
1003+
* The FDB entries for reserved MAC addresses shall specify filtering for all
1004+
* Bridge Ports and all VIDs. Management shall not provide the capability to
1005+
* modify or remove entries for reserved MAC addresses.
1006+
*
1007+
* The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
1008+
* propagation of PDUs within a Bridged Network, as follows:
1009+
*
1010+
* The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
1011+
* conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
1012+
* component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
1013+
* PDUs transmitted using this destination address, or any other addresses
1014+
* that appear in Table 8-1, Table 8-2, and Table 8-3
1015+
* (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
1016+
* therefore travel no further than those stations that can be reached via a
1017+
* single individual LAN from the originating station.
1018+
*
1019+
* The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
1020+
* address that no conformant S-VLAN component, C-VLAN component, or MAC
1021+
* Bridge can forward; however, this address is relayed by a TPMR component.
1022+
* PDUs using this destination address, or any of the other addresses that
1023+
* appear in both Table 8-1 and Table 8-2 but not in Table 8-3
1024+
* (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
1025+
* any TPMRs but will propagate no further than the nearest S-VLAN component,
1026+
* C-VLAN component, or MAC Bridge.
1027+
*
1028+
* The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
1029+
* that no conformant C-VLAN component, MAC Bridge can forward; however, it is
1030+
* relayed by TPMR components and S-VLAN components. PDUs using this
1031+
* destination address, or any of the other addresses that appear in Table 8-1
1032+
* but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
1033+
* will be relayed by TPMR components and S-VLAN components but will propagate
1034+
* no further than the nearest C-VLAN component or MAC Bridge.
1035+
*
1036+
* Because the LLC Entity associated with each Bridge Port is provided via CPU
1037+
* port, we must not filter these frames but forward them to CPU port.
1038+
*
1039+
* In a Bridge, the transmission Port is majorly decided by ingress and egress
1040+
* rules, FDB, and spanning tree Port State functions of the Forwarding Process.
1041+
* For link-local frames, only CPU port should be designated as destination port
1042+
* in the FDB, and the other functions of the Forwarding Process must not
1043+
* interfere with the decision of the transmission Port. We call this process
1044+
* trapping frames to CPU port.
1045+
*
1046+
* Therefore, on the switch with CPU port architecture, link-local frames must
1047+
* be trapped to CPU port, and certain link-local frames received by a Port of a
1048+
* Bridge comprising a TPMR component or an S-VLAN component must be excluded
1049+
* from it.
1050+
*
1051+
* A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
1052+
* MAC Relay (TPMR) component as a TPMR component supports only a subset of the
1053+
* functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
1054+
* doesn't count) of this architecture will either function as a standard MAC
1055+
* Bridge or a standard VLAN Bridge.
1056+
*
1057+
* Therefore, a Bridge of this architecture can only comprise S-VLAN components,
1058+
* C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
1059+
* we don't need to relay PDUs using the destination addresses specified on the
1060+
* Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
1061+
* section where they must be relayed by TPMR components.
1062+
*
1063+
* One option to trap link-local frames to CPU port is to add static FDB entries
1064+
* with CPU port designated as destination port. However, because that
1065+
* Independent VLAN Learning (IVL) is being used on every VID, each entry only
1066+
* applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
1067+
* Bridge component or a C-VLAN component, there would have to be 16 times 4096
1068+
* entries. This switch intellectual property can only hold a maximum of 2048
1069+
* entries. Using this option, there also isn't a mechanism to prevent
1070+
* link-local frames from being discarded when the spanning tree Port State of
1071+
* the reception Port is discarding.
1072+
*
1073+
* The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
1074+
* registers. Whilst this applies to every VID, it doesn't contain all of the
1075+
* reserved MAC addresses without affecting the remaining Standard Group MAC
1076+
* Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
1077+
* remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
1078+
* addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
1079+
* destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
1080+
* The latter option provides better but not complete conformance.
1081+
*
1082+
* This switch intellectual property also does not provide a mechanism to trap
1083+
* link-local frames with specific destination addresses to CPU port by Bridge,
1084+
* to conform to the filtering rules for the distinct Bridge components.
1085+
*
1086+
* Therefore, regardless of the type of the Bridge component, link-local frames
1087+
* with these destination addresses will be trapped to CPU port:
1088+
*
1089+
* 01-80-C2-00-00-[00,01,02,03,0E]
1090+
*
1091+
* In a Bridge comprising a MAC Bridge component or a C-VLAN component:
1092+
*
1093+
* Link-local frames with these destination addresses won't be trapped to CPU
1094+
* port which won't conform to IEEE Std 802.1Q-2022:
1095+
*
1096+
* 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
1097+
*
1098+
* In a Bridge comprising an S-VLAN component:
1099+
*
1100+
* Link-local frames with these destination addresses will be trapped to CPU
1101+
* port which won't conform to IEEE Std 802.1Q-2022:
1102+
*
1103+
* 01-80-C2-00-00-00
1104+
*
1105+
* Link-local frames with these destination addresses won't be trapped to CPU
1106+
* port which won't conform to IEEE Std 802.1Q-2022:
1107+
*
1108+
* 01-80-C2-00-00-[04,05,06,07,08,09,0A]
1109+
*
1110+
* To trap link-local frames to CPU port as conformant as this switch
1111+
* intellectual property can allow, link-local frames are made to be regarded as
1112+
* Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
1113+
* property only lets the frames regarded as BPDUs bypass the spanning tree Port
1114+
* State function of the Forwarding Process.
1115+
*
1116+
* The only remaining interference is the ingress rules. When the reception Port
1117+
* has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
1118+
* There doesn't seem to be a mechanism on the switch intellectual property to
1119+
* have link-local frames bypass this function of the Forwarding Process.
9671120
*/
9681121
static void
9691122
mt753x_trap_frames(struct mt7530_priv *priv)
9701123
{
9711124
/* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them
9721125
* VLAN-untagged.
9731126
*/
974-
mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK |
975-
MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
976-
MT753X_BPDU_PORT_FW_MASK,
977-
MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
978-
MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
979-
MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
980-
MT753X_BPDU_CPU_ONLY);
1127+
mt7530_rmw(priv, MT753X_BPC,
1128+
MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
1129+
MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
1130+
MT753X_BPDU_PORT_FW_MASK,
1131+
MT753X_PAE_BPDU_FR |
1132+
MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1133+
MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
1134+
MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1135+
MT753X_BPDU_CPU_ONLY);
9811136

9821137
/* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
9831138
* them VLAN-untagged.
9841139
*/
985-
mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |
986-
MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
987-
MT753X_R01_PORT_FW_MASK,
988-
MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
989-
MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
990-
MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
991-
MT753X_BPDU_CPU_ONLY);
1140+
mt7530_rmw(priv, MT753X_RGAC1,
1141+
MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
1142+
MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
1143+
MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
1144+
MT753X_R02_BPDU_FR |
1145+
MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1146+
MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
1147+
MT753X_R01_BPDU_FR |
1148+
MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1149+
MT753X_BPDU_CPU_ONLY);
9921150

9931151
/* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
9941152
* them VLAN-untagged.
9951153
*/
996-
mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |
997-
MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
998-
MT753X_R03_PORT_FW_MASK,
999-
MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1000-
MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
1001-
MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1002-
MT753X_BPDU_CPU_ONLY);
1154+
mt7530_rmw(priv, MT753X_RGAC2,
1155+
MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
1156+
MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
1157+
MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
1158+
MT753X_R0E_BPDU_FR |
1159+
MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1160+
MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
1161+
MT753X_R03_BPDU_FR |
1162+
MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
1163+
MT753X_BPDU_CPU_ONLY);
10031164
}
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10051166
static void

‎drivers/net/dsa/mt7530.h

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@@ -65,6 +65,7 @@ enum mt753x_id {
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/* Registers for BPDU and PAE frame control*/
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#define MT753X_BPC 0x24
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#define MT753X_PAE_BPDU_FR BIT(25)
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#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
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#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
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#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
@@ -75,20 +76,24 @@ enum mt753x_id {
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/* Register for :01 and :02 MAC DA frame control */
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#define MT753X_RGAC1 0x28
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#define MT753X_R02_BPDU_FR BIT(25)
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#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
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#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
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#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
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#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
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#define MT753X_R01_BPDU_FR BIT(9)
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#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
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#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
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#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
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/* Register for :03 and :0E MAC DA frame control */
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#define MT753X_RGAC2 0x2c
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#define MT753X_R0E_BPDU_FR BIT(25)
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#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
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#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
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#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
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#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
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#define MT753X_R03_BPDU_FR BIT(9)
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#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
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#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
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#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)

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