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| 1 | +/* |
| 2 | + * Clock Driver for Allo DAC |
| 3 | + * |
| 4 | + * Author: Baswaraj K <[email protected]> |
| 5 | + * Copyright 2016 |
| 6 | + * based on code by Stuart MacLean |
| 7 | + * |
| 8 | + * This program is free software; you can redistribute it and/or |
| 9 | + * modify it under the terms of the GNU General Public License |
| 10 | + * version 2 as published by the Free Software Foundation. |
| 11 | + * |
| 12 | + * This program is distributed in the hope that it will be useful, but |
| 13 | + * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | + * General Public License for more details. |
| 16 | + */ |
| 17 | + |
| 18 | +#include <linux/clk-provider.h> |
| 19 | +#include <linux/clkdev.h> |
| 20 | +#include <linux/kernel.h> |
| 21 | +#include <linux/module.h> |
| 22 | +#include <linux/of.h> |
| 23 | +#include <linux/slab.h> |
| 24 | +#include <linux/platform_device.h> |
| 25 | + |
| 26 | +/* Clock rate of CLK44EN attached to GPIO6 pin */ |
| 27 | +#define CLK_44EN_RATE 45158400UL |
| 28 | +/* Clock rate of CLK48EN attached to GPIO3 pin */ |
| 29 | +#define CLK_48EN_RATE 49152000UL |
| 30 | + |
| 31 | +/** |
| 32 | + * struct allo_dac_clk - Common struct to the Allo DAC |
| 33 | + * @hw: clk_hw for the common clk framework |
| 34 | + * @mode: 0 => CLK44EN, 1 => CLK48EN |
| 35 | + */ |
| 36 | +struct clk_allo_hw { |
| 37 | + struct clk_hw hw; |
| 38 | + uint8_t mode; |
| 39 | +}; |
| 40 | + |
| 41 | +#define to_allo_clk(_hw) container_of(_hw, struct clk_allo_hw, hw) |
| 42 | + |
| 43 | +static const struct of_device_id clk_allo_dac_dt_ids[] = { |
| 44 | + { .compatible = "allo,dac-clk",}, |
| 45 | + { } |
| 46 | +}; |
| 47 | +MODULE_DEVICE_TABLE(of, clk_allo_dac_dt_ids); |
| 48 | + |
| 49 | +static unsigned long clk_allo_dac_recalc_rate(struct clk_hw *hw, |
| 50 | + unsigned long parent_rate) |
| 51 | +{ |
| 52 | + return (to_allo_clk(hw)->mode == 0) ? CLK_44EN_RATE : |
| 53 | + CLK_48EN_RATE; |
| 54 | +} |
| 55 | + |
| 56 | +static long clk_allo_dac_round_rate(struct clk_hw *hw, |
| 57 | + unsigned long rate, unsigned long *parent_rate) |
| 58 | +{ |
| 59 | + long actual_rate; |
| 60 | + |
| 61 | + if (rate <= CLK_44EN_RATE) { |
| 62 | + actual_rate = (long)CLK_44EN_RATE; |
| 63 | + } else if (rate >= CLK_48EN_RATE) { |
| 64 | + actual_rate = (long)CLK_48EN_RATE; |
| 65 | + } else { |
| 66 | + long diff44Rate = (long)(rate - CLK_44EN_RATE); |
| 67 | + long diff48Rate = (long)(CLK_48EN_RATE - rate); |
| 68 | + |
| 69 | + if (diff44Rate < diff48Rate) |
| 70 | + actual_rate = (long)CLK_44EN_RATE; |
| 71 | + else |
| 72 | + actual_rate = (long)CLK_48EN_RATE; |
| 73 | + } |
| 74 | + return actual_rate; |
| 75 | +} |
| 76 | + |
| 77 | + |
| 78 | +static int clk_allo_dac_set_rate(struct clk_hw *hw, |
| 79 | + unsigned long rate, unsigned long parent_rate) |
| 80 | +{ |
| 81 | + unsigned long actual_rate; |
| 82 | + struct clk_allo_hw *clk = to_allo_clk(hw); |
| 83 | + |
| 84 | + actual_rate = (unsigned long)clk_allo_dac_round_rate(hw, rate, |
| 85 | + &parent_rate); |
| 86 | + clk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1; |
| 87 | + return 0; |
| 88 | +} |
| 89 | + |
| 90 | + |
| 91 | +const struct clk_ops clk_allo_dac_rate_ops = { |
| 92 | + .recalc_rate = clk_allo_dac_recalc_rate, |
| 93 | + .round_rate = clk_allo_dac_round_rate, |
| 94 | + .set_rate = clk_allo_dac_set_rate, |
| 95 | +}; |
| 96 | + |
| 97 | +static int clk_allo_dac_probe(struct platform_device *pdev) |
| 98 | +{ |
| 99 | + int ret; |
| 100 | + struct clk_allo_hw *proclk; |
| 101 | + struct clk *clk; |
| 102 | + struct device *dev; |
| 103 | + struct clk_init_data init; |
| 104 | + |
| 105 | + dev = &pdev->dev; |
| 106 | + |
| 107 | + proclk = kzalloc(sizeof(struct clk_allo_hw), GFP_KERNEL); |
| 108 | + if (!proclk) |
| 109 | + return -ENOMEM; |
| 110 | + |
| 111 | + init.name = "clk-allo-dac"; |
| 112 | + init.ops = &clk_allo_dac_rate_ops; |
| 113 | + init.flags = 0; |
| 114 | + init.parent_names = NULL; |
| 115 | + init.num_parents = 0; |
| 116 | + |
| 117 | + proclk->mode = 0; |
| 118 | + proclk->hw.init = &init; |
| 119 | + |
| 120 | + clk = devm_clk_register(dev, &proclk->hw); |
| 121 | + if (!IS_ERR(clk)) { |
| 122 | + ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, |
| 123 | + clk); |
| 124 | + } else { |
| 125 | + dev_err(dev, "Fail to register clock driver\n"); |
| 126 | + kfree(proclk); |
| 127 | + ret = PTR_ERR(clk); |
| 128 | + } |
| 129 | + return ret; |
| 130 | +} |
| 131 | + |
| 132 | +static int clk_allo_dac_remove(struct platform_device *pdev) |
| 133 | +{ |
| 134 | + of_clk_del_provider(pdev->dev.of_node); |
| 135 | + return 0; |
| 136 | +} |
| 137 | + |
| 138 | +static struct platform_driver clk_allo_dac_driver = { |
| 139 | + .probe = clk_allo_dac_probe, |
| 140 | + .remove = clk_allo_dac_remove, |
| 141 | + .driver = { |
| 142 | + .name = "clk-allo-dac", |
| 143 | + .of_match_table = clk_allo_dac_dt_ids, |
| 144 | + }, |
| 145 | +}; |
| 146 | + |
| 147 | +static int __init clk_allo_dac_init(void) |
| 148 | +{ |
| 149 | + return platform_driver_register(&clk_allo_dac_driver); |
| 150 | +} |
| 151 | +core_initcall(clk_allo_dac_init); |
| 152 | + |
| 153 | +static void __exit clk_allo_dac_exit(void) |
| 154 | +{ |
| 155 | + platform_driver_unregister(&clk_allo_dac_driver); |
| 156 | +} |
| 157 | +module_exit(clk_allo_dac_exit); |
| 158 | + |
| 159 | +MODULE_DESCRIPTION("Allo DAC clock driver"); |
| 160 | +MODULE_LICENSE("GPL v2"); |
| 161 | +MODULE_ALIAS("platform:clk-allo-dac"); |
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