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clk-bcm2835: Disable v3d clock
This is controlled by firmware, see clk-raspberrypi.c Signed-off-by: popcornmix <[email protected]>
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-18
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+12
-18
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drivers/clk/bcm/clk-bcm2835.c

Lines changed: 12 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1741,16 +1741,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.hold_mask = CM_PLLA_HOLDCORE,
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.fixed_divider = 1,
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.flags = CLK_SET_RATE_PARENT),
1744-
[BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
1745-
SOC_ALL,
1746-
.name = "plla_per",
1747-
.source_pll = "plla",
1748-
.cm_reg = CM_PLLA,
1749-
.a2w_reg = A2W_PLLA_PER,
1750-
.load_mask = CM_PLLA_LOADPER,
1751-
.hold_mask = CM_PLLA_HOLDPER,
1752-
.fixed_divider = 1,
1753-
.flags = CLK_SET_RATE_PARENT),
1744+
1745+
/*
1746+
* PLLA_PER is used for gpu clocks. Controlled by firmware, see
1747+
* clk-raspberrypi.c.
1748+
*/
1749+
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[BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
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SOC_ALL,
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.name = "plla_dsi0",
@@ -2051,14 +2047,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
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.int_bits = 6,
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.frac_bits = 0,
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.tcnt_mux = 3),
2054-
[BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
2055-
SOC_ALL,
2056-
.name = "v3d",
2057-
.ctl_reg = CM_V3DCTL,
2058-
.div_reg = CM_V3DDIV,
2059-
.int_bits = 4,
2060-
.frac_bits = 8,
2061-
.tcnt_mux = 4),
2050+
2051+
/*
2052+
* CLOCK_V3D is used for v3d clock. Controlled by firmware, see
2053+
* clk-raspberrypi.c.
2054+
*/
2055+
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/*
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* VPU clock. This doesn't have an enable bit, since it drives
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* the bus for everything else, and is special so it doesn't need

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