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mripardpelwell
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drm/vc4: hdmi: Convert to the new clock request API
The new clock request API allows us to increase the rate of the HSM clock to match our pixel rate requirements while decreasing it when we're done, resulting in a better power-efficiency. Signed-off-by: Maxime Ripard <[email protected]>
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-7
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+15
-7
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drivers/gpu/drm/vc4/vc4_hdmi.c

Lines changed: 12 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -852,7 +852,9 @@ static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
852852
HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
853853

854854
clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
855+
clk_request_done(vc4_hdmi->bvb_req);
855856
clk_disable_unprepare(vc4_hdmi->hsm_clock);
857+
clk_request_done(vc4_hdmi->hsm_req);
856858
clk_disable_unprepare(vc4_hdmi->pixel_clock);
857859

858860
ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
@@ -1157,9 +1159,9 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
11571159
* pixel clock, but HSM ends up being the limiting factor.
11581160
*/
11591161
hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1160-
ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1161-
if (ret) {
1162-
DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1162+
vc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate);
1163+
if (IS_ERR(vc4_hdmi->hsm_req)) {
1164+
DRM_ERROR("Failed to set HSM clock rate: %ld\n", PTR_ERR(vc4_hdmi->hsm_req));
11631165
return;
11641166
}
11651167

@@ -1176,10 +1178,11 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
11761178
* FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
11771179
* at 300MHz.
11781180
*/
1179-
ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
1180-
(hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
1181-
if (ret) {
1182-
DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1181+
vc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock,
1182+
(hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
1183+
if (IS_ERR(vc4_hdmi->bvb_req)) {
1184+
DRM_ERROR("Failed to set pixel bvb clock rate: %ld\n", PTR_ERR(vc4_hdmi->bvb_req));
1185+
clk_request_done(vc4_hdmi->hsm_req);
11831186
clk_disable_unprepare(vc4_hdmi->hsm_clock);
11841187
clk_disable_unprepare(vc4_hdmi->pixel_clock);
11851188
return;
@@ -1188,6 +1191,8 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
11881191
ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
11891192
if (ret) {
11901193
DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1194+
clk_request_done(vc4_hdmi->bvb_req);
1195+
clk_request_done(vc4_hdmi->hsm_req);
11911196
clk_disable_unprepare(vc4_hdmi->hsm_clock);
11921197
clk_disable_unprepare(vc4_hdmi->pixel_clock);
11931198
return;

drivers/gpu/drm/vc4/vc4_hdmi.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -175,6 +175,9 @@ struct vc4_hdmi {
175175

176176
struct reset_control *reset;
177177

178+
struct clk_request *bvb_req;
179+
struct clk_request *hsm_req;
180+
178181
/* Common debugfs regset */
179182
struct debugfs_regset32 hdmi_regset;
180183
struct debugfs_regset32 hd_regset;

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