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mripardpopcornmix
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drm/vc4: hdmi: Convert to the new clock request API
The new clock request API allows us to increase the rate of the HSM clock to match our pixel rate requirements while decreasing it when we're done, resulting in a better power-efficiency. Signed-off-by: Maxime Ripard <[email protected]>
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+18
-7
lines changed

2 files changed

+18
-7
lines changed

drivers/gpu/drm/vc4/vc4_hdmi.c

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -965,6 +965,9 @@ static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
965965
HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
966966

967967
clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
968+
clk_request_done(vc4_hdmi->bvb_req);
969+
clk_disable_unprepare(vc4_hdmi->hsm_clock);
970+
clk_request_done(vc4_hdmi->hsm_req);
968971
clk_disable_unprepare(vc4_hdmi->pixel_clock);
969972

970973
ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
@@ -1269,9 +1272,9 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
12691272
* pixel clock, but HSM ends up being the limiting factor.
12701273
*/
12711274
hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
1272-
ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1273-
if (ret) {
1274-
DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1275+
vc4_hdmi->hsm_req = clk_request_start(vc4_hdmi->hsm_clock, hsm_rate);
1276+
if (IS_ERR(vc4_hdmi->hsm_req)) {
1277+
DRM_ERROR("Failed to set HSM clock rate: %ld\n", PTR_ERR(vc4_hdmi->hsm_req));
12751278
return;
12761279
}
12771280

@@ -1281,17 +1284,22 @@ static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
12811284
* FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
12821285
* at 300MHz.
12831286
*/
1284-
ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
1285-
(hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
1286-
if (ret) {
1287-
DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1287+
vc4_hdmi->bvb_req = clk_request_start(vc4_hdmi->pixel_bvb_clock,
1288+
(hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
1289+
if (IS_ERR(vc4_hdmi->bvb_req)) {
1290+
DRM_ERROR("Failed to set pixel bvb clock rate: %ld\n", PTR_ERR(vc4_hdmi->bvb_req));
1291+
clk_request_done(vc4_hdmi->hsm_req);
1292+
clk_disable_unprepare(vc4_hdmi->hsm_clock);
12881293
clk_disable_unprepare(vc4_hdmi->pixel_clock);
12891294
return;
12901295
}
12911296

12921297
ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
12931298
if (ret) {
12941299
DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1300+
clk_request_done(vc4_hdmi->bvb_req);
1301+
clk_request_done(vc4_hdmi->hsm_req);
1302+
clk_disable_unprepare(vc4_hdmi->hsm_clock);
12951303
clk_disable_unprepare(vc4_hdmi->pixel_clock);
12961304
return;
12971305
}

drivers/gpu/drm/vc4/vc4_hdmi.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -185,6 +185,9 @@ struct vc4_hdmi {
185185

186186
struct reset_control *reset;
187187

188+
struct clk_request *bvb_req;
189+
struct clk_request *hsm_req;
190+
188191
/* Common debugfs regset */
189192
struct debugfs_regset32 hdmi_regset;
190193
struct debugfs_regset32 hd_regset;

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