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Merge tag 'drm-intel-fixes-2018-01-04' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
drm/i915 fixes for v4.15-rc7 - couple of documentation build fixes - serialize non-blocking modesets - prevent DMC from messing up GMBUS transfers - PSR regression fix * tag 'drm-intel-fixes-2018-01-04' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915: Apply Display WA #1183 on skl, kbl, and cfl docs: fix, intel_guc_loader.c has been moved to intel_guc_fw.c documentation/gpu/i915: fix docs build error after file rename drm/i915: Put all non-blocking modesets onto an ordered wq drm/i915: Disable DC states around GMBUS on GLK drm/i915/psr: Fix register name mess up.
2 parents 0007b9c + 30414f3 commit bc6fe53

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‎Documentation/gpu/i915.rst

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -341,10 +341,7 @@ GuC
341341
GuC-specific firmware loader
342342
----------------------------
343343

344-
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c
345-
:doc: GuC-specific firmware loader
346-
347-
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_loader.c
344+
.. kernel-doc:: drivers/gpu/drm/i915/intel_guc_fw.c
348345
:internal:
349346

350347
GuC-based command submission

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2368,6 +2368,9 @@ struct drm_i915_private {
23682368
*/
23692369
struct workqueue_struct *wq;
23702370

2371+
/* ordered wq for modesets */
2372+
struct workqueue_struct *modeset_wq;
2373+
23712374
/* Display functions */
23722375
struct drm_i915_display_funcs display;
23732376

‎drivers/gpu/drm/i915/i915_reg.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6977,6 +6977,7 @@ enum {
69776977
#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
69786978

69796979
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
6980+
#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
69806981
#define MASK_WAKEMEM (1<<13)
69816982

69826983
#define SKL_DFSM _MMIO(0x51000)
@@ -8522,6 +8523,7 @@ enum skl_power_gate {
85228523
#define BXT_CDCLK_CD2X_DIV_SEL_2 (2<<22)
85238524
#define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22)
85248525
#define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20)
8526+
#define CDCLK_DIVMUX_CD_OVERRIDE (1<<19)
85258527
#define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3)
85268528
#define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16)
85278529
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)

‎drivers/gpu/drm/i915/intel_cdclk.c

Lines changed: 26 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -860,16 +860,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
860860

861861
static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
862862
{
863-
int min_cdclk = skl_calc_cdclk(0, vco);
864863
u32 val;
865864

866865
WARN_ON(vco != 8100000 && vco != 8640000);
867866

868-
/* select the minimum CDCLK before enabling DPLL 0 */
869-
val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
870-
I915_WRITE(CDCLK_CTL, val);
871-
POSTING_READ(CDCLK_CTL);
872-
873867
/*
874868
* We always enable DPLL0 with the lowest link rate possible, but still
875869
* taking into account the VCO required to operate the eDP panel at the
@@ -923,7 +917,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
923917
{
924918
int cdclk = cdclk_state->cdclk;
925919
int vco = cdclk_state->vco;
926-
u32 freq_select, pcu_ack;
920+
u32 freq_select, pcu_ack, cdclk_ctl;
927921
int ret;
928922

929923
WARN_ON((cdclk == 24000) != (vco == 0));
@@ -940,7 +934,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
940934
return;
941935
}
942936

943-
/* set CDCLK_CTL */
937+
/* Choose frequency for this cdclk */
944938
switch (cdclk) {
945939
case 450000:
946940
case 432000:
@@ -968,10 +962,33 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
968962
dev_priv->cdclk.hw.vco != vco)
969963
skl_dpll0_disable(dev_priv);
970964

965+
cdclk_ctl = I915_READ(CDCLK_CTL);
966+
967+
if (dev_priv->cdclk.hw.vco != vco) {
968+
/* Wa Display #1183: skl,kbl,cfl */
969+
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
970+
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
971+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
972+
}
973+
974+
/* Wa Display #1183: skl,kbl,cfl */
975+
cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
976+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
977+
POSTING_READ(CDCLK_CTL);
978+
971979
if (dev_priv->cdclk.hw.vco != vco)
972980
skl_dpll0_enable(dev_priv, vco);
973981

974-
I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
982+
/* Wa Display #1183: skl,kbl,cfl */
983+
cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
984+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
985+
986+
cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
987+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
988+
989+
/* Wa Display #1183: skl,kbl,cfl */
990+
cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
991+
I915_WRITE(CDCLK_CTL, cdclk_ctl);
975992
POSTING_READ(CDCLK_CTL);
976993

977994
/* inform PCU of the change */

‎drivers/gpu/drm/i915/intel_display.c

Lines changed: 11 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12544,11 +12544,15 @@ static int intel_atomic_commit(struct drm_device *dev,
1254412544
INIT_WORK(&state->commit_work, intel_atomic_commit_work);
1254512545

1254612546
i915_sw_fence_commit(&intel_state->commit_ready);
12547-
if (nonblock)
12547+
if (nonblock && intel_state->modeset) {
12548+
queue_work(dev_priv->modeset_wq, &state->commit_work);
12549+
} else if (nonblock) {
1254812550
queue_work(system_unbound_wq, &state->commit_work);
12549-
else
12551+
} else {
12552+
if (intel_state->modeset)
12553+
flush_workqueue(dev_priv->modeset_wq);
1255012554
intel_atomic_commit_tail(state);
12551-
12555+
}
1255212556

1255312557
return 0;
1255412558
}
@@ -14462,6 +14466,8 @@ int intel_modeset_init(struct drm_device *dev)
1446214466
enum pipe pipe;
1446314467
struct intel_crtc *crtc;
1446414468

14469+
dev_priv->modeset_wq = alloc_ordered_workqueue("i915_modeset", 0);
14470+
1446514471
drm_mode_config_init(dev);
1446614472

1446714473
dev->mode_config.min_width = 0;
@@ -15270,6 +15276,8 @@ void intel_modeset_cleanup(struct drm_device *dev)
1527015276
intel_cleanup_gt_powersave(dev_priv);
1527115277

1527215278
intel_teardown_gmbus(dev_priv);
15279+
15280+
destroy_workqueue(dev_priv->modeset_wq);
1527315281
}
1527415282

1527515283
void intel_connector_attach_encoder(struct intel_connector *connector,

‎drivers/gpu/drm/i915/intel_psr.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -590,7 +590,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
590590
struct drm_i915_private *dev_priv = to_i915(dev);
591591

592592
if (dev_priv->psr.active) {
593-
i915_reg_t psr_ctl;
593+
i915_reg_t psr_status;
594594
u32 psr_status_mask;
595595

596596
if (dev_priv->psr.aux_frame_sync)
@@ -599,24 +599,24 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
599599
0);
600600

601601
if (dev_priv->psr.psr2_support) {
602-
psr_ctl = EDP_PSR2_CTL;
602+
psr_status = EDP_PSR2_STATUS_CTL;
603603
psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
604604

605-
I915_WRITE(psr_ctl,
606-
I915_READ(psr_ctl) &
605+
I915_WRITE(EDP_PSR2_CTL,
606+
I915_READ(EDP_PSR2_CTL) &
607607
~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
608608

609609
} else {
610-
psr_ctl = EDP_PSR_STATUS_CTL;
610+
psr_status = EDP_PSR_STATUS_CTL;
611611
psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
612612

613-
I915_WRITE(psr_ctl,
614-
I915_READ(psr_ctl) & ~EDP_PSR_ENABLE);
613+
I915_WRITE(EDP_PSR_CTL,
614+
I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
615615
}
616616

617617
/* Wait till PSR is idle */
618618
if (intel_wait_for_register(dev_priv,
619-
psr_ctl, psr_status_mask, 0,
619+
psr_status, psr_status_mask, 0,
620620
2000))
621621
DRM_ERROR("Timed out waiting for PSR Idle State\n");
622622

‎drivers/gpu/drm/i915/intel_runtime_pm.c

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv)
598598

599599
DRM_DEBUG_KMS("Enabling DC5\n");
600600

601+
/* Wa Display #1183: skl,kbl,cfl */
602+
if (IS_GEN9_BC(dev_priv))
603+
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
604+
SKL_SELECT_ALTERNATE_DC_EXIT);
605+
601606
gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
602607
}
603608

@@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
625630
{
626631
DRM_DEBUG_KMS("Disabling DC6\n");
627632

633+
/* Wa Display #1183: skl,kbl,cfl */
634+
if (IS_GEN9_BC(dev_priv))
635+
I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
636+
SKL_SELECT_ALTERNATE_DC_EXIT);
637+
628638
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
629639
}
630640

@@ -1786,6 +1796,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
17861796
GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
17871797
BIT_ULL(POWER_DOMAIN_MODESET) | \
17881798
BIT_ULL(POWER_DOMAIN_AUX_A) | \
1799+
BIT_ULL(POWER_DOMAIN_GMBUS) | \
17891800
BIT_ULL(POWER_DOMAIN_INIT))
17901801

17911802
#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \

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