File tree Expand file tree Collapse file tree 5 files changed +15
-15
lines changed
arch/arm/boot/dts/overlays Expand file tree Collapse file tree 5 files changed +15
-15
lines changed Original file line number Diff line number Diff line change 5
5
6
6
/*
7
7
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8
- * baudrate. The real clock is 100MHz , which we scale so that requesting
8
+ * baudrate. The real clock is 50MHz , which we scale so that requesting
9
9
* 38.4kHz results in an actual 31.25kHz.
10
10
*
11
- * 100000000 *38400/31250 = 122880000
11
+ * 50000000 *38400/31250 = 61440000
12
12
*/
13
13
14
14
/{
21
21
compatible = "fixed-clock";
22
22
#clock-cells = <0>;
23
23
clock-output-names = "uart0_pclk";
24
- clock-frequency = <122880000 >;
24
+ clock-frequency = <61440000 >;
25
25
};
26
26
};
27
27
};
Original file line number Diff line number Diff line change 5
5
6
6
/*
7
7
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8
- * baudrate. The real clock is 100MHz , which we scale so that requesting
8
+ * baudrate. The real clock is 50MHz , which we scale so that requesting
9
9
* 38.4kHz results in an actual 31.25kHz.
10
10
*
11
- * 100000000 *38400/31250 = 122880000
11
+ * 50000000 *38400/31250 = 61440000
12
12
*/
13
13
14
14
/{
21
21
compatible = "fixed-clock";
22
22
#clock-cells = <0>;
23
23
clock-output-names = "uart1_pclk";
24
- clock-frequency = <122880000 >;
24
+ clock-frequency = <61440000 >;
25
25
};
26
26
};
27
27
};
Original file line number Diff line number Diff line change 5
5
6
6
/*
7
7
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8
- * baudrate. The real clock is 100MHz , which we scale so that requesting
8
+ * baudrate. The real clock is 50MHz , which we scale so that requesting
9
9
* 38.4kHz results in an actual 31.25kHz.
10
10
*
11
- * 100000000 *38400/31250 = 122880000
11
+ * 50000000 *38400/31250 = 61440000
12
12
*/
13
13
14
14
/{
21
21
compatible = "fixed-clock";
22
22
#clock-cells = <0>;
23
23
clock-output-names = "uart2_pclk";
24
- clock-frequency = <122880000 >;
24
+ clock-frequency = <61440000 >;
25
25
};
26
26
};
27
27
};
Original file line number Diff line number Diff line change 5
5
6
6
/*
7
7
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8
- * baudrate. The real clock is 100MHz , which we scale so that requesting
8
+ * baudrate. The real clock is 50MHz , which we scale so that requesting
9
9
* 38.4kHz results in an actual 31.25kHz.
10
10
*
11
- * 100000000 *38400/31250 = 122880000
11
+ * 50000000 *38400/31250 = 61440000
12
12
*/
13
13
14
14
/{
21
21
compatible = "fixed-clock";
22
22
#clock-cells = <0>;
23
23
clock-output-names = "uart3_pclk";
24
- clock-frequency = <122880000 >;
24
+ clock-frequency = <61440000 >;
25
25
};
26
26
};
27
27
};
Original file line number Diff line number Diff line change 5
5
6
6
/*
7
7
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8
- * baudrate. The real clock is 100MHz , which we scale so that requesting
8
+ * baudrate. The real clock is 50MHz , which we scale so that requesting
9
9
* 38.4kHz results in an actual 31.25kHz.
10
10
*
11
- * 100000000 *38400/31250 = 122880000
11
+ * 50000000 *38400/31250 = 61440000
12
12
*/
13
13
14
14
/{
21
21
compatible = "fixed-clock";
22
22
#clock-cells = <0>;
23
23
clock-output-names = "uart4_pclk";
24
- clock-frequency = <122880000 >;
24
+ clock-frequency = <61440000 >;
25
25
};
26
26
};
27
27
};
You can’t perform that action at this time.
0 commit comments