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DTS: overlays: fix Pi 5 midi-over-UART
The UART source clock is 50MHz not 100MHz, so fix the fake-clock used to munge the baudrate. See https://forums.raspberrypi.com/viewtopic.php?p=2212755 Signed-off-by: Jonathan Bell <[email protected]>
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lines changed

5 files changed

+15
-15
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arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,10 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 100MHz, which we scale so that requesting
8+
* baudrate. The real clock is 50MHz, which we scale so that requesting
99
* 38.4kHz results in an actual 31.25kHz.
1010
*
11-
* 100000000*38400/31250 = 122880000
11+
* 50000000*38400/31250 = 61440000
1212
*/
1313

1414
/{
@@ -21,7 +21,7 @@
2121
compatible = "fixed-clock";
2222
#clock-cells = <0>;
2323
clock-output-names = "uart0_pclk";
24-
clock-frequency = <122880000>;
24+
clock-frequency = <61440000>;
2525
};
2626
};
2727
};

arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,10 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 100MHz, which we scale so that requesting
8+
* baudrate. The real clock is 50MHz, which we scale so that requesting
99
* 38.4kHz results in an actual 31.25kHz.
1010
*
11-
* 100000000*38400/31250 = 122880000
11+
* 50000000*38400/31250 = 61440000
1212
*/
1313

1414
/{
@@ -21,7 +21,7 @@
2121
compatible = "fixed-clock";
2222
#clock-cells = <0>;
2323
clock-output-names = "uart1_pclk";
24-
clock-frequency = <122880000>;
24+
clock-frequency = <61440000>;
2525
};
2626
};
2727
};

arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,10 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 100MHz, which we scale so that requesting
8+
* baudrate. The real clock is 50MHz, which we scale so that requesting
99
* 38.4kHz results in an actual 31.25kHz.
1010
*
11-
* 100000000*38400/31250 = 122880000
11+
* 50000000*38400/31250 = 61440000
1212
*/
1313

1414
/{
@@ -21,7 +21,7 @@
2121
compatible = "fixed-clock";
2222
#clock-cells = <0>;
2323
clock-output-names = "uart2_pclk";
24-
clock-frequency = <122880000>;
24+
clock-frequency = <61440000>;
2525
};
2626
};
2727
};

arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,10 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 100MHz, which we scale so that requesting
8+
* baudrate. The real clock is 50MHz, which we scale so that requesting
99
* 38.4kHz results in an actual 31.25kHz.
1010
*
11-
* 100000000*38400/31250 = 122880000
11+
* 50000000*38400/31250 = 61440000
1212
*/
1313

1414
/{
@@ -21,7 +21,7 @@
2121
compatible = "fixed-clock";
2222
#clock-cells = <0>;
2323
clock-output-names = "uart3_pclk";
24-
clock-frequency = <122880000>;
24+
clock-frequency = <61440000>;
2525
};
2626
};
2727
};

arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,10 @@
55

66
/*
77
* Fake a higher clock rate to get a larger divisor, and thereby a lower
8-
* baudrate. The real clock is 100MHz, which we scale so that requesting
8+
* baudrate. The real clock is 50MHz, which we scale so that requesting
99
* 38.4kHz results in an actual 31.25kHz.
1010
*
11-
* 100000000*38400/31250 = 122880000
11+
* 50000000*38400/31250 = 61440000
1212
*/
1313

1414
/{
@@ -21,7 +21,7 @@
2121
compatible = "fixed-clock";
2222
#clock-cells = <0>;
2323
clock-output-names = "uart4_pclk";
24-
clock-frequency = <122880000>;
24+
clock-frequency = <61440000>;
2525
};
2626
};
2727
};

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