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Sujith Manoharanlinvjw
Sujith Manoharan
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ath9k: Remove AR9462 v1.0 support
v1.0 chips are not available in the market. Signed-off-by: Sujith Manoharan <[email protected]> Signed-off-by: John W. Linville <[email protected]>
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7 files changed

+10
-1573
lines changed

7 files changed

+10
-1573
lines changed

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3603,10 +3603,6 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
36033603
u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
36043604

36053605
if (AR_SREV_9462(ah)) {
3606-
if (AR_SREV_9462_10(ah)) {
3607-
value &= ~AR_SWITCH_TABLE_COM_SPDT;
3608-
value |= 0x00100000;
3609-
}
36103606
REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
36113607
AR_SWITCH_TABLE_COM_AR9462_ALL, value);
36123608
} else

drivers/net/wireless/ath/ath9k/ar9003_hw.c

Lines changed: 3 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,6 @@
2222
#include "ar9330_1p1_initvals.h"
2323
#include "ar9330_1p2_initvals.h"
2424
#include "ar9580_1p0_initvals.h"
25-
#include "ar9462_1p0_initvals.h"
2625
#include "ar9462_2p0_initvals.h"
2726

2827
/* General hardware code for the AR9003 hadware family */
@@ -264,63 +263,6 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
264263
ar9485_1_1_pcie_phy_clkreq_disable_L1,
265264
ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
266265
2);
267-
} else if (AR_SREV_9462_10(ah)) {
268-
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
269-
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_1p0_mac_core,
270-
ARRAY_SIZE(ar9462_1p0_mac_core), 2);
271-
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
272-
ar9462_1p0_mac_postamble,
273-
ARRAY_SIZE(ar9462_1p0_mac_postamble),
274-
5);
275-
276-
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
277-
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
278-
ar9462_1p0_baseband_core,
279-
ARRAY_SIZE(ar9462_1p0_baseband_core),
280-
2);
281-
INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
282-
ar9462_1p0_baseband_postamble,
283-
ARRAY_SIZE(ar9462_1p0_baseband_postamble), 5);
284-
285-
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
286-
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
287-
ar9462_1p0_radio_core,
288-
ARRAY_SIZE(ar9462_1p0_radio_core), 2);
289-
INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
290-
ar9462_1p0_radio_postamble,
291-
ARRAY_SIZE(ar9462_1p0_radio_postamble), 5);
292-
293-
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
294-
ar9462_1p0_soc_preamble,
295-
ARRAY_SIZE(ar9462_1p0_soc_preamble), 2);
296-
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
297-
INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
298-
ar9462_1p0_soc_postamble,
299-
ARRAY_SIZE(ar9462_1p0_soc_postamble), 5);
300-
301-
INIT_INI_ARRAY(&ah->iniModesRxGain,
302-
ar9462_common_rx_gain_table_1p0,
303-
ARRAY_SIZE(ar9462_common_rx_gain_table_1p0), 2);
304-
305-
/* Awake -> Sleep Setting */
306-
INIT_INI_ARRAY(&ah->iniPcieSerdes,
307-
ar9462_pcie_phy_clkreq_disable_L1_1p0,
308-
ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
309-
2);
310-
311-
/* Sleep -> Awake Setting */
312-
INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
313-
ar9462_pcie_phy_clkreq_disable_L1_1p0,
314-
ARRAY_SIZE(ar9462_pcie_phy_clkreq_disable_L1_1p0),
315-
2);
316-
317-
INIT_INI_ARRAY(&ah->iniModesAdditional,
318-
ar9462_modes_fast_clock_1p0,
319-
ARRAY_SIZE(ar9462_modes_fast_clock_1p0), 3);
320-
INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
321-
AR9462_BB_CTX_COEFJ(1p0),
322-
ARRAY_SIZE(AR9462_BB_CTX_COEFJ(1p0)), 2);
323-
324266
} else if (AR_SREV_9462_20(ah)) {
325267

326268
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
@@ -537,11 +479,6 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
537479
ar9580_1p0_lowest_ob_db_tx_gain_table,
538480
ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
539481
5);
540-
else if (AR_SREV_9462_10(ah))
541-
INIT_INI_ARRAY(&ah->iniModesTxGain,
542-
ar9462_modes_low_ob_db_tx_gain_table_1p0,
543-
ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_1p0),
544-
5);
545482
else if (AR_SREV_9462_20(ah))
546483
INIT_INI_ARRAY(&ah->iniModesTxGain,
547484
ar9462_modes_low_ob_db_tx_gain_table_2p0,
@@ -581,11 +518,6 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
581518
ar9580_1p0_high_ob_db_tx_gain_table,
582519
ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
583520
5);
584-
else if (AR_SREV_9462_10(ah))
585-
INIT_INI_ARRAY(&ah->iniModesTxGain,
586-
ar9462_modes_high_ob_db_tx_gain_table_1p0,
587-
ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_1p0),
588-
5);
589521
else if (AR_SREV_9462_20(ah))
590522
INIT_INI_ARRAY(&ah->iniModesTxGain,
591523
ar9462_modes_high_ob_db_tx_gain_table_2p0,
@@ -712,11 +644,6 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
712644
ar9580_1p0_rx_gain_table,
713645
ARRAY_SIZE(ar9580_1p0_rx_gain_table),
714646
2);
715-
else if (AR_SREV_9462_10(ah))
716-
INIT_INI_ARRAY(&ah->iniModesRxGain,
717-
ar9462_common_rx_gain_table_1p0,
718-
ARRAY_SIZE(ar9462_common_rx_gain_table_1p0),
719-
2);
720647
else if (AR_SREV_9462_20(ah))
721648
INIT_INI_ARRAY(&ah->iniModesRxGain,
722649
ar9462_common_rx_gain_table_2p0,
@@ -751,11 +678,6 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
751678
ar9485Common_wo_xlna_rx_gain_1_1,
752679
ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
753680
2);
754-
else if (AR_SREV_9462_10(ah))
755-
INIT_INI_ARRAY(&ah->iniModesRxGain,
756-
ar9462_common_wo_xlna_rx_gain_table_1p0,
757-
ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_1p0),
758-
2);
759681
else if (AR_SREV_9462_20(ah))
760682
INIT_INI_ARRAY(&ah->iniModesRxGain,
761683
ar9462_common_wo_xlna_rx_gain_table_2p0,
@@ -775,14 +697,10 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
775697

776698
static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
777699
{
778-
if (AR_SREV_9462_10(ah))
779-
INIT_INI_ARRAY(&ah->iniModesRxGain,
780-
ar9462_common_mixed_rx_gain_table_1p0,
781-
ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_1p0), 2);
782-
else if (AR_SREV_9462_20(ah))
700+
if (AR_SREV_9462_20(ah))
783701
INIT_INI_ARRAY(&ah->iniModesRxGain,
784-
ar9462_common_mixed_rx_gain_table_2p0,
785-
ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
702+
ar9462_common_mixed_rx_gain_table_2p0,
703+
ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
786704
}
787705

788706
static void ar9003_rx_gain_table_apply(struct ath_hw *ah)

drivers/net/wireless/ath/ath9k/ar9003_mci.c

Lines changed: 4 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -274,14 +274,6 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah)
274274
ath_dbg(common, MCI, "MCI send REMOTE_RESET\n");
275275
ar9003_mci_remote_reset(ah, true);
276276

277-
/*
278-
* This delay is required for the reset delay worst case value 255 in
279-
* MCI_COMMAND2 register
280-
*/
281-
282-
if (AR_SREV_9462_10(ah))
283-
udelay(252);
284-
285277
ath_dbg(common, MCI, "MCI Send REQ_WAKE to remoter(BT)\n");
286278
ar9003_mci_send_req_wake(ah, true);
287279

@@ -291,8 +283,6 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah)
291283
ath_dbg(common, MCI, "MCI SYS_WAKING from remote(BT)\n");
292284
mci->bt_state = MCI_BT_AWAKE;
293285

294-
if (AR_SREV_9462_10(ah))
295-
udelay(10);
296286
/*
297287
* we don't need to send more remote_reset at this moment.
298288
* If BT receive first remote_reset, then BT HW will
@@ -339,15 +329,14 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah)
339329
REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
340330
AR_MCI_INTERRUPT_BT_PRI);
341331

342-
if (AR_SREV_9462_10(ah) || mci->is_2g) {
332+
if (mci->is_2g) {
343333
/* Send LNA_TRANS */
344334
ath_dbg(common, MCI, "MCI send LNA_TRANS to BT\n");
345335
ar9003_mci_send_lna_transfer(ah, true);
346336
udelay(5);
347337
}
348338

349-
if (AR_SREV_9462_10(ah) || (mci->is_2g &&
350-
!mci->update_2g5g)) {
339+
if ((mci->is_2g && !mci->update_2g5g)) {
351340
if (ar9003_mci_wait_for_interrupt(ah,
352341
AR_MCI_INTERRUPT_RX_MSG_RAW,
353342
AR_MCI_INTERRUPT_RX_MSG_LNA_INFO,
@@ -358,14 +347,6 @@ static void ar9003_mci_prep_interface(struct ath_hw *ah)
358347
ath_dbg(common, MCI,
359348
"MCI BT didn't respond to LNA_TRANS\n");
360349
}
361-
362-
if (AR_SREV_9462_10(ah)) {
363-
/* Send another remote_reset to deassert BT clk_req. */
364-
ath_dbg(common, MCI,
365-
"MCI another remote_reset to deassert clk_req\n");
366-
ar9003_mci_remote_reset(ah, true);
367-
udelay(252);
368-
}
369350
}
370351

371352
/* Clear the extra redundant SYS_WAKING from BT */
@@ -618,9 +599,6 @@ void ar9003_mci_reset(struct ath_hw *ah, bool en_int, bool is_2g,
618599
} else
619600
ath_dbg(common, MCI, "MCI SCHED one step look ahead off\n");
620601

621-
if (AR_SREV_9462_10(ah))
622-
regval |= SM(1, AR_BTCOEX_CTRL_SPDT_ENABLE_10);
623-
624602
REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
625603

626604
if (AR_SREV_9462_20(ah)) {
@@ -771,9 +749,6 @@ static void ar9003_mci_send_2g5g_status(struct ath_hw *ah, bool wait_done)
771749
ar9003_mci_send_coex_bt_flags(ah, wait_done,
772750
MCI_GPM_COEX_BT_FLAGS_SET, to_set);
773751
}
774-
775-
if (AR_SREV_9462_10(ah) && (mci->bt_state != MCI_BT_SLEEP))
776-
mci->update_2g5g = false;
777752
}
778753

779754
static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
@@ -810,11 +785,8 @@ static void ar9003_mci_queue_unsent_gpm(struct ath_hw *ah, u8 header,
810785
switch (opcode) {
811786
case MCI_GPM_COEX_BT_UPDATE_FLAGS:
812787

813-
if (AR_SREV_9462_10(ah))
814-
break;
815-
816788
if (*(((u8 *)payload) + MCI_GPM_COEX_B_BT_FLAGS_OP) ==
817-
MCI_GPM_COEX_BT_FLAGS_READ)
789+
MCI_GPM_COEX_BT_FLAGS_READ)
818790
break;
819791

820792
mci->update_2g5g = queue;
@@ -1438,9 +1410,7 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type, u32 *p_data)
14381410
break;
14391411

14401412
case MCI_STATE_SEND_STATUS_QUERY:
1441-
query_type = (AR_SREV_9462_10(ah)) ?
1442-
MCI_GPM_COEX_QUERY_BT_ALL_INFO :
1443-
MCI_GPM_COEX_QUERY_BT_TOPOLOGY;
1413+
query_type = MCI_GPM_COEX_QUERY_BT_TOPOLOGY;
14441414

14451415
ar9003_mci_send_coex_bt_status_query(ah, true, query_type);
14461416
break;

drivers/net/wireless/ath/ath9k/ar9003_phy.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -617,10 +617,8 @@
617617
#define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
618618
#define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
619619
#define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
620-
#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
621-
0x4c0 : 0x4c4))
622-
#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + (AR_SREV_9462_10(ah) ? \
623-
0x4c4 : 0x4c8))
620+
#define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4))
621+
#define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8))
624622
#define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
625623
#define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
626624

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