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1 parent 3ac3bcb commit cf5b2d2Copy full SHA for cf5b2d2
arch/mips/include/asm/cpu-features.h
@@ -17,6 +17,8 @@
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#define current_cpu_type() current_cpu_data.cputype
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#endif
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+#define boot_cpu_type() cpu_data[0].cputype
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+
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/*
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* SMP assumption: Options of CPU 0 are a superset of all processors.
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* This is true for all known MIPS systems.
arch/mips/oprofile/op_model_mipsxx.c
@@ -166,7 +166,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
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reg.control[i] |= M_PERFCTL_USER;
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if (ctr[i].exl)
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reg.control[i] |= M_PERFCTL_EXL;
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- if (current_cpu_type() == CPU_XLR)
+ if (boot_cpu_type() == CPU_XLR)
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reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS;
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reg.counter[i] = 0x80000000 - ctr[i].count;
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}
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