@@ -82,13 +82,22 @@ static unsigned int
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vc4_crtc_get_cob_allocation (struct vc4_dev * vc4 , unsigned int channel )
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{
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struct vc4_hvs * hvs = vc4 -> hvs ;
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- u32 dispbase = HVS_READ (SCALER_DISPBASEX (channel ));
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+ u32 dispbase , top , base ;
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+
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/* Top/base are supposed to be 4-pixel aligned, but the
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* Raspberry Pi firmware fills the low bits (which are
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* presumably ignored).
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*/
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- u32 top = VC4_GET_FIELD (dispbase , SCALER_DISPBASEX_TOP ) & ~3 ;
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- u32 base = VC4_GET_FIELD (dispbase , SCALER_DISPBASEX_BASE ) & ~3 ;
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+
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+ if (vc4 -> gen >= VC4_GEN_6 ) {
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+ dispbase = HVS_READ (SCALER6_DISPX_COB (channel ));
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+ top = VC4_GET_FIELD (dispbase , SCALER6_DISPX_COB_TOP ) & ~3 ;
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+ base = VC4_GET_FIELD (dispbase , SCALER6_DISPX_COB_BASE ) & ~3 ;
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+ } else {
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+ dispbase = HVS_READ (SCALER_DISPBASEX (channel ));
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+ top = VC4_GET_FIELD (dispbase , SCALER_DISPBASEX_TOP ) & ~3 ;
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+ base = VC4_GET_FIELD (dispbase , SCALER_DISPBASEX_BASE ) & ~3 ;
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+ }
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return top - base + 4 ;
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}
@@ -121,7 +130,10 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
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* Read vertical scanline which is currently composed for our
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* pixelvalve by the HVS, and also the scaler status.
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*/
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- val = HVS_READ (SCALER_DISPSTATX (channel ));
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+ if (vc4 -> gen >= VC4_GEN_6 )
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+ val = HVS_READ (SCALER6_DISPX_STATUS (channel ));
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+ else
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+ val = HVS_READ (SCALER_DISPSTATX (channel ));
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/* Get optional system timestamp after query. */
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if (etime )
@@ -130,7 +142,12 @@ static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
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/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
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/* Vertical position of hvs composed scanline. */
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- * vpos = VC4_GET_FIELD (val , SCALER_DISPSTATX_LINE );
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+
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+ if (vc4 -> gen >= VC4_GEN_6 )
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+ * vpos = VC4_GET_FIELD (val , SCALER6_DISPX_STATUS_YLINE );
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+ else
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+ * vpos = VC4_GET_FIELD (val , SCALER_DISPSTATX_LINE );
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+
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* hpos = 0 ;
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if (mode -> flags & DRM_MODE_FLAG_INTERLACE ) {
@@ -475,8 +492,10 @@ static void require_hvs_enabled(struct drm_device *dev)
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struct vc4_dev * vc4 = to_vc4_dev (dev );
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struct vc4_hvs * hvs = vc4 -> hvs ;
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- WARN_ON_ONCE ((HVS_READ (SCALER_DISPCTRL ) & SCALER_DISPCTRL_ENABLE ) !=
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- SCALER_DISPCTRL_ENABLE );
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+ if (vc4 -> gen >= VC4_GEN_6 )
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+ WARN_ON_ONCE (!(HVS_READ (SCALER6_CONTROL ) & SCALER6_CONTROL_HVS_EN ));
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+ else
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+ WARN_ON_ONCE (!(HVS_READ (SCALER_DISPCTRL ) & SCALER_DISPCTRL_ENABLE ));
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}
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static int vc4_crtc_disable (struct drm_crtc * crtc ,
@@ -804,14 +823,21 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
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struct drm_device * dev = crtc -> dev ;
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struct vc4_dev * vc4 = to_vc4_dev (dev );
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struct vc4_hvs * hvs = vc4 -> hvs ;
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+ unsigned int current_dlist ;
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u32 chan = vc4_crtc -> current_hvs_channel ;
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unsigned long flags ;
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spin_lock_irqsave (& dev -> event_lock , flags );
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spin_lock (& vc4_crtc -> irq_lock );
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+
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+ if (vc4 -> gen >= VC4_GEN_6 )
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+ current_dlist = VC4_GET_FIELD (HVS_READ (SCALER6_DISPX_DL (chan )),
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+ SCALER6_DISPX_DL_LACT );
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+ else
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+ current_dlist = HVS_READ (SCALER_DISPLACTX (chan ));
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+
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if (vc4_crtc -> event &&
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- (vc4_crtc -> current_dlist == HVS_READ (SCALER_DISPLACTX (chan )) ||
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- vc4_crtc -> feeds_txp )) {
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+ (vc4_crtc -> current_dlist == current_dlist || vc4_crtc -> feeds_txp )) {
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drm_crtc_send_vblank_event (crtc , vc4_crtc -> event );
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vc4_crtc -> event = NULL ;
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drm_crtc_vblank_put (crtc );
@@ -822,7 +848,8 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
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* the CRTC and encoder already reconfigured, leading to
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* underruns. This can be seen when reconfiguring the CRTC.
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*/
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- vc4_hvs_unmask_underrun (hvs , chan );
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+ if (vc4 -> gen < VC4_GEN_6 )
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+ vc4_hvs_unmask_underrun (hvs , chan );
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}
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spin_unlock (& vc4_crtc -> irq_lock );
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spin_unlock_irqrestore (& dev -> event_lock , flags );
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