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3.12.0-rc3+: dwc_otg_core_reset() HANG! Soft Reset GRSTCTL=80000001 #393

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notro opened this issue Oct 2, 2013 · 8 comments
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3.12.0-rc3+: dwc_otg_core_reset() HANG! Soft Reset GRSTCTL=80000001 #393

notro opened this issue Oct 2, 2013 · 8 comments

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@notro
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notro commented Oct 2, 2013

I'm attempting to use dwc_otg with 3.12.0-rc3+
Anyone know what this could be? No mouse or keyboard is detected.

$ lsusb
Bus 001 Device 001: ID 1d6b:0002 Linux Foundation 2.0 root hub

Kernel messages

Linux version 3.12.0-rc3+ (pi@raspi1) (gcc version 4.7.1 20120402 (prerelease) (crosstool-NG 1.15.2) ) #6 Wed Oct 2 18:26:51 CEST 2013
CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
Machine: BCM2835, model: v5 Raspberry Pi Model B
[...]
dwc_otg: version 3.00a 10-AUG-2012 (platform bus)
Core Release: 2.80a
Setting default values for core params
Finished setting default values for core params
WARN::dwc_otg_core_reset:5119: dwc_otg_core_reset() HANG! Soft Reset GRSTCTL=80000001

WARN::dwc_otg_core_reset:5119: dwc_otg_core_reset() HANG! Soft Reset GRSTCTL=80000001

Using Buffer DMA mode
Periodic Transfer Interrupt Enhancement - disabled
Multiprocessor Interrupt Enhancement - disabled
OTG VER PARAM: 0, OTG VER FLAG: 0
Dedicated Tx FIFOs mode
dwc_otg: Microframe scheduler enabled
dwc_otg bcm2708_usb: DWC OTG Controller
dwc_otg bcm2708_usb: new USB bus registered, assigned bus number 1
dwc_otg bcm2708_usb: irq 32, io mem 0x00000000
Init: Port Power? op_state=1
Init: Power Port (0)
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
dwc_otg: FIQ enabled
dwc_otg: NAK holdoff enabled
dwc_otg: FIQ split fix enabled
Module dwc_common_port init
[...]
usbcore: registered new interface driver usbhid
usbhid: USB HID core driver

Google gave me this link: http://embedded-software.blogspot.no/2010/12/ar-drone-usb.html
But gpio 127 is already low

$ gpio read 127
0
@P33M
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P33M commented Oct 2, 2013

GPIO127 doesn't exist on the Pi. There's 53 only. The onboard PHY is also internally connected to the DWC core, there are no accessible signals at a hardware level.

Can you try with the FIQ disabled?

@notro
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notro commented Oct 2, 2013

It didn't help. I have turned on some debug output this time

dwc_otg: version 3.00a 10-AUG-2012 (platform bus)
DWC_otg: Platform resource: start=20980000, len=00020000
DWC_otg: dwc_otg_cil_init(f0980000)
DWC_otg: in_ep_regs[0]->diepctl=f0980900
DWC_otg: out_ep_regs[0]->doepctl=f0980b00
DWC_otg: in_ep_regs[1]->diepctl=f0980920
DWC_otg: out_ep_regs[1]->doepctl=f0980b20
DWC_otg: in_ep_regs[2]->diepctl=f0980940
DWC_otg: out_ep_regs[2]->doepctl=f0980b40
DWC_otg: in_ep_regs[3]->diepctl=f0980960
DWC_otg: out_ep_regs[3]->doepctl=f0980b60
DWC_otg: in_ep_regs[4]->diepctl=f0980980
DWC_otg: out_ep_regs[4]->doepctl=f0980b80
DWC_otg: in_ep_regs[5]->diepctl=f09809a0
DWC_otg: out_ep_regs[5]->doepctl=f0980ba0
DWC_otg: in_ep_regs[6]->diepctl=f09809c0
DWC_otg: out_ep_regs[6]->doepctl=f0980bc0
DWC_otg: in_ep_regs[7]->diepctl=f09809e0
DWC_otg: out_ep_regs[7]->doepctl=f0980be0
DWC_otg: in_ep_regs[8]->diepctl=f0980a00
DWC_otg: out_ep_regs[8]->doepctl=f0980c00
DWC_otg: in_ep_regs[9]->diepctl=f0980a20
DWC_otg: out_ep_regs[9]->doepctl=f0980c20
DWC_otg: in_ep_regs[10]->diepctl=f0980a40
DWC_otg: out_ep_regs[10]->doepctl=f0980c40
DWC_otg: in_ep_regs[11]->diepctl=f0980a60
DWC_otg: out_ep_regs[11]->doepctl=f0980c60
DWC_otg: in_ep_regs[12]->diepctl=f0980a80
DWC_otg: out_ep_regs[12]->doepctl=f0980c80
DWC_otg: in_ep_regs[13]->diepctl=f0980aa0
DWC_otg: out_ep_regs[13]->doepctl=f0980ca0
DWC_otg: in_ep_regs[14]->diepctl=f0980ac0
DWC_otg: out_ep_regs[14]->doepctl=f0980cc0
DWC_otg: in_ep_regs[15]->diepctl=f0980ae0
DWC_otg: out_ep_regs[15]->doepctl=f0980ce0
DWC_otg: hc_reg[0]->hcchar=f0980500
DWC_otg: hc_reg[1]->hcchar=f0980520
DWC_otg: hc_reg[2]->hcchar=f0980540
DWC_otg: hc_reg[3]->hcchar=f0980560
DWC_otg: hc_reg[4]->hcchar=f0980580
DWC_otg: hc_reg[5]->hcchar=f09805a0
DWC_otg: hc_reg[6]->hcchar=f09805c0
DWC_otg: hc_reg[7]->hcchar=f09805e0
DWC_otg: hc_reg[8]->hcchar=f0980600
DWC_otg: hc_reg[9]->hcchar=f0980620
DWC_otg: hc_reg[10]->hcchar=f0980640
DWC_otg: hc_reg[11]->hcchar=f0980660
DWC_otg: hc_reg[12]->hcchar=f0980680
DWC_otg: hc_reg[13]->hcchar=f09806a0
DWC_otg: hc_reg[14]->hcchar=f09806c0
DWC_otg: hc_reg[15]->hcchar=f09806e0
DWC_otg: data_fifo[0]=0xf0981000
DWC_otg: data_fifo[1]=0xf0982000
DWC_otg: data_fifo[2]=0xf0983000
DWC_otg: data_fifo[3]=0xf0984000
DWC_otg: data_fifo[4]=0xf0985000
DWC_otg: data_fifo[5]=0xf0986000
DWC_otg: data_fifo[6]=0xf0987000
DWC_otg: data_fifo[7]=0xf0988000
DWC_otg: data_fifo[8]=0xf0989000
DWC_otg: data_fifo[9]=0xf098a000
DWC_otg: data_fifo[10]=0xf098b000
DWC_otg: data_fifo[11]=0xf098c000
DWC_otg: data_fifo[12]=0xf098d000
DWC_otg: data_fifo[13]=0xf098e000
DWC_otg: data_fifo[14]=0xf098f000
DWC_otg: data_fifo[15]=0xf0990000
DWC_otg: hwcfg1=00000000
DWC_otg: hwcfg2=228ddd50
DWC_otg: hwcfg3=0ff000e8
DWC_otg: hwcfg4=1ff00020
DWC_otg: hcfg=00200000
DWC_otg: dcfg=00200000
DWC_otg: op_mode=0
DWC_otg: arch=2
DWC_otg: num_dev_ep=7
DWC_otg: num_host_chan=7
DWC_otg: nonperio_tx_q_depth=0x2
DWC_otg: host_perio_tx_q_depth=0x2
DWC_otg: dev_token_q_depth=0x8
DWC_otg: Total FIFO SZ=4080
DWC_otg: xfer_size_cntr_width=8
Core Release: 2.80a
Setting default values for core params
Finished setting default values for core params
DWC_otg: probe of device db988e20 given core_if db950c00
DWC_otg: registering (common) handler for irq75
DWC_otg: dwc_otg_core_init(db950c00) regs at f0980000
DWC_otg: dwc_otg_core_reset
WARN::dwc_otg_core_reset:5119: dwc_otg_core_reset() HANG! Soft Reset GRSTCTL=80000001

DWC_otg: num_dev_perio_in_ep=0
DWC_otg: Tx FIFO SZ #0=0x200
DWC_otg: Tx FIFO SZ #1=0x200
DWC_otg: Tx FIFO SZ #2=0x200
DWC_otg: Tx FIFO SZ #3=0x200
DWC_otg: Tx FIFO SZ #4=0x200
DWC_otg: Tx FIFO SZ #5=0x200
DWC_otg: Tx FIFO SZ #6=0x200
DWC_otg: Total FIFO SZ=4080
DWC_otg: Rx FIFO SZ=4096
DWC_otg: NP Tx FIFO SZ=4096
DWC_otg: dwc_otg_core_reset
WARN::dwc_otg_core_reset:5119: dwc_otg_core_reset() HANG! Soft Reset GRSTCTL=80000001

DWC_otg: Internal DMA Mode
Using Buffer DMA mode
Periodic Transfer Interrupt Enhancement - disabled
Multiprocessor Interrupt Enhancement - disabled
OTG VER PARAM: 0, OTG VER FLAG: 0
DWC_otg: Host Mode
DWC_otg: pcd_init(c05891e0) otg_dev=db988e20
DWC_otg: Init of PCD db81c000 given core_if db950c00
Dedicated Tx FIFOs mode
DWC_otg: gadget_add_eps
DWC_otg: registering handler for irq75
DWC_otg: DWC OTG HCD INIT otg_dev=db988e20
DWC_otg: init of HCD db951000 given core_if db950c00
DWC_otg: HCD Added channel #0, hc=db98a360
DWC_otg: HCD Added channel #1, hc=db98a3c0
DWC_otg: HCD Added channel #2, hc=db98a420
DWC_otg: HCD Added channel #3, hc=db98a480
DWC_otg: HCD Added channel #4, hc=db98a4e0
DWC_otg: HCD Added channel #5, hc=db98a540
DWC_otg: HCD Added channel #6, hc=db98a5a0
DWC_otg: HCD Added channel #7, hc=db98a600
dwc_otg: Microframe scheduler enabled
dwc_otg bcm2708_usb: DWC OTG Controller
dwc_otg bcm2708_usb: new USB bus registered, assigned bus number 1
dwc_otg bcm2708_usb: irq 75, io mem 0x00000000
DWC_otg: DWC OTG HCD START
DWC_otg: dwc_otg_core_host_init(db950c00)
DWC_otg: Initializing HCFG.FSLSPClkSel to 0x0
DWC_otg: Total FIFO Size=4080
DWC_otg: Rx FIFO Size=774
DWC_otg: NP Tx FIFO Size=32
DWC_otg: P Tx FIFO Size=0
DWC_otg: initial grxfsiz=00001000
DWC_otg: new grxfsiz=00001000
DWC_otg: initial gnptxfsiz=10001000
DWC_otg: new gnptxfsiz=10001000
DWC_otg: initial hptxfsiz=02001020
DWC_otg: new hptxfsiz=02001020
DWC_otg: Flush Tx FIFO 16
DWC_otg: dwc_otg_flush_rx_fifo
DWC_otg: dwc_otg_core_host_init: Halt channel 0 regs f0980500
DWC_otg: dwc_otg_core_host_init: Halt channel 1 regs f0980520
DWC_otg: dwc_otg_core_host_init: Halt channel 2 regs f0980540
DWC_otg: dwc_otg_core_host_init: Halt channel 3 regs f0980560
DWC_otg: dwc_otg_core_host_init: Halt channel 4 regs f0980580
DWC_otg: dwc_otg_core_host_init: Halt channel 5 regs f09805a0
DWC_otg: dwc_otg_core_host_init: Halt channel 6 regs f09805c0
DWC_otg: dwc_otg_core_host_init: Halt channel 7 regs f09805e0
Init: Port Power? op_state=1
Init: Power Port (0)
DWC_otg: dwc_otg_enable_host_interrupts(db950c00)
DWC_otg: DWC OTG HCD Has Root Hub
hub 1-0:1.0: USB hub found
DWC_otg: DWC OTG HCD HUB CONTROL - GetHubDescriptor
hub 1-0:1.0: 1 port detected
DWC_otg: DWC OTG HCD HUB CONTROL - GetHubStatus
dwc_otg: FIQ disabled
dwc_otg: NAK holdoff enabled
dwc_otg: FIQ split fix disabled
Module dwc_common_port init
[...]
DWC_otg: DWC OTG HCD HUB CONTROL - GetPortStatus wIndex = 0x0001 FLAGS=0x00000000

This is the source code diff: https://gist.github.com/notro/6798734
In addition to this I have copied these directories from the 3.10.y branch:
arch/arm/mach-bcm2835/include/mach/{arm_control.h,hardware.h,platform.h}
drivers/usb/host/dwc_common_port/
drivers/usb/host/dwc_otg/

@notro
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notro commented Oct 3, 2013

I have tried to track the register address used to do the reset, and it depends on the address range given through the platform_device.
Is the address f0980000 correct?

[    0.597398] DWC_otg: Platform resource: start=20980000, len=00020000
[    0.603814] DWC_otg: dwc_otg_cil_init(f0980000)

[    1.180095] DWC_otg: probe of device db988e20 given core_if db950c00
[    1.186651] DWC_otg: registering (common) handler for irq32
[    1.192299] DWC_otg: dwc_otg_core_init(db950c00) regs at f0980000
[    1.198388] DWC_otg: dwc_otg_core_reset
[    1.202259] DWC_otg: dwc_otg_core_reset() 1 GRSTCTL=80000000, ahbidle=1, csftrst=0
[    2.217543] WARN::dwc_otg_core_reset:5127: dwc_otg_core_reset() HANG! Soft Reset GRSTCTL=80000001
[    2.217543]
[    2.227916] DWC_otg: dwc_otg_core_reset() 2 GRSTCTL=80000001, ahbidle=1, csftrst=1

[    2.378072] DWC_otg: dwc_otg_core_reset
[    2.381932] DWC_otg: dwc_otg_core_reset() 1 GRSTCTL=80000001, ahbidle=1, csftrst=1
[    3.397200] WARN::dwc_otg_core_reset:5127: dwc_otg_core_reset() HANG! Soft Reset GRSTCTL=80000001
[    3.397200]
[    3.407570] DWC_otg: dwc_otg_core_reset() 2 GRSTCTL=80000001, ahbidle=1, csftrst=1

Code snippets

static int dwc_otg_driver_probe(struct platform_device *_dev)
{
[...]
    dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
[...]
        DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n",
                    _dev->resource->start,
                    _dev->resource->end - _dev->resource->start + 1);

        if (!request_mem_region(_dev->resource[0].start,
                                _dev->resource[0].end - _dev->resource[0].start + 1,
                                "dwc_otg")) {
          dev_dbg(&_dev->dev, "error reserving mapped memory\n");
          retval = -EFAULT;
          goto fail;
        }

    dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start,
                                                      _dev->resource[0].end -
                                                      _dev->resource[0].start+1);

[...]
    dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
        DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n",
                    dwc_otg_device, dwc_otg_device->core_if);//GRAYG
[...]
}


dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
{
    uint8_t *reg_base = (uint8_t *) reg_base_addr;

    core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
    core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
}


void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
{
    dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;

greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
DWC_DEBUGPL(DBG_CILV, "%s() 1 GRSTCTL=%0x, ahbidle=%0x, csftrst=%0x\n", __func__, greset.d32, greset.b.ahbidle, greset.b.csftrst);

    /* Core Soft Reset */
    count = 0;
    greset.b.csftrst = 1;
    DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
    do {
        greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
        if (++count > 10000) {
            DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
                 __func__, greset.d32);
            break;
        }
        dwc_udelay(1);
    }
    while (greset.b.csftrst == 1);

DWC_DEBUGPL(DBG_CILV, "%s() 2 GRSTCTL=%0x, ahbidle=%0x, csftrst=%0x\n", __func__, greset.d32, greset.b.ahbidle, greset.b.csftrst);

}

@notro
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notro commented Oct 3, 2013

I have looked at the BCM2835 commits and found that from 3.11 to 3.12 there is no important changes, and from 3.10 to 3.11 there is only one change:
ARM: bcm2835: Add Raspberry Pi's ACT LED to DT

This means I can use the 3.10.y branch instead to try and make USB work with BCM2835.

@notro
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notro commented Oct 3, 2013

3.10.14 and 3.11.2 from kernel.org boots fine, but rpi-3.10.y and rpi.3.11.y won't boot. I use the same raspian image in all tests. Just changing kernel and DT.

This is what I do:

Add to bcm2835-rpi-b.dts

/memreserve/ 0x1c000000 0x04000000;

/ {
    chosen {
        bootargs = "debug earlyprintk dtb dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait";
    };
};

Build

make bcm2835_defconfig
make -j4

3.11.2 from kernel.org boot messages: https://gist.github.com/notro/6811898

rpi-3.11.y kernel messages

[    0.000000] Linux version 3.11.2+ (pi@raspi1) (gcc version 4.7.1 20120402 (prerelease) (crosstool-NG 1.15.2) ) #1 Thu Oct 3 15:58:37 CEST 2013

[    0.000000] Kernel command line: debug earlyprintk dtb dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait

[    0.558989] Waiting for root device /dev/mmcblk0p2...
[    0.576333] mmc0: new SDHC card at address 0007
[    0.581502] mmcblk0: mmc0:0007 SD8GB 7.21 GiB
[    0.587880]  mmcblk0: p1 p2
[   10.678012] mmc0: Timeout waiting for hardware interrupt - cmd18.
[   10.684355] mmcblk0: error -110 sending stop command, original cmd response 0x900, card status 0x900
[   10.693530] mmcblk0: error -110 transferring data, sector 122882, nr 2, cmd response 0x900, card status 0x0
[   10.703295] mmcblk0: retrying using single block read
[   10.711524] EXT4-fs (mmcblk0p2): Magic mismatch, very weird!
[   10.717295] List of all partitions:
[   10.720869] b300         7561216 mmcblk0  driver: mmcblk
[   10.726195]   b301           57344 mmcblk0p1 000b03b7-01
[   10.731553]   b302         7499776 mmcblk0p2 000b03b7-02
[   10.736862] No filesystem could mount root, tried:  ext4
[   10.742222] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2)
[   10.750656] CPU: 0 PID: 1 Comm: swapper Not tainted 3.11.2+ #1
[   10.756548] [<c0015448>] (unwind_backtrace+0x0/0x128) from [<c0012338>] (show_stack+0x20/0x24)
[   10.765188] [<c0012338>] (show_stack+0x20/0x24) from [<c03851e4>] (dump_stack+0x20/0x28)
[   10.773291] [<c03851e4>] (dump_stack+0x20/0x28) from [<c0382458>] (panic+0x84/0x1e0)
[   10.781046] [<c0382458>] (panic+0x84/0x1e0) from [<c04c2288>] (mount_block_root+0x284/0x2f4)
[   10.789487] [<c04c2288>] (mount_block_root+0x284/0x2f4) from [<c04c2350>] (mount_root+0x58/0x70)
[   10.798273] [<c04c2350>] (mount_root+0x58/0x70) from [<c04c2498>] (prepare_namespace+0x130/0x190)
[   10.807146] [<c04c2498>] (prepare_namespace+0x130/0x190) from [<c04c1e50>] (kernel_init_freeable+0x1a8/0x1f0)
[   10.817062] [<c04c1e50>] (kernel_init_freeable+0x1a8/0x1f0) from [<c03815c8>] (kernel_init+0x18/0xf4)
[   10.826287] [<c03815c8>] (kernel_init+0x18/0xf4) from [<c000e9d8>] (ret_from_fork+0x14/0x20)
PANIC: VFS: Unable to mount root fs on unknown-block(179,2)

Entering kdb (current=0xdb84c000, pid 1) due to Keyboard Entry
kdb>

@notro
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notro commented Oct 3, 2013

I have turned on debugging on my BCM2708 rpi-3.10.y kernel and I get a different address f2980000 from what I did on 3.12 f0980000. Is this significant?

Linux version 3.10.12+ (pi@raspi1) (gcc version 4.7.1 20120402 (prerelease) (crosstool-NG 1.15.2) ) #54 Thu Oct 3 21:01:02 CEST 2013

dwc_otg: version 3.00a 10-AUG-2012 (platform bus)
DWC_otg: Platform resource: start=20980000, len=00020000
DWC_otg: dwc_otg_cil_init(f2980000)

@marcopi
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marcopi commented Oct 4, 2013

I also have problem in booting 3.11.

Perhaps this link can help:
http://www.raspberrypi.org/phpBB3/viewtopic.php?t=55284&p=419510

@notro notro closed this as completed Oct 5, 2013
@notro notro mentioned this issue Nov 14, 2013
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@zain5248
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Were you ever able to solve this issue?

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