diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 10fede16c588fc..8d35327a3fa4b3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -330,6 +330,7 @@ config ARCH_BCM2708 select GENERIC_CLOCKEVENTS select ARM_ERRATA_411920 select MACH_BCM2708 + select MULTI_IRQ_HANDLER select VC4 select FIQ help diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5f166afff5e0d1..4f1bb6fabed2f5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -3,6 +3,7 @@ ifeq ($(CONFIG_OF),y) dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b.dtb dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b-plus.dtb dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-cm.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-cm.dtb dtb-$(CONFIG_BCM2709_DT) += bcm2709-rpi-2-b.dtb # Raspberry Pi diff --git a/arch/arm/boot/dts/bcm2708.dtsi b/arch/arm/boot/dts/bcm2708.dtsi index 57d4c5680df98d..b5b54ce76197d3 100644 --- a/arch/arm/boot/dts/bcm2708.dtsi +++ b/arch/arm/boot/dts/bcm2708.dtsi @@ -24,3 +24,7 @@ }; }; }; + +&intc { + compatible = "brcm,bcm2835-armctrl-ic"; +}; diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi index f096f457ea846c..0420ebcb7e7b4a 100644 --- a/arch/arm/boot/dts/bcm2708_common.dtsi +++ b/arch/arm/boot/dts/bcm2708_common.dtsi @@ -65,7 +65,7 @@ brcm,dma-channel-mask = <0x0f35>; }; - intc: interrupt-controller { + intc: interrupt-controller@7e00b200 { compatible = "brcm,bcm2708-armctrl-ic"; reg = <0x7e00b200 0x200>; interrupt-controller; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index 668442b1bda581..17e24434b201d6 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -1,30 +1,128 @@ /dts-v1/; -#include "bcm2835-rpi.dtsi" +#include "bcm2835.dtsi" / { compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; model = "Raspberry Pi Model B+"; +}; - leds { - act { - gpios = <&gpio 47 0>; - }; +&gpio { + spi0_pins: spi0_pins { + brcm,pins = <7 8 9 10 11>; + brcm,function = <4>; /* alt0 */ + }; - pwr { - label = "PWR"; - gpios = <&gpio 35 0>; - default-state = "keep"; - linux,default-trigger = "default-on"; - }; + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; }; -}; -&gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; - /* I2S interface */ - i2s_alt0: i2s_alt0 { + i2s_pins: i2s { brcm,pins = <18 19 20 21>; - brcm,function = ; + brcm,function = <4>; /* alt0 */ + }; +}; + +&mmc { + status = "okay"; + bus-width = <4>; +}; + +&fb { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <500000>; + }; + + spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <500000>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: act { + label = "led0"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 47 0>; + }; + + pwr_led: pwr { + label = "led1"; + linux,default-trigger = "input"; + gpios = <&gpio 35 0>; + }; +}; + +/ { + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; + uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; + i2c1 = <&i2c1>,"status"; + i2c2_iknowwhatimdoing = <&i2c2>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; + i2c2_baudrate = <&i2c2>,"clock-frequency:0"; + core_freq = <&clk_core>,"clock-frequency:0"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + pwr_led_gpio = <&pwr_led>,"gpios:4"; + pwr_led_activelow = <&pwr_led>,"gpios:8"; + pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; + + audio = <&audio>,"status"; + watchdog = <&watchdog>,"status"; + random = <&random>,"status"; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index ee89b79426cf4d..221d2524798d16 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -1,23 +1,118 @@ /dts-v1/; -#include "bcm2835-rpi.dtsi" +#include "bcm2835.dtsi" / { compatible = "raspberrypi,model-b", "brcm,bcm2835"; model = "Raspberry Pi Model B"; - - leds { - act { - gpios = <&gpio 16 1>; - }; - }; }; &gpio { - pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; + spi0_pins: spi0_pins { + brcm,pins = <7 8 9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; - /* I2S interface */ - i2s_alt2: i2s_alt2 { + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { brcm,pins = <28 29 30 31>; - brcm,function = ; + brcm,function = <6>; /* alt2 */ + }; +}; + +&mmc { + status = "okay"; + bus-width = <4>; +}; + +&fb { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <500000>; + }; + + spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <500000>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +&leds { + act_led: act { + label = "led0"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 16 1>; + }; +}; + +/ { + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; + uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; + i2c1 = <&i2c1>,"status"; + i2c2_iknowwhatimdoing = <&i2c2>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; + i2c2_baudrate = <&i2c2>,"clock-frequency:0"; + core_freq = <&clk_core>,"clock-frequency:0"; + + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + audio = <&audio>,"status"; + watchdog = <&watchdog>,"status"; + random = <&random>,"status"; }; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm.dts b/arch/arm/boot/dts/bcm2835-rpi-cm.dts new file mode 100644 index 00000000000000..c6e6860a6d4356 --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-cm.dts @@ -0,0 +1,93 @@ +/dts-v1/; + +#include "bcm2835-rpi-cm.dtsi" + +/ { + model = "Raspberry Pi Compute Module"; +}; + +&uart0 { + status = "okay"; +}; + +&gpio { + spi0_pins: spi0_pins { + brcm,pins = <7 8 9 10 11>; + brcm,function = <4>; /* alt0 */ + }; + + i2c0_pins: i2c0 { + brcm,pins = <0 1>; + brcm,function = <4>; + }; + + i2c1_pins: i2c1 { + brcm,pins = <2 3>; + brcm,function = <4>; + }; + + i2s_pins: i2s { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + + spidev@0{ + compatible = "spidev"; + reg = <0>; /* CE0 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <500000>; + }; + + spidev@1{ + compatible = "spidev"; + reg = <1>; /* CE1 */ + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <500000>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2s { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_pins>; +}; + +/ { + __overrides__ { + uart0 = <&uart0>,"status"; + uart0_clkrate = <&clk_uart0>,"clock-frequency:0"; + uart1_clkrate = <&uart1>,"clock-frequency:0"; + i2s = <&i2s>,"status"; + spi = <&spi0>,"status"; + i2c0 = <&i2c0>,"status"; + i2c1 = <&i2c1>,"status"; + i2c2_iknowwhatimdoing = <&i2c2>,"status"; + i2c0_baudrate = <&i2c0>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; + i2c2_baudrate = <&i2c2>,"clock-frequency:0"; + core_freq = <&clk_core>,"clock-frequency:0"; + }; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm.dtsi b/arch/arm/boot/dts/bcm2835-rpi-cm.dtsi new file mode 100644 index 00000000000000..9c4000fc686a98 --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-cm.dtsi @@ -0,0 +1,30 @@ +#include "bcm2835.dtsi" + +&leds { + act_led: act { + label = "led0"; + linux,default-trigger = "mmc0"; + gpios = <&gpio 47 0>; + }; +}; + +&mmc { + status = "okay"; + bus-width = <4>; +}; + +&fb { + status = "okay"; +}; + +/ { + __overrides__ { + act_led_gpio = <&act_led>,"gpios:4"; + act_led_activelow = <&act_led>,"gpios:8"; + act_led_trigger = <&act_led>,"linux,default-trigger"; + + audio = <&audio>,"status"; + watchdog = <&watchdog>,"status"; + random = <&random>,"status"; + }; +}; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 440717c6925128..3256bff273466a 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -1,20 +1,15 @@ -#include -#include "skeleton.dtsi" +#include "bcm2708_common.dtsi" / { compatible = "brcm,bcm2835"; model = "BCM2835"; - interrupt-parent = <&intc>; chosen { - bootargs = "earlyprintk console=ttyAMA0"; + bootargs = ""; }; soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x7e000000 0x20000000 0x02000000>; + ranges = <0x7e000000 0x20000000 0x01000000>; dma-ranges = <0x40000000 0x00000000 0x20000000>; timer@7e003000 { @@ -24,169 +19,21 @@ clock-frequency = <1000000>; }; - dma: dma@7e007000 { - compatible = "brcm,bcm2835-dma"; - reg = <0x7e007000 0xf00>; - interrupts = <1 16>, - <1 17>, - <1 18>, - <1 19>, - <1 20>, - <1 21>, - <1 22>, - <1 23>, - <1 24>, - <1 25>, - <1 26>, - <1 27>, - <1 28>; - - #dma-cells = <1>; - brcm,dma-channel-mask = <0x7f35>; - }; - - intc: interrupt-controller@7e00b200 { - compatible = "brcm,bcm2835-armctrl-ic"; - reg = <0x7e00b200 0x200>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - watchdog@7e100000 { - compatible = "brcm,bcm2835-pm-wdt"; - reg = <0x7e100000 0x28>; - }; - - rng@7e104000 { - compatible = "brcm,bcm2835-rng"; - reg = <0x7e104000 0x10>; - }; - - mailbox: mailbox@7e00b800 { - compatible = "brcm,bcm2835-mbox"; - reg = <0x7e00b880 0x40>; - interrupts = <0 1>; - #mbox-cells = <0>; - }; - - gpio: gpio@7e200000 { - compatible = "brcm,bcm2835-gpio"; - reg = <0x7e200000 0xb4>; - /* - * The GPIO IP block is designed for 3 banks of GPIOs. - * Each bank has a GPIO interrupt for itself. - * There is an overall "any bank" interrupt. - * In order, these are GIC interrupts 17, 18, 19, 20. - * Since the BCM2835 only has 2 banks, the 2nd bank - * interrupt output appears to be mirrored onto the - * 3rd bank's interrupt signal. - * So, a bank0 interrupt shows up on 17, 20, and - * a bank1 interrupt shows up on 18, 19, 20! - */ - interrupts = <2 17>, <2 18>, <2 19>, <2 20>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - uart@7e201000 { - compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell"; - reg = <0x7e201000 0x1000>; - interrupts = <2 25>; - clock-frequency = <3000000>; - arm,primecell-periphid = <0x00241011>; - }; - - i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x24>, - <0x7e101098 0x08>; - - dmas = <&dma 2>, - <&dma 3>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spi: spi@7e204000 { - compatible = "brcm,bcm2835-spi"; - reg = <0x7e204000 0x1000>; - interrupts = <2 22>; - clocks = <&clk_spi>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c0: i2c@7e205000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e205000 0x1000>; - interrupts = <2 21>; - clocks = <&clk_i2c>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - sdhci: sdhci@7e300000 { - compatible = "brcm,bcm2835-sdhci"; - reg = <0x7e300000 0x100>; - interrupts = <2 30>; - clocks = <&clk_mmc>; - status = "disabled"; - }; - - i2c1: i2c@7e804000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e804000 0x1000>; - interrupts = <2 21>; - clocks = <&clk_i2c>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - usb@7e980000 { - compatible = "brcm,bcm2835-usb"; - reg = <0x7e980000 0x10000>; - interrupts = <1 9>; - }; - arm-pmu { compatible = "arm,arm1176-pmu"; }; - }; - - clocks { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - clk_mmc: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-output-names = "mmc"; - clock-frequency = <100000000>; + aux_enable: aux_enable@0x7e215004 { + compatible = "bcrm,bcm2835-aux-enable"; + reg = <0x7e215004 0x04>; }; + }; +}; - clk_i2c: clock@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-output-names = "i2c"; - clock-frequency = <250000000>; - }; +&intc { + compatible = "brcm,bcm2835-armctrl-ic"; +}; - clk_spi: clock@2 { - compatible = "fixed-clock"; - reg = <2>; - #clock-cells = <0>; - clock-output-names = "spi"; - clock-frequency = <250000000>; - }; - }; +&watchdog { + status = "okay"; }; diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index 47f2a6aad84833..5b391a53343084 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -52,6 +52,8 @@ CONFIG_KSM=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA=y +CONFIG_ZSMALLOC=m +CONFIG_PGTABLE_MAPPING=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_SECCOMP=y CONFIG_ZBOOT_ROM_TEXT=0x0 @@ -394,6 +396,8 @@ CONFIG_DEVTMPFS_MOUNT=y # CONFIG_STANDALONE is not set CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_ZRAM=m +CONFIG_ZRAM_LZ4_COMPRESS=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=m CONFIG_BLK_DEV_DRBD=m @@ -519,6 +523,8 @@ CONFIG_RT2800USB_RT3573=y CONFIG_RT2800USB_RT53XX=y CONFIG_RT2800USB_RT55XX=y CONFIG_RT2800USB_UNKNOWN=y +CONFIG_WL_MEDIATEK=y +CONFIG_MT7601U=m CONFIG_RTL8192CU=m CONFIG_ZD1211RW=m CONFIG_MWIFIEX=m @@ -536,9 +542,11 @@ CONFIG_JOYSTICK_IFORCE=m CONFIG_JOYSTICK_IFORCE_USB=y CONFIG_JOYSTICK_XPAD=m CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_RPISENSE=m CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ADS7846=m CONFIG_TOUCHSCREEN_EGALAX=m +CONFIG_TOUCHSCREEN_RPI_FT5406=m CONFIG_TOUCHSCREEN_USB_COMPOSITE=m CONFIG_TOUCHSCREEN_STMPE=m CONFIG_INPUT_MISC=y @@ -557,21 +565,30 @@ CONFIG_SERIO_RAW=m CONFIG_GAMEPORT=m CONFIG_GAMEPORT_NS558=m CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VC_CMA=y +CONFIG_BCM_VCIO=y +CONFIG_BCM_VC_SM=y CONFIG_DEVPTS_MULTIPLE_INSTANCES=y # CONFIG_LEGACY_PTYS is not set # CONFIG_DEVKMEM is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set +CONFIG_SERIAL_8250_NR_UARTS=1 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 CONFIG_SERIAL_AMBA_PL011=y CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y CONFIG_TTY_PRINTK=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_BCM2835=m CONFIG_RAW_DRIVER=y -CONFIG_BRCM_CHAR_DRIVERS=y -CONFIG_BCM_VC_CMA=y -CONFIG_BCM_VC_SM=y CONFIG_I2C=y CONFIG_I2C_CHARDEV=m -CONFIG_I2C_BCM2835=y +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2835=m CONFIG_SPI=y CONFIG_SPI_BCM2835=m CONFIG_SPI_SPIDEV=y @@ -600,6 +617,8 @@ CONFIG_W1_SLAVE_DS2781=m CONFIG_W1_SLAVE_DS28E04=m CONFIG_W1_SLAVE_BQ27000=m CONFIG_BATTERY_DS2760=m +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y # CONFIG_HWMON is not set CONFIG_THERMAL=y CONFIG_THERMAL_BCM2835=y @@ -778,6 +797,7 @@ CONFIG_VIDEO_MT9V011=m CONFIG_FB=y CONFIG_FB_BCM2708=y CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m # CONFIG_BACKLIGHT_GENERIC is not set CONFIG_BACKLIGHT_GPIO=m CONFIG_FRAMEBUFFER_CONSOLE=y @@ -807,6 +827,7 @@ CONFIG_SND_USB_CAIAQ_INPUT=y CONFIG_SND_USB_6FIRE=m CONFIG_SND_SOC=m CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_BCM2708_SOC_I2S=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m @@ -814,6 +835,7 @@ CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m CONFIG_SND_BCM2708_SOC_RPI_DAC=m CONFIG_SND_BCM2708_SOC_RPI_PROTO=m CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m +CONFIG_SND_SOC_WM8804_I2C=m CONFIG_SND_SIMPLE_CARD=m CONFIG_SOUND_PRIME=m CONFIG_HIDRAW=y @@ -868,6 +890,7 @@ CONFIG_USB_HIDDEV=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_MON=m +CONFIG_USB_DWCOTG=y CONFIG_USB_PRINTER=m CONFIG_USB_STORAGE=y CONFIG_USB_STORAGE_REALTEK=m @@ -1032,6 +1055,7 @@ CONFIG_SPEAKUP_SYNTH_SOFT=m CONFIG_STAGING_MEDIA=y CONFIG_LIRC_STAGING=y CONFIG_LIRC_IMON=m +CONFIG_LIRC_RPI=m CONFIG_LIRC_SASEM=m CONFIG_LIRC_SERIAL=m CONFIG_FB_TFT=m @@ -1063,10 +1087,16 @@ CONFIG_FB_TFT_WATTEROTT=m CONFIG_FB_FLEX=m CONFIG_FB_TFT_FBTFT_DEVICE=m CONFIG_MAILBOX=y -CONFIG_BCM2708_MBOX=y +CONFIG_BCM2835_MBOX=y # CONFIG_IOMMU_SUPPORT is not set CONFIG_EXTCON=m CONFIG_EXTCON_ARIZONA=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_BUFFER_CB=y +CONFIG_IIO_KFIFO_BUF=m +CONFIG_DHT11=m +CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y @@ -1214,7 +1244,6 @@ CONFIG_CRYPTO_TGR192=m CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set # CONFIG_CRYPTO_HW is not set CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM=m diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig index 0ac9e4b3b26525..037eb259ae0cb4 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig @@ -114,6 +114,7 @@ config ARCH_BCM2835 select ARM_ERRATA_411920 select ARM_TIMER_SP804 select CLKSRC_OF + select FIQ select PINCTRL select PINCTRL_BCM2835 help diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c index 1e6f1cf95bf37c..ea36eeca903872 100644 --- a/arch/arm/mach-bcm/board_bcm2835.c +++ b/arch/arm/mach-bcm/board_bcm2835.c @@ -22,6 +22,29 @@ #include #include +/* Use this hack until a proper solution is agreed upon */ +static void __init bcm2835_init_uart1(void) +{ + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart"); + if (of_device_is_available(np)) { + np = of_find_compatible_node(NULL, NULL, + "bcrm,bcm2835-aux-enable"); + if (np) { + void __iomem *base = of_iomap(np, 0); + + if (!base) { + pr_err("bcm2835: Failed enabling Mini UART\n"); + return; + } + + writel(1, base); + pr_info("bcm2835: Mini UART enabled\n"); + } + } +} + static void __init bcm2835_init(void) { struct device_node *np = of_find_node_by_path("/system"); @@ -42,6 +65,8 @@ static void __init bcm2835_init(void) system_rev = val; if (!of_property_read_u64(np, "linux,serial", &val64)) system_serial_low = val64; + + bcm2835_init_uart1(); } static const char * const bcm2835_compat[] = { diff --git a/arch/arm/mach-bcm2708/armctrl.c b/arch/arm/mach-bcm2708/armctrl.c index 0429225d4e32af..16c6746b39ae16 100644 --- a/arch/arm/mach-bcm2708/armctrl.c +++ b/arch/arm/mach-bcm2708/armctrl.c @@ -26,10 +26,22 @@ #include #include +#include #include #include #include "armctrl.h" +/* Mask out shortcut interrupts where they also appear in the regular bank */ +#define BANK0_HWIRQ 0x001ffcff +#define BANK1_HWIRQ BIT(8) +#define BANK2_HWIRQ BIT(9) +#define BANK0_VALID_MASK \ + (BANK0_HWIRQ + BANK1_HWIRQ + BANK2_HWIRQ) +#define BANK1_VALID_MASK \ + (~(BIT(7) | BIT(9) | BIT(10) | BIT(18) | BIT(19))) +#define BANK2_VALID_MASK \ + (~(BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25) | BIT(30))) + /* For support of kernels >= 3.0 assume only one VIC for now*/ static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { INTERRUPT_VC_JPEG, @@ -285,6 +297,59 @@ static struct irq_chip armctrl_chip = { .irq_set_wake = armctrl_set_wake, }; +#ifdef CONFIG_MULTI_IRQ_HANDLER + +static void __exception_irq_entry armctrl_handle_irq( + struct pt_regs *regs) +{ + u32 stat; + + while ((stat = readl_relaxed(__io_address(ARM_IRQ_PEND0)) & + BANK0_VALID_MASK)) { + u32 stat2; + u32 irq; + + if (stat & BANK0_HWIRQ) { + irq = ARM_IRQ0_BASE + ffs(stat & BANK0_HWIRQ) - 1; + } else if (stat & BANK1_HWIRQ) { + stat2 = readl_relaxed(__io_address(ARM_IRQ_PEND1)) & + BANK1_VALID_MASK; + if (stat2) + irq = ARM_IRQ1_BASE + + ffs(stat2 & BANK1_VALID_MASK) - 1; + else + continue; + } else if (stat & BANK2_HWIRQ) { + stat2 = readl_relaxed(__io_address(ARM_IRQ_PEND2)) & + BANK2_VALID_MASK; + if (stat2) + irq = ARM_IRQ2_BASE + + ffs(stat2 & BANK2_VALID_MASK) - 1; + else + continue; + } else { + BUG(); + } + + handle_IRQ(irq, regs); + } +} + +/* This function forces the interrupt numbers to be allocated sequentially, + * instead of with gaps due to the sparse BANK0, to make the offset from + * IRQs and FIQs constant (and equal to FIQ_START). + */ +unsigned int arch_dynirq_lower_bound(unsigned int from) +{ + if (from < 24) + return from + 24; + else if (from >= 104) + return from - 24; + return from; +} + +#endif + /** * armctrl_init - initialise a vectored interrupt controller * @base: iomem base address @@ -308,6 +373,9 @@ int __init armctrl_init(void __iomem * base, unsigned int irq_start, set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } +#ifdef CONFIG_MULTI_IRQ_HANDLER + set_handle_irq(armctrl_handle_irq); +#endif armctrl_pm_register(base, irq_start, resume_sources); init_FIQ(FIQ_START); armctrl_dt_init(); diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c index 39cb7bc9f0a524..5ad4826d0c00dd 100644 --- a/arch/arm/mach-bcm2708/bcm2708.c +++ b/arch/arm/mach-bcm2708/bcm2708.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -101,7 +102,10 @@ static void __init bcm2708_init_led(void); void __init bcm2708_init_irq(void) { - armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); + if (of_have_populated_dt()) + irqchip_init(); + else + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); } static struct map_desc bcm2708_io_desc[] __initdata = { diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 1e164b8a43a4ca..1b193289418344 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -10,7 +10,7 @@ comment "PC SMBus host controller drivers" config I2C_BCM2708 tristate "BCM2708 BSC" - depends on MACH_BCM2708 || MACH_BCM2709 + depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 help Enabling this option will add BSC (Broadcom Serial Controller) support for the BCM2708. BSC is a Broadcom proprietary bus compatible diff --git a/drivers/i2c/busses/i2c-bcm2708.c b/drivers/i2c/busses/i2c-bcm2708.c index 8b8762d89e10fc..5b4fd7b3ba53bc 100644 --- a/drivers/i2c/busses/i2c-bcm2708.c +++ b/drivers/i2c/busses/i2c-bcm2708.c @@ -96,6 +96,9 @@ struct bcm2708_i2c { bool error; }; +#ifdef CONFIG_ARCH_BCM2835 +static void bcm2708_i2c_init_pinmode(int id) { } +#else /* * This function sets the ALT mode on the I2C pins so that we can use them with * the BSC hardware. @@ -123,6 +126,7 @@ static void bcm2708_i2c_init_pinmode(int id) #undef INP_GPIO #undef SET_GPIO_ALT } +#endif static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg) { diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index b8d4e9691890ec..e5e2447ee80584 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -1,6 +1,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o +obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o obj-$(CONFIG_ARCH_MMP) += irq-mmp.o diff --git a/drivers/irqchip/irq-bcm2835.c b/drivers/irqchip/irq-bcm2835.c index e68c3b60a681ba..b1178d4cfd694c 100644 --- a/drivers/irqchip/irq-bcm2835.c +++ b/drivers/irqchip/irq-bcm2835.c @@ -56,7 +56,7 @@ #include "irqchip.h" /* Put the bank and irq (32 bits) into the hwirq */ -#define MAKE_HWIRQ(b, n) ((b << 5) | (n)) +#define MAKE_HWIRQ(b, n) (((b) << 5) | (n)) #define HWIRQ_BANK(i) (i >> 5) #define HWIRQ_BIT(i) BIT(i & 0x1f) @@ -72,9 +72,13 @@ | SHORTCUT1_MASK | SHORTCUT2_MASK) #define REG_FIQ_CONTROL 0x0c +#define REG_FIQ_ENABLE 0x80 +#define REG_FIQ_DISABLE 0 #define NR_BANKS 3 #define IRQS_PER_BANK 32 +#define NUMBER_IRQS MAKE_HWIRQ(NR_BANKS, 0) +#define FIQ_START (NR_IRQS_BANK0 + MAKE_HWIRQ(NR_BANKS - 1, 0)) static int reg_pending[] __initconst = { 0x00, 0x04, 0x08 }; static int reg_enable[] __initconst = { 0x18, 0x10, 0x14 }; @@ -98,14 +102,38 @@ static struct armctrl_ic intc __read_mostly; static void __exception_irq_entry bcm2835_handle_irq( struct pt_regs *regs); +static inline unsigned int hwirq_to_fiq(unsigned long hwirq) +{ + hwirq -= NUMBER_IRQS; + /* + * The hwirq numbering used in this driver is: + * BASE (0-7) GPU1 (32-63) GPU2 (64-95). + * This differ from the one used in the FIQ register: + * GPU1 (0-31) GPU2 (32-63) BASE (64-71) + */ + if (hwirq >= 32) + return hwirq - 32; + + return hwirq + 64; +} + static void armctrl_mask_irq(struct irq_data *d) { - writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); + if (d->hwirq >= NUMBER_IRQS) + writel_relaxed(REG_FIQ_DISABLE, intc.base + REG_FIQ_CONTROL); + else + writel_relaxed(HWIRQ_BIT(d->hwirq), + intc.disable[HWIRQ_BANK(d->hwirq)]); } static void armctrl_unmask_irq(struct irq_data *d) { - writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); + if (d->hwirq >= NUMBER_IRQS) + writel_relaxed(REG_FIQ_ENABLE | hwirq_to_fiq(d->hwirq), + intc.base + REG_FIQ_CONTROL); + else + writel_relaxed(HWIRQ_BIT(d->hwirq), + intc.enable[HWIRQ_BANK(d->hwirq)]); } static struct irq_chip armctrl_chip = { @@ -150,8 +178,9 @@ static int __init armctrl_of_init(struct device_node *node, panic("%s: unable to map IC registers\n", node->full_name); - intc.domain = irq_domain_add_linear(node, MAKE_HWIRQ(NR_BANKS, 0), - &armctrl_ops, NULL); + intc.base = base; + intc.domain = irq_domain_add_linear(node, NUMBER_IRQS * 2, + &armctrl_ops, NULL); if (!intc.domain) panic("%s: unable to create IRQ domain\n", node->full_name); @@ -168,8 +197,20 @@ static int __init armctrl_of_init(struct device_node *node, set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } } - set_handle_irq(bcm2835_handle_irq); + + /* Make a duplicate irq range which is used to enable FIQ */ + for (b = 0; b < NR_BANKS; b++) { + for (i = 0; i < bank_irqs[b]; i++) { + irq = irq_create_mapping(intc.domain, + MAKE_HWIRQ(b, i) + NUMBER_IRQS); + BUG_ON(irq <= 0); + irq_set_chip(irq, &armctrl_chip); + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); + } + } + init_FIQ(FIQ_START); + return 0; } diff --git a/drivers/staging/media/lirc/lirc_rpi.c b/drivers/staging/media/lirc/lirc_rpi.c index 24563ec53b02c9..e1c3cb645af408 100644 --- a/drivers/staging/media/lirc/lirc_rpi.c +++ b/drivers/staging/media/lirc/lirc_rpi.c @@ -39,11 +39,12 @@ #include #include #include -#include #include #include - #include +#ifndef CONFIG_ARCH_BCM2835 +#include +#endif #define LIRC_DRIVER_NAME "lirc_rpi" #define RBUF_LEN 256 @@ -388,6 +389,10 @@ static int init_port(void) } else { +#ifdef CONFIG_ARCH_BCM2835 + ret = -EINVAL; + goto exit_init_port; +#else if (gpio_in_pin >= BCM2708_NR_GPIOS || gpio_out_pin >= BCM2708_NR_GPIOS) { ret = -EINVAL; @@ -413,6 +418,7 @@ static int init_port(void) bcm2708_gpio_setpull(gpiochip, gpio_in_pin, gpio_in_pull); gpiochip->direction_input(gpiochip, gpio_in_pin); gpiochip->direction_output(gpiochip, gpio_out_pin, 1); +#endif } gpiochip->set(gpiochip, gpio_out_pin, invert); diff --git a/drivers/usb/host/dwc_otg/dwc_otg_driver.c b/drivers/usb/host/dwc_otg/dwc_otg_driver.c index 53307f00cffe15..95edadf088cf2a 100644 --- a/drivers/usb/host/dwc_otg/dwc_otg_driver.c +++ b/drivers/usb/host/dwc_otg/dwc_otg_driver.c @@ -723,6 +723,7 @@ static int dwc_otg_driver_probe( memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF; + dwc_otg_device->os_dep.platformdev = _dev; /* * Map the DWC_otg Core memory into virtual address space. diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c index 2c29f7dc380bd1..8db3dfcba4ffb9 100644 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c @@ -36,7 +36,6 @@ #include "dwc_otg_regs.h" #include -#include #include diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c index 0f4ebcd0fdf40d..a331720e6627a4 100644 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c @@ -445,7 +445,16 @@ static void hcd_init_fiq(void *cookie) DWC_WARN("MPHI periph has NOT been enabled"); #endif // Enable FIQ interrupt from USB peripheral - enable_fiq(INTERRUPT_VC_USB); +#ifdef CONFIG_ARCH_BCM2835 + enable_fiq(platform_get_irq(otg_dev->os_dep.platformdev, 1)); +#else +#ifdef CONFIG_MULTI_IRQ_HANDLER + if (otg_dev->os_dep.platformdev->dev.of_node) + enable_fiq(platform_get_irq(otg_dev->os_dep.platformdev, 1)); + else +#endif + enable_fiq(INTERRUPT_VC_USB); +#endif local_fiq_enable(); } diff --git a/drivers/watchdog/bcm2835_wdt.c b/drivers/watchdog/bcm2835_wdt.c index 7116968dee1294..43dbf5b40758aa 100644 --- a/drivers/watchdog/bcm2835_wdt.c +++ b/drivers/watchdog/bcm2835_wdt.c @@ -36,6 +36,13 @@ #define PM_RSTC_WRCFG_FULL_RESET 0x00000020 #define PM_RSTC_RESET 0x00000102 +/* + * The Raspberry Pi firmware uses the RSTS register to know which partiton + * to boot from. The partiton value is spread into bits 0, 2, 4, 6, 8, 10. + * Partiton 63 is a special partition used by the firmware to indicate halt. + */ +#define PM_RSTS_RASPBERRYPI_HALT 0x555 + #define SECS_TO_WDOG_TICKS(x) ((x) << 16) #define WDOG_TICKS_TO_SECS(x) ((x) >> 16) @@ -151,8 +158,7 @@ static void bcm2835_power_off(void) * hard reset. */ val = readl_relaxed(wdt->base + PM_RSTS); - val &= PM_RSTC_WRCFG_CLR; - val |= PM_PASSWORD | PM_RSTS_HADWRH_SET; + val |= PM_PASSWORD | PM_RSTS_RASPBERRYPI_HALT; writel_relaxed(val, wdt->base + PM_RSTS); /* Continue with normal reset mechanism */ diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig index fc151ea4e62caf..257faa78d84cb5 100644 --- a/sound/soc/bcm/Kconfig +++ b/sound/soc/bcm/Kconfig @@ -10,7 +10,7 @@ config SND_BCM2835_SOC_I2S config SND_BCM2708_SOC_I2S tristate "SoC Audio support for the Broadcom BCM2708 I2S module" - depends on MACH_BCM2708 || MACH_BCM2709 + depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835 select REGMAP_MMIO select SND_SOC_DMAENGINE_PCM select SND_SOC_GENERIC_DMAENGINE_PCM diff --git a/sound/soc/bcm/bcm2708-i2s.c b/sound/soc/bcm/bcm2708-i2s.c index 5e93cd64cb0223..ad9ca2c9249558 100644 --- a/sound/soc/bcm/bcm2708-i2s.c +++ b/sound/soc/bcm/bcm2708-i2s.c @@ -40,7 +40,9 @@ #include #include #include +#ifndef CONFIG_ARCH_BCM2835 #include +#endif #include #include @@ -320,6 +322,9 @@ static int bcm2708_i2s_set_dai_bclk_ratio(struct snd_soc_dai *dai, } +#ifdef CONFIG_ARCH_BCM2835 +static void bcm2708_i2s_setup_gpio(void) { } +#else static int bcm2708_i2s_set_function(unsigned offset, int function) { #define GPIOFSEL(x) (0x00+(x)*4) @@ -379,6 +384,7 @@ static void bcm2708_i2s_setup_gpio(void) bcm2708_i2s_set_function(pin, alt); } } +#endif static int bcm2708_i2s_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params,