From 3ac11dcf893a2d41cf08150d93cd9097b68f1dce Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 1 Jun 2016 12:05:35 -0700 Subject: [PATCH 01/16] clk: bcm2835: Mark the CM SDRAM clock's parent as critical While the SDRAM is being driven by its dedicated PLL most of the time, there is a little loop running in the firmware that periodically turns on the CM SDRAM clock (using its pre-initialized parent) and switches SDRAM to using the CM clock to do PVT recalibration. This avoids system hangs if we choose SDRAM's parent for some other clock, then disable that clock. Signed-off-by: Eric Anholt --- drivers/clk/bcm/clk-bcm2835.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 6b6b279a640ae0..4e2b02a6750414 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -36,6 +36,7 @@ #include #include +#include #include #include #include @@ -1839,6 +1840,25 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_PERIICTL), }; +/* + * Permanently take a reference on the parent of the SDRAM clock. + * + * While the SDRAM is being driven by its dedicated PLL most of the + * time, there is a little loop running in the firmware that + * periodically switches the SDRAM to using our CM clock to do PVT + * recalibration, with the assumption that the previously configured + * SDRAM parent is still enabled and running. + */ +static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) +{ + struct clk *parent = clk_get_parent(sdc); + + if (IS_ERR(parent)) + return PTR_ERR(parent); + + return clk_prepare_enable(parent); +} + static int bcm2835_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1848,6 +1868,7 @@ static int bcm2835_clk_probe(struct platform_device *pdev) const struct bcm2835_clk_desc *desc; const size_t asize = ARRAY_SIZE(clk_desc_array); size_t i; + int ret; cprman = devm_kzalloc(dev, sizeof(*cprman) + asize * sizeof(*clks), @@ -1878,6 +1899,10 @@ static int bcm2835_clk_probe(struct platform_device *pdev) clks[i] = desc->clk_register(cprman, desc->data); } + ret = bcm2835_mark_sdc_parent_critical(clks[BCM2835_CLOCK_SDRAM]); + if (ret) + return ret; + return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get, &cprman->onecell); } From 2b8dfa3e9046eb617dbe4a10d863e70cb80a096f Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 31 Mar 2016 12:51:04 -0700 Subject: [PATCH 02/16] clk: bcm2835: Don't rate change PLLs on behalf of dividers. Our core PLLs are intended to be configured once and left alone. With the flag set, asking to set the PLLD_DSI1 clock rate would change PLLD just to get closer to the requested DSI clock, thus changing PLLD_PER, the UART and ethernet PHY clock rates downstream of it, and breaking ethernet. Signed-off-by: Eric Anholt --- drivers/clk/bcm/clk-bcm2835.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 4e2b02a6750414..001cff5625c00f 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1209,7 +1209,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, init.num_parents = 1; init.name = divider_name; init.ops = &bcm2835_pll_divider_clk_ops; - init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; + init.flags = CLK_IGNORE_UNUSED; divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); if (!divider) From bd7c4fa14fac7fff4767c8535e464710b36a7dfa Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 14 Apr 2016 15:13:53 -0700 Subject: [PATCH 03/16] clk: bcm2835: Do appropriate name lookups for DSI1's parents as well. Signed-off-by: Eric Anholt --- .../bindings/clock/brcm,bcm2835-cprman.txt | 12 ++++- drivers/clk/bcm/clk-bcm2835.c | 54 +++++++++++++++---- 2 files changed, 54 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt index e56a1df3a9d3ca..f04e45d3acd555 100644 --- a/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt +++ b/Documentation/devicetree/bindings/clock/brcm,bcm2835-cprman.txt @@ -16,7 +16,17 @@ Required properties: - #clock-cells: Should be <1>. The permitted clock-specifier values can be found in include/dt-bindings/clock/bcm2835.h - reg: Specifies base physical address and size of the registers -- clocks: The external oscillator clock phandle +- clocks: phandles to the parent clocks used as input to the module, in + the following order: + + - External oscillator + - DSI1 byte clock + - DSI1 DDR2 clock + - DSI1 DDR clock + + Only external oscillator is required. The DSI clocks may + not be present, in which case their children will be + unusable. Example: diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 001cff5625c00f..f39722c994f7e2 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -297,11 +297,29 @@ #define LOCK_TIMEOUT_NS 100000000 #define BCM2835_MAX_FB_RATE 1750000000u +/* + * Names of clocks used within the driver that need to be replaced + * with an external parent's name. This array is in the order that + * the clocks node in the DT references external clocks. + */ +static const char *cprman_parent_names[] = { + "xosc", + "dsi1_byte", + "dsi1_ddr2", + "dsi1_ddr", +}; + struct bcm2835_cprman { struct device *dev; void __iomem *regs; spinlock_t regs_lock; /* spinlock for all clocks */ - const char *osc_name; + + /* + * Real names of cprman clock parents looked up through + * of_clk_get_parent_name(), which will be used in the + * parent_names[] arrays for clock registration. + */ + const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)]; struct clk_onecell_data onecell; struct clk *clks[]; @@ -1168,7 +1186,7 @@ static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman, memset(&init, 0, sizeof(init)); /* All of the PLLs derive from the external oscillator. */ - init.parent_names = &cprman->osc_name; + init.parent_names = &cprman->real_parent_names[0]; init.num_parents = 1; init.name = data->name; init.ops = &bcm2835_pll_clk_ops; @@ -1251,17 +1269,21 @@ static struct clk *bcm2835_register_clock(struct bcm2835_cprman *cprman, struct bcm2835_clock *clock; struct clk_init_data init; const char *parents[1 << CM_SRC_BITS]; - size_t i; + size_t i, j; /* - * Replace our "xosc" references with the oscillator's - * actual name. + * Replace our strings referencing parent clocks with the + * actual clock-output-name of the parent. */ for (i = 0; i < data->num_mux_parents; i++) { - if (strcmp(data->parents[i], "xosc") == 0) - parents[i] = cprman->osc_name; - else - parents[i] = data->parents[i]; + parents[i] = data->parents[i]; + + for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) { + if (strcmp(parents[i], cprman_parent_names[j]) == 0) { + parents[i] = cprman->real_parent_names[j]; + break; + } + } } memset(&init, 0, sizeof(init)); @@ -1883,8 +1905,18 @@ static int bcm2835_clk_probe(struct platform_device *pdev) if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); - cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0); - if (!cprman->osc_name) + for (i = 0; i < ARRAY_SIZE(cprman_parent_names); i++) { + cprman->real_parent_names[i] = + of_clk_get_parent_name(dev->of_node, i); + } + /* + * Make sure the external oscillator has been registered. + * + * The other (DSI) clocks are not present on older device + * trees, which we still need to support for backwards + * compatibility. + */ + if (!cprman->real_parent_names[0]) return -ENODEV; platform_set_drvdata(pdev, cprman); From 12262a8a5085c21094f3982d7741e46db8ccdedf Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 14 Apr 2016 19:00:33 -0700 Subject: [PATCH 04/16] clk: bcm2835: Add an enum for the DSI1 pixel clock. Signed-off-by: Eric Anholt --- drivers/clk/bcm/clk-bcm2835.c | 39 +++++++++++++++++++++++++++-- include/dt-bindings/clock/bcm2835.h | 1 + 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index f39722c994f7e2..764b8bf9ca6862 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -934,6 +934,9 @@ static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, const struct bcm2835_clock_data *data = clock->data; u64 temp; + if (data->int_bits == 0 && data->frac_bits == 0) + return parent_rate; + /* * The divisor is a 12.12 fixed point field, but only some of * the bits are populated in any given clock. @@ -957,7 +960,12 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; const struct bcm2835_clock_data *data = clock->data; - u32 div = cprman_read(cprman, data->div_reg); + u32 div; + + if (data->int_bits == 0 && data->frac_bits == 0) + return parent_rate; + + div = cprman_read(cprman, data->div_reg); return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); } @@ -1402,6 +1410,28 @@ static const char *const bcm2835_clock_vpu_parents[] = { .parents = bcm2835_clock_vpu_parents, \ __VA_ARGS__) +/* + * DSI1 parent clocks. The DSI1 byte clock comes from the DSI1 PHY, + * which in turn sources from plld_dsi1. + */ +static const char *const bcm2835_clock_dsi1_parents[] = { + "gnd", + "xosc", + "testdebug0", + "testdebug1", + "dsi1_ddr", + "dsi1_ddr_inv", + "dsi1_ddr2", + "dsi1_ddr2_inv", + "dsi1_byte", + "dsi1_byte_inv", +}; + +#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \ + .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ + .parents = bcm2835_clock_dsi1_parents, \ + __VA_ARGS__) + /* * the real definition of all the pll, pll_dividers and clocks * these make use of the above REGISTER_* macros @@ -1847,7 +1877,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .div_reg = CM_DSI1EDIV, .int_bits = 4, .frac_bits = 8), - + [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( + .name = "dsi1p", + .ctl_reg = CM_DSI1PCTL, + .div_reg = CM_DSI1PDIV, + .int_bits = 0, + .frac_bits = 0), /* the gates */ /* diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h index 360e00cefd3567..c30715a9c56ffe 100644 --- a/include/dt-bindings/clock/bcm2835.h +++ b/include/dt-bindings/clock/bcm2835.h @@ -64,3 +64,4 @@ #define BCM2835_CLOCK_CAM1 46 #define BCM2835_CLOCK_DSI0E 47 #define BCM2835_CLOCK_DSI1E 48 +#define BCM2835_CLOCK_DSI1P 49 From 61f4c8251ecd4c65719c77289fac6f952fe3a84a Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Thu, 14 Jan 2016 16:24:56 +0100 Subject: [PATCH 05/16] drm/fb_cma_helper: Remove implicit call to disable_unused_functions The drm_fbdev_cma_init function always calls the drm_helper_disable_unused_functions. Since it's part of the usual probe process, all the drivers using that helper will end up having their encoder and CRTC disable functions called at probe if their device has not been reported as enabled. This could be fixed by reading out from the registers the current state of the device if it is enabled, but even that will not handle the case where the device is actually disabled. Moreover, the drivers using the atomic modesetting expect that their enable and disable callback to be called when the device is already enabled or disabled (respectively). We can however fix this issue by moving the call to drm_helper_disable_unused_functions out of drm_fbdev_cma_init and make the drivers needing it (all the drivers calling drm_fbdev_cma_init and not using the atomic modesetting) explicitly call it. Signed-off-by: Maxime Ripard Link: http://patchwork.freedesktop.org/patch/msgid/1452785109-6172-14-git-send-email-maxime.ripard@free-electrons.com Acked-by: Laurent Pinchart Signed-off-by: Daniel Vetter (cherry picked from commit 4314e19ef4ae0ba8872bd8610f6fef5e8743e236) --- drivers/gpu/drm/drm_fb_cma_helper.c | 3 --- drivers/gpu/drm/imx/imx-drm-core.c | 1 + drivers/gpu/drm/sti/sti_drv.c | 1 + drivers/gpu/drm/tilcdc/tilcdc_drv.c | 1 + 4 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c index c1a37d334477ed..6349d0c7b5b680 100644 --- a/drivers/gpu/drm/drm_fb_cma_helper.c +++ b/drivers/gpu/drm/drm_fb_cma_helper.c @@ -348,9 +348,6 @@ struct drm_fbdev_cma *drm_fbdev_cma_init(struct drm_device *dev, } - /* disable all the possible outputs/crtcs before entering KMS mode */ - drm_helper_disable_unused_functions(dev); - ret = drm_fb_helper_initial_config(helper, preferred_bpp); if (ret < 0) { dev_err(dev->dev, "Failed to set initial hw configuration.\n"); diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c index 5378bdc3bbf9fc..5f936223e67b9c 100644 --- a/drivers/gpu/drm/imx/imx-drm-core.c +++ b/drivers/gpu/drm/imx/imx-drm-core.c @@ -313,6 +313,7 @@ static int imx_drm_driver_load(struct drm_device *drm, unsigned long flags) dev_warn(drm->dev, "Invalid legacyfb_depth. Defaulting to 16bpp\n"); legacyfb_depth = 16; } + drm_helper_disable_unused_functions(drm); imxdrm->fbhelper = drm_fbdev_cma_init(drm, legacyfb_depth, drm->mode_config.num_crtc, MAX_CRTC); if (IS_ERR(imxdrm->fbhelper)) { diff --git a/drivers/gpu/drm/sti/sti_drv.c b/drivers/gpu/drm/sti/sti_drv.c index 1469987949d88f..506b5626f3ed2e 100644 --- a/drivers/gpu/drm/sti/sti_drv.c +++ b/drivers/gpu/drm/sti/sti_drv.c @@ -160,6 +160,7 @@ static int sti_load(struct drm_device *dev, unsigned long flags) drm_mode_config_reset(dev); + drm_helper_disable_unused_functions(dev); drm_fbdev_cma_init(dev, 32, dev->mode_config.num_crtc, dev->mode_config.num_connector); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index 876cad58b1f9ee..24be31d6970142 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -294,6 +294,7 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags) break; } + drm_helper_disable_unused_functions(dev); priv->fbdev = drm_fbdev_cma_init(dev, bpp, dev->mode_config.num_crtc, dev->mode_config.num_connector); From b36fd0f8f5f7bea870884eadd87a3f68d7de68a0 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 2 Aug 2016 14:16:42 +0200 Subject: [PATCH 06/16] drm/mipi-dsi: Unregister bus at exit This is a preliminary patch for building drm-mipi-dsi as a module. Add the module exit callback to unregister the bus properly. Suggested-by: Thierry Reding Signed-off-by: Takashi Iwai Signed-off-by: Eric Anholt --- drivers/gpu/drm/drm_mipi_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index 2d5ca8eec13a96..b37274e8022016 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -928,6 +928,12 @@ static int __init mipi_dsi_bus_init(void) } postcore_initcall(mipi_dsi_bus_init); +static void __exit mipi_dsi_bus_exit(void) +{ + bus_unregister(&mipi_dsi_bus_type); +} +module_exit(mipi_dsi_bus_exit); + MODULE_AUTHOR("Andrzej Hajda "); MODULE_DESCRIPTION("MIPI DSI Bus"); MODULE_LICENSE("GPL and additional rights"); From 4b7ae430c9ecf788324d6de4d017d9a1d3931be0 Mon Sep 17 00:00:00 2001 From: Takashi Iwai Date: Tue, 2 Aug 2016 14:16:43 +0200 Subject: [PATCH 07/16] drm/mipi-dsi: Allow to build drm-mipi-dsi as a module The drm-mipi-dsi driver has been only built-in although this isn't strictly required to be so. Since it's referred by lots of DRM drivers nowadays, most of distro kernels include the driver as built-in as a result, even though many systems don't need it at all. This patch fixes Kconfig to allow drm-mipi-dsi driver built as a module, so that we can save footprint on systems without such DRM drivers. The probe order is managed by the module dependency, and postcore_initcall() works just fine as a module init call. Signed-off-by: Takashi Iwai Signed-off-by: Eric Anholt --- drivers/gpu/drm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index c4bf9a1cf4a65d..567f95ad86644c 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -22,7 +22,7 @@ menuconfig DRM (/dev/agpgart) support if it is available for your platform. config DRM_MIPI_DSI - bool + tristate depends on DRM config DRM_KMS_HELPER From 804467c4d10f2306a6f928599b277a6d80507219 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 11 Feb 2016 12:29:45 -0800 Subject: [PATCH 08/16] drm/vc4: Fix flipped HVS channels for DSI0/1. Empirically, DSI1 appears to be using HVS channel 0 on my Pi2. Signed-off-by: Eric Anholt --- drivers/gpu/drm/vc4/vc4_crtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 07662bd44bac21..f4044c49780d1f 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -699,13 +699,13 @@ void vc4_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) } static const struct vc4_crtc_data pv0_data = { - .hvs_channel = 0, + .hvs_channel = 2, .encoder0_type = VC4_ENCODER_TYPE_DSI0, .encoder1_type = VC4_ENCODER_TYPE_DPI, }; static const struct vc4_crtc_data pv1_data = { - .hvs_channel = 2, + .hvs_channel = 0, .encoder0_type = VC4_ENCODER_TYPE_DSI1, .encoder1_type = VC4_ENCODER_TYPE_SMI, }; From b5f1d8fd7d213867ed207fd6ab7daeb428ebdb8d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 10 Feb 2016 16:17:29 -0800 Subject: [PATCH 09/16] drm/vc4: Add support for feeding DSI encoders from the pixel valve. Signed-off-by: Eric Anholt --- drivers/gpu/drm/vc4/vc4_crtc.c | 30 +++++++++++++++++------------- drivers/gpu/drm/vc4/vc4_regs.h | 2 ++ 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index f4044c49780d1f..1423b61d3bc1a4 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -210,38 +210,40 @@ static u32 vc4_get_fifo_full_level(u32 format) } /* - * Returns the clock select bit for the connector attached to the - * CRTC. + * Returns the encoder attached to the CRTC. + * + * VC4 can only scan out to one encoder at a type, while the DRM core + * allows drivers to push pixels to more than one encoder from the + * same CRTC. */ -static int vc4_get_clock_select(struct drm_crtc *crtc) +static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) { struct drm_connector *connector; drm_for_each_connector(connector, crtc->dev) { if (connector->state->crtc == crtc) { - struct drm_encoder *encoder = connector->encoder; - struct vc4_encoder *vc4_encoder = - to_vc4_encoder(encoder); - - return vc4_encoder->clock_select; + return connector->encoder; } } - return -1; + return NULL; } static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct vc4_dev *vc4 = to_vc4_dev(dev); + struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); + struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); struct drm_crtc_state *state = crtc->state; struct drm_display_mode *mode = &state->adjusted_mode; bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0)); - u32 format = PV_CONTROL_FORMAT_24; - bool debug_dump_regs = false; - int clock_select = vc4_get_clock_select(crtc); + bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || + vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); + u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; + bool debug_dump_regs = true; if (debug_dump_regs) { DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); @@ -289,6 +291,7 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS | + (is_dsi ? PV_VCONTROL_DSI : 0) | (interlace ? PV_VCONTROL_INTERLACE : 0)); CRTC_WRITE(PV_CONTROL, @@ -298,7 +301,8 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) PV_CONTROL_CLR_AT_START | PV_CONTROL_TRIGGER_UNDERFLOW | PV_CONTROL_WAIT_HSTART | - VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) | + VC4_SET_FIELD(vc4_encoder->clock_select, + PV_CONTROL_CLK_SELECT) | PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h index 6163b95c54111b..7a90bd8a96607a 100644 --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -184,6 +184,8 @@ #define PV_V_CONTROL 0x04 # define PV_VCONTROL_INTERLACE BIT(4) +# define PV_VCONTROL_DSI BIT(3) +# define PV_VCONTROL_COMMAND BIT(2) # define PV_VCONTROL_CONTINUOUS BIT(1) # define PV_VCONTROL_VIDEN BIT(0) From 315305371b5f5b1f162937eef93a1256882e0737 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Fri, 20 May 2016 16:24:47 -0700 Subject: [PATCH 10/16] drm/vc4: Start switching to using debugfs_reg32 helpers for debugfs. Every file was defining its own little struct and dumping for the regs, when there's a helper in debugfs for doing just this. However, instead of printing: PV_HORZA (0x000c): 0x00000000 we now print: PV_HORZA = 0x00000000 Signed-off-by: Eric Anholt --- drivers/gpu/drm/vc4/vc4_crtc.c | 48 +++++++++++++--------------------- drivers/gpu/drm/vc4/vc4_drv.c | 13 +++++++++ drivers/gpu/drm/vc4/vc4_drv.h | 6 +++++ 3 files changed, 37 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 1423b61d3bc1a4..812dfc4df6ef4b 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -35,6 +35,7 @@ #include "drm_atomic_helper.h" #include "drm_crtc_helper.h" #include "linux/clk.h" +#include "linux/debugfs.h" #include "drm_fb_cma_helper.h" #include "linux/component.h" #include "linux/of_device.h" @@ -85,35 +86,25 @@ struct vc4_crtc_data { #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) -#define CRTC_REG(reg) { reg, #reg } -static const struct { - u32 reg; - const char *name; -} crtc_regs[] = { - CRTC_REG(PV_CONTROL), - CRTC_REG(PV_V_CONTROL), - CRTC_REG(PV_VSYNCD_EVEN), - CRTC_REG(PV_HORZA), - CRTC_REG(PV_HORZB), - CRTC_REG(PV_VERTA), - CRTC_REG(PV_VERTB), - CRTC_REG(PV_VERTA_EVEN), - CRTC_REG(PV_VERTB_EVEN), - CRTC_REG(PV_INTEN), - CRTC_REG(PV_INTSTAT), - CRTC_REG(PV_STAT), - CRTC_REG(PV_HACT_ACT), +static const struct debugfs_reg32 crtc_regs[] = { + VC4_DEBUG_REG(PV_CONTROL), + VC4_DEBUG_REG(PV_V_CONTROL), + VC4_DEBUG_REG(PV_VSYNCD_EVEN), + VC4_DEBUG_REG(PV_HORZA), + VC4_DEBUG_REG(PV_HORZB), + VC4_DEBUG_REG(PV_VERTA), + VC4_DEBUG_REG(PV_VERTB), + VC4_DEBUG_REG(PV_VERTA_EVEN), + VC4_DEBUG_REG(PV_VERTB_EVEN), + VC4_DEBUG_REG(PV_INTEN), + VC4_DEBUG_REG(PV_INTSTAT), + VC4_DEBUG_REG(PV_STAT), + VC4_DEBUG_REG(PV_HACT_ACT), }; static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc) { - int i; - - for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { - DRM_INFO("0x%04x (%s): 0x%08x\n", - crtc_regs[i].reg, crtc_regs[i].name, - CRTC_READ(crtc_regs[i].reg)); - } + vc4_dump_regs32(crtc_regs, ARRAY_SIZE(crtc_regs), vc4_crtc->regs, ""); } #ifdef CONFIG_DEBUG_FS @@ -136,11 +127,8 @@ int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused) return 0; vc4_crtc = to_vc4_crtc(crtc); - for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { - seq_printf(m, "%s (0x%04x): 0x%08x\n", - crtc_regs[i].name, crtc_regs[i].reg, - CRTC_READ(crtc_regs[i].reg)); - } + debugfs_print_regs32(m, crtc_regs, ARRAY_SIZE(crtc_regs), + vc4_crtc->regs, ""); return 0; } diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c index 2854ba313a6b8e..8909b6ca7e902d 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.c +++ b/drivers/gpu/drm/vc4/vc4_drv.c @@ -9,6 +9,7 @@ #include #include +#include #include #include #include @@ -52,6 +53,18 @@ static void vc4_drm_preclose(struct drm_device *dev, struct drm_file *file) vc4_cancel_page_flip(crtc, file); } +void vc4_dump_regs32(const struct debugfs_reg32 *regs, unsigned int num_regs, + void __iomem *base, const char *prefix) +{ + unsigned int i; + + for (i = 0; i < num_regs; i++) { + DRM_INFO("%s0x%04lx (%s): 0x%08x\n", + prefix, regs[i].offset, regs[i].name, + readl(base + regs[i].offset)); + } +} + static void vc4_lastclose(struct drm_device *dev) { struct vc4_dev *vc4 = to_vc4_dev(dev); diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 8b381d1716c42f..0f1ce45a7cf0ca 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -9,6 +9,8 @@ #include "drmP.h" #include "drm_gem_cma_helper.h" +struct debugfs_reg32; + struct vc4_dev { struct drm_device *dev; @@ -207,6 +209,8 @@ to_vc4_encoder(struct drm_encoder *encoder) #define HVS_READ(offset) readl(vc4->hvs->regs + offset) #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) +#define VC4_DEBUG_REG(reg) { .name = #reg, .offset = reg } + struct vc4_exec_info { /* Sequence number for this bin/render job. */ uint64_t seqno; @@ -418,6 +422,8 @@ void vc4_debugfs_cleanup(struct drm_minor *minor); /* vc4_drv.c */ void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); +void vc4_dump_regs32(const struct debugfs_reg32 *reg, unsigned int num_regs, + void __iomem *base, const char *prefix); /* vc4_dpi.c */ extern struct platform_driver vc4_dpi_driver; From 4fd38075174d83b6e525859d6aef6befbb6040d4 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 10 Feb 2016 11:42:32 -0800 Subject: [PATCH 11/16] drm/vc4: Add DSI1 driver The DSI0 and DSI1 blocks on the 2835 are different but very similar hardware blocks. Some registers move around, and the featureset is slightly different, but they're clearly related. This doesn't enable DSI0, but some of the infrastructure is present. Also, this driver doesn't initialize the DSI successfully from poweron, so we currently require that the Raspberry Pi firmware enable it at boot time. From there, we just keep the same settings forever, and when poweroff is requested we just scan out black instead. Signed-off-by: Eric Anholt --- drivers/gpu/drm/vc4/Kconfig | 2 + drivers/gpu/drm/vc4/Makefile | 1 + drivers/gpu/drm/vc4/vc4_crtc.c | 41 +- drivers/gpu/drm/vc4/vc4_debugfs.c | 2 + drivers/gpu/drm/vc4/vc4_drv.c | 1 + drivers/gpu/drm/vc4/vc4_drv.h | 8 + drivers/gpu/drm/vc4/vc4_dsi.c | 1737 +++++++++++++++++++++++++++++ 7 files changed, 1780 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/vc4/vc4_dsi.c diff --git a/drivers/gpu/drm/vc4/Kconfig b/drivers/gpu/drm/vc4/Kconfig index 33aa7f5ecb6a5d..19b1ec8a6dfb70 100644 --- a/drivers/gpu/drm/vc4/Kconfig +++ b/drivers/gpu/drm/vc4/Kconfig @@ -6,6 +6,8 @@ config DRM_VC4 select DRM_KMS_CMA_HELPER select DRM_GEM_CMA_HELPER select DRM_PANEL + select DRM_MIPI_DSI + select CLKSRC_OF help Choose this option if you have a system that has a Broadcom VC4 GPU, such as the Raspberry Pi or other BCM2708/BCM2835. diff --git a/drivers/gpu/drm/vc4/Makefile b/drivers/gpu/drm/vc4/Makefile index fb77db755e0a29..b31f25bce239b1 100644 --- a/drivers/gpu/drm/vc4/Makefile +++ b/drivers/gpu/drm/vc4/Makefile @@ -8,6 +8,7 @@ vc4-y := \ vc4_crtc.o \ vc4_drv.o \ vc4_dpi.o \ + vc4_dsi.o \ vc4_kms.o \ vc4_gem.o \ vc4_hdmi.o \ diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 812dfc4df6ef4b..30f64aa47d104a 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -231,7 +231,7 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; - bool debug_dump_regs = true; + bool debug_dump_regs = false; if (debug_dump_regs) { DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); @@ -327,6 +327,19 @@ static void vc4_crtc_disable(struct drm_crtc *crtc) int ret; require_hvs_enabled(dev); + if (VC4_DSI_USE_FIRMWARE_SETUP && + (CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_DSI)) { + /* Skip disabling the PV/HVS for the channel if it was + * connected to the DSI panel and we're using the + * firmware setup. Instead, just set it to stuff + * black in the composite output buffer. + */ + HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), + HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) | + SCALER_DISPBKGND_FILL); + return; + } + CRTC_WRITE(PV_V_CONTROL, CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); @@ -396,17 +409,19 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc, if (drm_atomic_connectors_for_crtc(state->state, crtc) > 1) return -EINVAL; - drm_atomic_crtc_state_for_each_plane(plane, state) { - struct drm_plane_state *plane_state = - state->state->plane_states[drm_plane_index(plane)]; + if (state->active) { + drm_atomic_crtc_state_for_each_plane(plane, state) { + struct drm_plane_state *plane_state = + state->state->plane_states[drm_plane_index(plane)]; - /* plane might not have changed, in which case take - * current state: - */ - if (!plane_state) - plane_state = plane->state; + /* plane might not have changed, in which case take + * current state: + */ + if (!plane_state) + plane_state = plane->state; - dlist_count += vc4_plane_dlist_size(plane_state); + dlist_count += vc4_plane_dlist_size(plane_state); + } } dlist_count++; /* Account for SCALER_CTL0_END. */ @@ -439,8 +454,10 @@ static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, } /* Copy all the active planes' dlist contents to the hardware dlist. */ - drm_atomic_crtc_for_each_plane(plane, crtc) { - dlist_next += vc4_plane_write_dlist(plane, dlist_next); + if (crtc->state->active) { + drm_atomic_crtc_for_each_plane(plane, crtc) { + dlist_next += vc4_plane_write_dlist(plane, dlist_next); + } } writel(SCALER_CTL0_END, dlist_next); diff --git a/drivers/gpu/drm/vc4/vc4_debugfs.c b/drivers/gpu/drm/vc4/vc4_debugfs.c index 94f2154c368525..ac549dd2377cdd 100644 --- a/drivers/gpu/drm/vc4/vc4_debugfs.c +++ b/drivers/gpu/drm/vc4/vc4_debugfs.c @@ -19,6 +19,8 @@ static const struct drm_info_list vc4_debugfs_list[] = { {"bo_stats", vc4_bo_stats_debugfs, 0}, {"dpi_regs", vc4_dpi_debugfs_regs, 0}, {"gem_exec", vc4_gem_exec_debugfs, 0}, + {"dsi0_regs", vc4_dsi_debugfs_regs, 0, (void *)(uintptr_t)0}, + {"dsi1_regs", vc4_dsi_debugfs_regs, 0, (void *)(uintptr_t)1}, {"hdmi_regs", vc4_hdmi_debugfs_regs, 0}, {"hvs_regs", vc4_hvs_debugfs_regs, 0}, {"crtc0_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)0}, diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c index 8909b6ca7e902d..e0e7a099ff06ba 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.c +++ b/drivers/gpu/drm/vc4/vc4_drv.c @@ -294,6 +294,7 @@ static const struct component_master_ops vc4_drm_ops = { static struct platform_driver *const component_drivers[] = { &vc4_hdmi_driver, &vc4_dpi_driver, + &vc4_dsi_driver, &vc4_crtc_driver, &vc4_hvs_driver, &vc4_v3d_driver, diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 0f1ce45a7cf0ca..8571923ef02f30 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -19,6 +19,8 @@ struct vc4_dev { struct vc4_crtc *crtc[3]; struct vc4_v3d *v3d; struct vc4_dpi *dpi; + struct vc4_dsi *dsi0; + struct vc4_dsi *dsi1; struct drm_fbdev_cma *fbdev; struct rpi_firmware *firmware; @@ -192,6 +194,8 @@ enum vc4_encoder_type { VC4_ENCODER_TYPE_DPI, }; +#define VC4_DSI_USE_FIRMWARE_SETUP true + struct vc4_encoder { struct drm_encoder base; enum vc4_encoder_type type; @@ -429,6 +433,10 @@ void vc4_dump_regs32(const struct debugfs_reg32 *reg, unsigned int num_regs, extern struct platform_driver vc4_dpi_driver; int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused); +/* vc4_dsi.c */ +extern struct platform_driver vc4_dsi_driver; +int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused); + /* vc4_gem.c */ void vc4_gem_init(struct drm_device *dev); void vc4_gem_destroy(struct drm_device *dev); diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c new file mode 100644 index 00000000000000..2bce6afe131bb8 --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -0,0 +1,1737 @@ + /* + * Copyright (C) 2016 Broadcom Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +/** + * DOC: VC4 DSI0 module + */ + +#include "drm_atomic_helper.h" +#include "drm_crtc_helper.h" +#include "drm_edid.h" +#include "drm_mipi_dsi.h" +#include "drm_panel.h" +#include "linux/clk.h" +#include "linux/clk-provider.h" +#include "linux/completion.h" +#include "linux/component.h" +#include "linux/debugfs.h" +#include "linux/dmaengine.h" +#include "linux/i2c.h" +#include "linux/of_address.h" +#include "linux/of_gpio.h" +#include "linux/of_platform.h" +#include "vc4_drv.h" +#include "vc4_regs.h" + +#define DSI_CMD_FIFO_DEPTH 16 +#define DSI_PIX_FIFO_DEPTH 256 +#define DSI_PIX_FIFO_WIDTH 4 + +#define DSI0_CTRL 0x00 + +/* Command packet control. */ +#define DSI0_TXPKT1C 0x04 /* AKA PKTC */ +#define DSI1_TXPKT1C 0x04 +# define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24) +# define DSI_TXPKT1C_TRIG_CMD_SHIFT 24 +# define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10) +# define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10 + +# define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8) +# define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8 +/* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */ +# define DSI_TXPKT1C_DISPLAY_NO_SHORT 0 +/* Primary display where cmdfifo provides part of the payload and + * pixelvalve the rest. + */ +# define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1 +/* Secondary display where cmdfifo provides part of the payload and + * pixfifo the rest. + */ +# define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2 + +# define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6) +# define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6 +# define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4) +# define DSI_TXPKT1C_CMD_CTRL_SHIFT 4 +/* Command only. Uses TXPKT1H and DISPLAY_NO */ +# define DSI_TXPKT1C_CMD_CTRL_TX 0 +/* Command with BTA for either ack or read data. */ +# define DSI_TXPKT1C_CMD_CTRL_RX 1 +/* Trigger according to TRIG_CMD */ +# define DSI_TXPKT1C_CMD_CTRL_TRIG 2 +/* BTA alone for getting error status after a command, or a TE trigger + * without a previous command. + */ +# define DSI_TXPKT1C_CMD_CTRL_BTA 3 + +# define DSI_TXPKT1C_CMD_MODE_LP BIT(3) +# define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2) +# define DSI_TXPKT1C_CMD_TE_EN BIT(1) +# define DSI_TXPKT1C_CMD_EN BIT(0) + +/* Command packet header. */ +#define DSI0_TXPKT1H 0x08 /* AKA PKTH */ +#define DSI1_TXPKT1H 0x08 +# define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24) +# define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24 +# define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) +# define DSI_TXPKT1H_BC_PARAM_SHIFT 8 +# define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0) +# define DSI_TXPKT1H_BC_DT_SHIFT 0 + +#define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */ +#define DSI1_RXPKT1H 0x14 +# define DSI_RXPKT1H_CRC_ERR BIT(31) +# define DSI_RXPKT1H_DET_ERR BIT(30) +# define DSI_RXPKT1H_ECC_ERR BIT(29) +# define DSI_RXPKT1H_COR_ERR BIT(28) +# define DSI_RXPKT1H_INCOMP_PKT BIT(25) +# define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24) +/* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */ +# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) +# define DSI_RXPKT1H_BC_PARAM_SHIFT 8 +/* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */ +# define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16) +# define DSI_RXPKT1H_SHORT_1_SHIFT 16 +# define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8) +# define DSI_RXPKT1H_SHORT_0_SHIFT 8 +# define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0) +# define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0 + +#define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */ +#define DSI1_RXPKT2H 0x18 +# define DSI_RXPKT1H_DET_ERR BIT(30) +# define DSI_RXPKT1H_ECC_ERR BIT(29) +# define DSI_RXPKT1H_COR_ERR BIT(28) +# define DSI_RXPKT1H_INCOMP_PKT BIT(25) +# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) +# define DSI_RXPKT1H_BC_PARAM_SHIFT 8 +# define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0) +# define DSI_RXPKT1H_DT_SHIFT 0 + +#define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */ +#define DSI1_TXPKT_CMD_FIFO 0x1c + +#define DSI0_DISP0_CTRL 0x18 +# define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13) +# define DSI_DISP0_PIX_CLK_DIV_SHIFT 13 +# define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11) +# define DSI_DISP0_LP_STOP_CTRL_SHIFT 11 +# define DSI_DISP0_LP_STOP_DISABLE 0 +# define DSI_DISP0_LP_STOP_PERLINE 1 +# define DSI_DISP0_LP_STOP_PERFRAME 2 + +/* Transmit RGB pixels and null packets only during HACTIVE, instead + * of going to LP-STOP. + */ +# define DSI_DISP_HACTIVE_NULL BIT(10) +/* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */ +# define DSI_DISP_VBLP_CTRL BIT(9) +/* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */ +# define DSI_DISP_HFP_CTRL BIT(8) +/* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */ +# define DSI_DISP_HBP_CTRL BIT(7) +# define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5) +# define DSI_DISP0_CHANNEL_SHIFT 5 +/* Enables and end events for HSYNC/VSYNC, not just start events. */ +# define DSI_DISP0_ST_END BIT(4) +# define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2) +# define DSI_DISP0_PFORMAT_SHIFT 2 +# define DSI_PFORMAT_RGB565 0 +# define DSI_PFORMAT_RGB666_PACKED 1 +# define DSI_PFORMAT_RGB666 2 +# define DSI_PFORMAT_RGB888 3 +/* Default is VIDEO mode. */ +# define DSI_DISP0_COMMAND_MODE BIT(1) +# define DSI_DISP0_ENABLE BIT(0) + +#define DSI0_DISP1_CTRL 0x1c +#define DSI1_DISP1_CTRL 0x2c +/* Format of the data written to TXPKT_PIX_FIFO. */ +# define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1) +# define DSI_DISP1_PFORMAT_SHIFT 1 +# define DSI_DISP1_PFORMAT_16BIT 0 +# define DSI_DISP1_PFORMAT_24BIT 1 +# define DSI_DISP1_PFORMAT_32BIT_LE 2 +# define DSI_DISP1_PFORMAT_32BIT_BE 3 + +/* DISP1 is always command mode. */ +# define DSI_DISP1_ENABLE BIT(0) + +#define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */ + +#define DSI0_INT_STAT 0x24 +#define DSI0_INT_EN 0x28 +# define DSI1_INT_PHY_D3_ULPS BIT(30) +# define DSI1_INT_PHY_D3_STOP BIT(29) +# define DSI1_INT_PHY_D2_ULPS BIT(28) +# define DSI1_INT_PHY_D2_STOP BIT(27) +# define DSI1_INT_PHY_D1_ULPS BIT(26) +# define DSI1_INT_PHY_D1_STOP BIT(25) +# define DSI1_INT_PHY_D0_ULPS BIT(24) +# define DSI1_INT_PHY_D0_STOP BIT(23) +# define DSI1_INT_FIFO_ERR BIT(22) +# define DSI1_INT_PHY_DIR_RTF BIT(21) +# define DSI1_INT_PHY_RXLPDT BIT(20) +# define DSI1_INT_PHY_RXTRIG BIT(19) +# define DSI1_INT_PHY_D0_LPDT BIT(18) +# define DSI1_INT_PHY_DIR_FTR BIT(17) + +/* Signaled when the clock lane enters the given state. */ +# define DSI1_INT_PHY_CLOCK_ULPS BIT(16) +# define DSI1_INT_PHY_CLOCK_HS BIT(15) +# define DSI1_INT_PHY_CLOCK_STOP BIT(14) + +/* Signaled on timeouts */ +# define DSI1_INT_PR_TO BIT(13) +# define DSI1_INT_TA_TO BIT(12) +# define DSI1_INT_LPRX_TO BIT(11) +# define DSI1_INT_HSTX_TO BIT(10) + +/* Contention on a line when trying to drive the line low */ +# define DSI1_INT_ERR_CONT_LP1 BIT(9) +# define DSI1_INT_ERR_CONT_LP0 BIT(8) + +/* Control error: incorrect line state sequence on data lane 0. */ +# define DSI1_INT_ERR_CONTROL BIT(7) +/* LPDT synchronization error (bits received not a multiple of 8. */ + +# define DSI1_INT_ERR_SYNC_ESC BIT(6) +/* Signaled after receiving an error packet from the display in + * response to a read. + */ +# define DSI1_INT_RXPKT2 BIT(5) +/* Signaled after receiving a packet. The header and optional short + * response will be in RXPKT1H, and a long response will be in the + * RXPKT_FIFO. + */ +# define DSI1_INT_RXPKT1 BIT(4) +# define DSI1_INT_TXPKT2_DONE BIT(3) +# define DSI1_INT_TXPKT2_END BIT(2) +/* Signaled after all repeats of TXPKT1 are transferred. */ +# define DSI1_INT_TXPKT1_DONE BIT(1) +/* Signaled after each TXPKT1 repeat is scheduled. */ +# define DSI1_INT_TXPKT1_END BIT(0) + +#define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \ + DSI1_INT_ERR_CONTROL | \ + DSI1_INT_ERR_CONT_LP0 | \ + DSI1_INT_ERR_CONT_LP1 | \ + DSI1_INT_HSTX_TO | \ + DSI1_INT_LPRX_TO | \ + DSI1_INT_TA_TO | \ + DSI1_INT_PR_TO) + +#define DSI0_STAT 0x2c +#define DSI0_HSTX_TO_CNT 0x30 +#define DSI0_LPRX_TO_CNT 0x34 +#define DSI0_TA_TO_CNT 0x38 +#define DSI0_PR_TO_CNT 0x3c +#define DSI0_PHYC 0x40 +# define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20) +# define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20 +# define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18) +# define DSI1_PHYC_CLANE_ULPS BIT(17) +# define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12) +# define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12 +# define DSI1_PHYC_CLANE_ENABLE BIT(16) +# define DSI_PHYC_DLANE3_ULPS BIT(13) +# define DSI_PHYC_DLANE3_ENABLE BIT(12) +# define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10) +# define DSI0_PHYC_CLANE_ULPS BIT(9) +# define DSI_PHYC_DLANE2_ULPS BIT(9) +# define DSI0_PHYC_CLANE_ENABLE BIT(8) +# define DSI_PHYC_DLANE2_ENABLE BIT(8) +# define DSI_PHYC_DLANE1_ULPS BIT(5) +# define DSI_PHYC_DLANE1_ENABLE BIT(4) +# define DSI_PHYC_DLANE0_FORCE_STOP BIT(2) +# define DSI_PHYC_DLANE0_ULPS BIT(1) +# define DSI_PHYC_DLANE0_ENABLE BIT(0) + +#define DSI0_HS_CLT0 0x44 +#define DSI0_HS_CLT1 0x48 +#define DSI0_HS_CLT2 0x4c +#define DSI0_HS_DLT3 0x50 +#define DSI0_HS_DLT4 0x54 +#define DSI0_HS_DLT5 0x58 +#define DSI0_HS_DLT6 0x5c +#define DSI0_HS_DLT7 0x60 + +#define DSI0_PHY_AFEC0 0x64 +# define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26) +# define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25) +# define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24) +# define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29) +# define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29 +# define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26) +# define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26 +# define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23) +# define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23 +# define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20) +# define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20 +# define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17) +# define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17 +# define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20) +# define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20 +# define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16) +# define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16 +# define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12) +# define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12 +# define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16) +# define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15) +# define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14) +# define DSI1_PHY_AFEC0_RESET BIT(13) +# define DSI1_PHY_AFEC0_PD BIT(12) +# define DSI0_PHY_AFEC0_RESET BIT(11) +# define DSI1_PHY_AFEC0_PD_BG BIT(11) +# define DSI0_PHY_AFEC0_PD BIT(10) +# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10) +# define DSI0_PHY_AFEC0_PD_BG BIT(9) +# define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9) +# define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8) +# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8) +# define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4) +# define DSI_PHY_AFEC0_PTATADJ_SHIFT 4 +# define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0) +# define DSI_PHY_AFEC0_CTATADJ_SHIFT 0 + +#define DSI0_PHY_AFEC1 0x68 +# define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8) +# define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8 +# define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4) +# define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4 +# define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0) +# define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0 + +#define DSI0_TST_SEL 0x6c +#define DSI0_TST_MON 0x70 +#define DSI0_ID 0x74 +# define DSI_ID_VALUE 0x00647369 + + +#define DSI1_CTRL 0x00 +# define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14) +# define DSI_CTRL_HS_CLKC_SHIFT 14 +# define DSI_CTRL_HS_CLKC_BYTE 0 +# define DSI_CTRL_HS_CLKC_DDR2 1 +# define DSI_CTRL_HS_CLKC_DDR 2 + +# define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13) +# define DSI_CTRL_LPDT_EOT_DISABLE BIT(12) +# define DSI_CTRL_HSDT_EOT_DISABLE BIT(11) +# define DSI_CTRL_SOFT_RESET_CFG BIT(10) +# define DSI_CTRL_CAL_BYTE BIT(9) +# define DSI_CTRL_INV_BYTE BIT(8) +# define DSI_CTRL_CLR_LDF BIT(7) +# define DSI0_CTRL_CLR_PBCF BIT(6) +# define DSI1_CTRL_CLR_RXF BIT(6) +# define DSI0_CTRL_CLR_CPBCF BIT(5) +# define DSI1_CTRL_CLR_PDF BIT(5) +# define DSI0_CTRL_CLR_PDF BIT(4) +# define DSI1_CTRL_CLR_CDF BIT(4) +# define DSI0_CTRL_CLR_CDF BIT(3) +# define DSI0_CTRL_CTRL2 BIT(2) +# define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2) +# define DSI0_CTRL_CTRL1 BIT(1) +# define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1) +# define DSI0_CTRL_CTRL0 BIT(0) +# define DSI1_CTRL_EN BIT(0) +# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \ + DSI0_CTRL_CLR_PBCF | \ + DSI0_CTRL_CLR_CPBCF | \ + DSI0_CTRL_CLR_PDF | \ + DSI0_CTRL_CLR_CDF) +# define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \ + DSI1_CTRL_CLR_RXF | \ + DSI1_CTRL_CLR_PDF | \ + DSI1_CTRL_CLR_CDF) + +#define DSI1_TXPKT2C 0x0c +#define DSI1_TXPKT2H 0x10 +#define DSI1_TXPKT_PIX_FIFO 0x20 +#define DSI1_RXPKT_FIFO 0x24 +#define DSI1_DISP0_CTRL 0x28 +#define DSI1_INT_STAT 0x30 +#define DSI1_INT_EN 0x34 + +/* State reporting bits. These mostly behave like INT_STAT, where + * writing a 1 clears the bit. + */ +#define DSI1_STAT 0x38 +# define DSI1_STAT_PHY_D3_ULPS BIT(31) +# define DSI1_STAT_PHY_D3_STOP BIT(30) +# define DSI1_STAT_PHY_D2_ULPS BIT(29) +# define DSI1_STAT_PHY_D2_STOP BIT(28) +# define DSI1_STAT_PHY_D1_ULPS BIT(27) +# define DSI1_STAT_PHY_D1_STOP BIT(26) +# define DSI1_STAT_PHY_D0_ULPS BIT(25) +# define DSI1_STAT_PHY_D0_STOP BIT(24) +# define DSI1_STAT_FIFO_ERR BIT(23) +# define DSI1_STAT_PHY_RXLPDT BIT(22) +# define DSI1_STAT_PHY_RXTRIG BIT(21) +# define DSI1_STAT_PHY_D0_LPDT BIT(20) +/* Set when in forward direction */ +# define DSI1_STAT_PHY_DIR BIT(19) +# define DSI1_STAT_PHY_CLOCK_ULPS BIT(18) +# define DSI1_STAT_PHY_CLOCK_HS BIT(17) +# define DSI1_STAT_PHY_CLOCK_STOP BIT(16) +# define DSI1_STAT_PR_TO BIT(15) +# define DSI1_STAT_TA_TO BIT(14) +# define DSI1_STAT_LPRX_TO BIT(13) +# define DSI1_STAT_HSTX_TO BIT(12) +# define DSI1_STAT_ERR_CONT_LP1 BIT(11) +# define DSI1_STAT_ERR_CONT_LP0 BIT(10) +# define DSI1_STAT_ERR_CONTROL BIT(9) +# define DSI1_STAT_ERR_SYNC_ESC BIT(8) +# define DSI1_STAT_RXPKT2 BIT(7) +# define DSI1_STAT_RXPKT1 BIT(6) +# define DSI1_STAT_TXPKT2_BUSY BIT(5) +# define DSI1_STAT_TXPKT2_DONE BIT(4) +# define DSI1_STAT_TXPKT2_END BIT(3) +# define DSI1_STAT_TXPKT1_BUSY BIT(2) +# define DSI1_STAT_TXPKT1_DONE BIT(1) +# define DSI1_STAT_TXPKT1_END BIT(0) + +#define DSI1_HSTX_TO_CNT 0x3c +#define DSI1_LPRX_TO_CNT 0x40 +#define DSI1_TA_TO_CNT 0x44 +#define DSI1_PR_TO_CNT 0x48 +#define DSI1_PHYC 0x4c + +#define DSI1_HS_CLT0 0x50 +# define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18) +# define DSI_HS_CLT0_CZERO_SHIFT 18 +# define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9) +# define DSI_HS_CLT0_CPRE_SHIFT 9 +# define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0) +# define DSI_HS_CLT0_CPREP_SHIFT 0 + +#define DSI1_HS_CLT1 0x54 +# define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9) +# define DSI_HS_CLT1_CTRAIL_SHIFT 9 +# define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0) +# define DSI_HS_CLT1_CPOST_SHIFT 0 + +#define DSI1_HS_CLT2 0x58 +# define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0) +# define DSI_HS_CLT2_WUP_SHIFT 0 + +#define DSI1_HS_DLT3 0x5c +# define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18) +# define DSI_HS_DLT3_EXIT_SHIFT 18 +# define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9) +# define DSI_HS_DLT3_ZERO_SHIFT 9 +# define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0) +# define DSI_HS_DLT3_PRE_SHIFT 0 + +#define DSI1_HS_DLT4 0x60 +# define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18) +# define DSI_HS_DLT4_ANLAT_SHIFT 18 +# define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9) +# define DSI_HS_DLT4_TRAIL_SHIFT 9 +# define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0) +# define DSI_HS_DLT4_LPX_SHIFT 0 + +#define DSI1_HS_DLT5 0x64 +# define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0) +# define DSI_HS_DLT5_INIT_SHIFT 0 + +#define DSI1_HS_DLT6 0x68 +# define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24) +# define DSI_HS_DLT6_TA_GET_SHIFT 24 +# define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16) +# define DSI_HS_DLT6_TA_SURE_SHIFT 16 +# define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8) +# define DSI_HS_DLT6_TA_GO_SHIFT 8 +# define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0) +# define DSI_HS_DLT6_LP_LPX_SHIFT 0 + +#define DSI1_HS_DLT7 0x6c +# define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0) +# define DSI_HS_DLT7_LP_WUP_SHIFT 0 + +#define DSI1_PHY_AFEC0 0x70 + +#define DSI1_PHY_AFEC1 0x74 +# define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16) +# define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16 +# define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12) +# define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12 +# define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8) +# define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8 +# define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4) +# define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4 +# define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0) +# define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0 + +#define DSI1_TST_SEL 0x78 +#define DSI1_TST_MON 0x7c +#define DSI1_PHY_TST1 0x80 +#define DSI1_PHY_TST2 0x84 +#define DSI1_PHY_FIFO_STAT 0x88 +/* Actually, all registers in the range that aren't otherwise claimed + * will return the ID. + */ +#define DSI1_ID 0x8c + +/* General DSI hardware state. */ +struct vc4_dsi { + struct platform_device *pdev; + + struct mipi_dsi_host dsi_host; + struct drm_encoder *encoder; + struct drm_connector *connector; + struct drm_panel *panel; + + void __iomem *regs; + + struct dma_chan *reg_dma_chan; + dma_addr_t reg_dma_paddr; + u32 *reg_dma_mem; + dma_addr_t reg_paddr; + + /* Whether we're on bcm2835's DSI0 or DSI1. */ + int port; + + /* DSI channel for the panel we're connected to. */ + u32 channel; + u32 lanes; + enum mipi_dsi_pixel_format format; + u32 mode_flags; + + /* Input clock to the PHY, for the DSI escape clock. */ + struct clk *escape_clock; + + /* Input clock to the PHY, used to generate the DSI bit + * clock. + */ + struct clk *pll_phy_clock; + + /* Byte clock generated within the DSI PHY. */ + struct clk_hw phy_byte_clock; + + struct clk_onecell_data clk_onecell; + + /* Pixel clock output to the pixelvalve, generated from the + * byte clock. + */ + struct clk *pixel_clock; + + struct completion xfer_completion; + int xfer_result; + + bool use_firmware_setup; +}; + +static inline void +dsi_write(struct vc4_dsi *dsi, u32 offset, u32 val) +{ + struct dma_chan *chan = dsi->reg_dma_chan; + struct dma_async_tx_descriptor *tx; + dma_cookie_t cookie; + int ret; + +#if 0 /* XXX */ + dev_info(&dsi->pdev->dev, "WRITE 0x%04x -> 0x%08x\n", offset, val); +#endif + + if (!chan) { + writel(val, dsi->regs + offset); + return; + } + + *dsi->reg_dma_mem = val; + + tx = chan->device->device_prep_dma_memcpy(chan, + dsi->reg_paddr + offset, + dsi->reg_dma_paddr, + 4, 0); + if (!tx) { + DRM_ERROR("Failed to set up DMA register write\n"); + return; + } + + cookie = tx->tx_submit(tx); + ret = dma_submit_error(cookie); + if (ret) { + DRM_ERROR("Failed to submit DMA: %d\n", ret); + return; + } + ret = dma_sync_wait(chan, cookie); + if (ret) + DRM_ERROR("Failed to wait for DMA: %d\n", ret); + +#if 0 /* XXX */ + if (offset != DSI1_TXPKT_CMD_FIFO && + offset != DSI1_TXPKT_PIX_FIFO) { + dev_info(&dsi->pdev->dev, + " -> 0x%08x\n", + readl(dsi->regs + (offset))); + } +#endif +} + +#define DSI_READ(offset) readl(dsi->regs + (offset)) +#define DSI_WRITE(offset, val) dsi_write(dsi, offset, val) +#define DSI_PORT_READ(offset) \ + DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset) +#define DSI_PORT_WRITE(offset, val) \ + DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val) +#define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit) + +/* VC4 DSI encoder KMS struct */ +struct vc4_dsi_encoder { + struct vc4_encoder base; + struct vc4_dsi *dsi; +}; + +static inline struct vc4_dsi_encoder * +to_vc4_dsi_encoder(struct drm_encoder *encoder) +{ + return container_of(encoder, struct vc4_dsi_encoder, base.base); +} +#define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host) + +/* VC4 DSI connector KMS struct */ +struct vc4_dsi_connector { + struct drm_connector base; + struct vc4_dsi *dsi; + + /* Since the connector is attached to just the one encoder, + * this is the reference to it so we can do the best_encoder() + * hook. + */ + struct drm_encoder *encoder; +}; + +static inline struct vc4_dsi_connector * +to_vc4_dsi_connector(struct drm_connector *connector) +{ + return container_of(connector, struct vc4_dsi_connector, base); +} + +static const struct debugfs_reg32 dsi0_regs[] = { + VC4_DEBUG_REG(DSI0_CTRL), + VC4_DEBUG_REG(DSI0_STAT), + VC4_DEBUG_REG(DSI0_DISP0_CTRL), + VC4_DEBUG_REG(DSI0_DISP1_CTRL), + VC4_DEBUG_REG(DSI0_PHYC), + VC4_DEBUG_REG(DSI0_STAT), + VC4_DEBUG_REG(DSI0_HS_CLT0), + VC4_DEBUG_REG(DSI0_HS_CLT1), + VC4_DEBUG_REG(DSI0_HS_CLT2), + VC4_DEBUG_REG(DSI0_HS_DLT3), + VC4_DEBUG_REG(DSI0_HS_DLT4), + VC4_DEBUG_REG(DSI0_HS_DLT5), + VC4_DEBUG_REG(DSI0_HS_DLT6), + VC4_DEBUG_REG(DSI0_HS_DLT7), + VC4_DEBUG_REG(DSI0_PHY_AFEC0), + VC4_DEBUG_REG(DSI0_PHY_AFEC1), + VC4_DEBUG_REG(DSI0_ID), +}; + +static const struct debugfs_reg32 dsi1_regs[] = { + VC4_DEBUG_REG(DSI1_CTRL), + VC4_DEBUG_REG(DSI1_STAT), + VC4_DEBUG_REG(DSI1_DISP0_CTRL), + VC4_DEBUG_REG(DSI1_DISP1_CTRL), + VC4_DEBUG_REG(DSI1_PHYC), + VC4_DEBUG_REG(DSI1_STAT), + VC4_DEBUG_REG(DSI1_HS_CLT0), + VC4_DEBUG_REG(DSI1_HS_CLT1), + VC4_DEBUG_REG(DSI1_HS_CLT2), + VC4_DEBUG_REG(DSI1_HS_DLT3), + VC4_DEBUG_REG(DSI1_HS_DLT4), + VC4_DEBUG_REG(DSI1_HS_DLT5), + VC4_DEBUG_REG(DSI1_HS_DLT6), + VC4_DEBUG_REG(DSI1_HS_DLT7), + VC4_DEBUG_REG(DSI1_PHY_AFEC0), + VC4_DEBUG_REG(DSI1_PHY_AFEC1), + VC4_DEBUG_REG(DSI1_ID), +}; + +static void vc4_dsi_dump_regs(struct vc4_dsi *dsi, const char *prefix) +{ + if (dsi->port == 0) { + vc4_dump_regs32(dsi0_regs, ARRAY_SIZE(dsi0_regs), dsi->regs, + prefix); + } else { + vc4_dump_regs32(dsi1_regs, ARRAY_SIZE(dsi1_regs), dsi->regs, + prefix); + } +} + +#ifdef CONFIG_DEBUG_FS +int vc4_dsi_debugfs_regs(struct seq_file *m, void *number) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + struct vc4_dsi *dsi; + int port = (uintptr_t)number; + + if (port == 0) { + dsi = vc4->dsi0; + debugfs_print_regs32(m, dsi0_regs, ARRAY_SIZE(dsi0_regs), + dsi->regs, ""); + } else { + dsi = vc4->dsi1; + debugfs_print_regs32(m, dsi1_regs, ARRAY_SIZE(dsi1_regs), + dsi->regs, ""); + } + + return 0; +} +#endif + +static enum drm_connector_status +vc4_dsi_connector_detect(struct drm_connector *connector, bool force) +{ + struct vc4_dsi_connector *vc4_connector = + to_vc4_dsi_connector(connector); + struct vc4_dsi *dsi = vc4_connector->dsi; + + if (dsi->panel) + return connector_status_connected; + else + return connector_status_disconnected; +} + +static void vc4_dsi_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); +} + +static int vc4_dsi_connector_get_modes(struct drm_connector *connector) +{ + struct vc4_dsi_connector *vc4_connector = + to_vc4_dsi_connector(connector); + struct vc4_dsi *dsi = vc4_connector->dsi; + + if (dsi->panel) + return drm_panel_get_modes(dsi->panel); + + return 0; +} + +static struct drm_encoder * +vc4_dsi_connector_best_encoder(struct drm_connector *connector) +{ + struct vc4_dsi_connector *dsi_connector = + to_vc4_dsi_connector(connector); + return dsi_connector->encoder; +} + +static const struct drm_connector_funcs vc4_dsi_connector_funcs = { + .dpms = drm_atomic_helper_connector_dpms, + .detect = vc4_dsi_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = vc4_dsi_connector_destroy, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_connector_helper_funcs vc4_dsi_connector_helper_funcs = { + .get_modes = vc4_dsi_connector_get_modes, + .best_encoder = vc4_dsi_connector_best_encoder, +}; + +static struct drm_connector *vc4_dsi_connector_init(struct drm_device *dev, + struct vc4_dsi *dsi) +{ + struct drm_connector *connector = NULL; + struct vc4_dsi_connector *dsi_connector; + int ret = 0; + + dsi_connector = devm_kzalloc(dev->dev, sizeof(*dsi_connector), + GFP_KERNEL); + if (!dsi_connector) { + ret = -ENOMEM; + goto fail; + } + connector = &dsi_connector->base; + + dsi_connector->encoder = dsi->encoder; + dsi_connector->dsi = dsi; + + drm_connector_init(dev, connector, &vc4_dsi_connector_funcs, + DRM_MODE_CONNECTOR_DSI); + drm_connector_helper_add(connector, &vc4_dsi_connector_helper_funcs); + + connector->polled = 0; + connector->interlace_allowed = 0; + connector->doublescan_allowed = 0; + + drm_mode_connector_attach_encoder(connector, dsi->encoder); + + return connector; + + fail: + if (connector) + vc4_dsi_connector_destroy(connector); + + return ERR_PTR(ret); +} + +static void vc4_dsi_encoder_destroy(struct drm_encoder *encoder) +{ + drm_encoder_cleanup(encoder); +} + +static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = { + .destroy = vc4_dsi_encoder_destroy, +}; + +static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch) +{ + u32 afec0 = DSI_PORT_READ(PHY_AFEC0); + + if (latch) + afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); + else + afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); + + DSI_PORT_WRITE(PHY_AFEC0, afec0); +} + +/* Enters or exits Ultra Low Power State. */ +static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps) +{ + u32 phyc_ulps = (DSI_PORT_BIT(PHYC_CLANE_ULPS) | + DSI_PHYC_DLANE0_ULPS | + (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | + (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | + (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); + u32 stat_ulps = (DSI1_STAT_PHY_CLOCK_ULPS | + DSI1_STAT_PHY_D0_ULPS | + (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | + (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | + (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); + u32 stat_stop = (DSI1_STAT_PHY_CLOCK_STOP | + DSI1_STAT_PHY_D0_STOP | + (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | + (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | + (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); + int ret; + + DSI_PORT_WRITE(STAT, stat_ulps); + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps); + ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 20); + if (ret) { + dev_warn(&dsi->pdev->dev, + "Timeout waiting for DSI ULPS entry: STAT 0x%08x", + DSI_PORT_READ(STAT)); + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); + vc4_dsi_latch_ulps(dsi, false); + return; + } + + /* The DSI module can't be disabled while the module is + * generating ULPS state. So, to be able to disable the + * module, we have the AFE latch the ULPS state and continue + * on to having the module enter STOP. + */ + vc4_dsi_latch_ulps(dsi, ulps); + + DSI_PORT_WRITE(STAT, stat_stop); + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); + ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 20); + if (ret) { + dev_warn(&dsi->pdev->dev, + "Timeout waiting for DSI STOP entry: STAT 0x%08x", + DSI_PORT_READ(STAT)); + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); + return; + } +} + +static uint32_t +dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui) +{ + /* The HS timings have to be rounded up to a multiple of 8 + * because we're using the byte clock. + */ + return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8); +} + +/* ESC always runs at 100Mhz. */ +#define ESC_TIME_NS 10 + +static uint32_t +dsi_esc_timing(u32 ns) +{ + return DIV_ROUND_UP(ns, ESC_TIME_NS); +} + +static void vc4_dsi_encoder_disable(struct drm_encoder *encoder) +{ + struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder); + struct vc4_dsi *dsi = vc4_encoder->dsi; + + drm_panel_disable(dsi->panel); + + if (!dsi->use_firmware_setup) + vc4_dsi_ulps(dsi, true); + + drm_panel_unprepare(dsi->panel); + + if (dsi->use_firmware_setup) { + /* Since we're using the firmware setup and aren't + * communicating with the panel to bring the link + * down, we need to just keep the clocks and DSI + * module running. + */ + } else { + clk_disable_unprepare(dsi->pll_phy_clock); + clk_disable_unprepare(dsi->escape_clock); + clk_disable_unprepare(dsi->pixel_clock); + } +} + +static void vc4_dsi_encoder_enable(struct drm_encoder *encoder) +{ + struct drm_display_mode *mode = &encoder->crtc->mode; + struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder); + struct vc4_dsi *dsi = vc4_encoder->dsi; + struct device *dev = &dsi->pdev->dev; + uint32_t format = 0, divider = 0; + bool debug_dump_regs = false; + unsigned long hs_clock; + uint32_t ui_ns; + /* Minimum LP state duration in escape clock cycles. */ + uint32_t lpx = dsi_esc_timing(60); + uint32_t phyc; + int ret; + + ret = drm_panel_prepare(dsi->panel); + if (ret) { + DRM_ERROR("Panel failed to prepare\n"); + return; + } + + if (debug_dump_regs) + vc4_dsi_dump_regs(dsi, "DSI before: "); + + /* XXX */ + if (!dsi->use_firmware_setup) { + ret = clk_set_rate(dsi->pll_phy_clock, 2020000000 / 3); + if (ret) + dev_err(&dsi->pdev->dev, "Failed to set phy clock: %d\n", ret); + dev_info(&dsi->pdev->dev, "Tried to set clock to: %d\n", 2000000000 / 3); + + ret = clk_prepare_enable(dsi->escape_clock); + if (ret) { + DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret); + return; + } + + ret = clk_prepare_enable(dsi->pll_phy_clock); + if (ret) { + DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret); + return; + } + + ret = clk_set_rate(dsi->pixel_clock, mode->clock * 1000); + if (ret) + dev_err(dev, "Failed to set pixel clock: %d\n", ret); + dev_info(&dsi->pdev->dev, "Tried to set pixel clock to: %d\n", mode->clock * 1000); + + ret = clk_prepare_enable(dsi->pixel_clock); + if (ret) { + DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret); + return; + } + } + + hs_clock = clk_get_rate(dsi->pll_phy_clock); + + /* Reset the DSI and all its fifos. */ + if (dsi->port == 0) { + DSI_PORT_WRITE(CTRL, + DSI_CTRL_SOFT_RESET_CFG | + DSI0_CTRL_RESET_FIFOS); + } else { + DSI_PORT_WRITE(CTRL, + DSI_CTRL_SOFT_RESET_CFG | + DSI1_CTRL_RESET_FIFOS); + } + + DSI_PORT_WRITE(CTRL, + DSI_CTRL_HSDT_EOT_DISABLE | + DSI_CTRL_RX_LPDT_EOT_DISABLE); + + switch (dsi->format) { + case MIPI_DSI_FMT_RGB888: + format = DSI_PFORMAT_RGB888; + divider = 24 / dsi->lanes; + break; + case MIPI_DSI_FMT_RGB666: + format = DSI_PFORMAT_RGB666; + divider = 24 / dsi->lanes; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + format = DSI_PFORMAT_RGB666_PACKED; + divider = 18 / dsi->lanes; + break; + case MIPI_DSI_FMT_RGB565: + format = DSI_PFORMAT_RGB565; + divider = 16 / dsi->lanes; + break; + } + + /* Set AFE CTR00/CTR1 to release powerdown of analog. */ + if (dsi->port == 0) { + u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | + VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); + + if (dsi->lanes < 2) + afec0 |= DSI0_PHY_AFEC0_PD_DLANE1; + + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) + afec0 |= DSI0_PHY_AFEC0_RESET; + + DSI_PORT_WRITE(PHY_AFEC0, afec0); + + DSI_PORT_WRITE(PHY_AFEC1, + VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | + VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | + VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); + } else { + u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | + VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) | + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) | + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3)); + + if (dsi->lanes < 4) + afec0 |= DSI1_PHY_AFEC0_PD_DLANE3; + if (dsi->lanes < 3) + afec0 |= DSI1_PHY_AFEC0_PD_DLANE2; + if (dsi->lanes < 2) + afec0 |= DSI1_PHY_AFEC0_PD_DLANE1; + + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) + afec0 |= DSI1_PHY_AFEC0_RESET; + + DSI_PORT_WRITE(PHY_AFEC0, afec0); + + DSI_PORT_WRITE(PHY_AFEC1, 0); + } + + /* How many ns one DSI unit interval is. Note that the clock + * is DDR, so there's an extra divide by 2. + */ + ui_ns = DIV_ROUND_UP(500000000, hs_clock); + + DSI_PORT_WRITE(HS_CLT0, + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0), + DSI_HS_CLT0_CZERO) | + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8), + DSI_HS_CLT0_CPRE) | + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0), + DSI_HS_CLT0_CPREP)); + + DSI_PORT_WRITE(HS_CLT1, + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0), + DSI_HS_CLT1_CTRAIL) | + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52), + DSI_HS_CLT1_CPOST)); + + DSI_PORT_WRITE(HS_CLT2, + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0), + DSI_HS_CLT2_WUP)); + + DSI_PORT_WRITE(HS_DLT3, + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0), + DSI_HS_DLT3_EXIT) | + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6), + DSI_HS_DLT3_ZERO) | + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4), + DSI_HS_DLT3_PRE)); + + DSI_PORT_WRITE(HS_DLT4, + VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0), + DSI_HS_DLT4_LPX) | + VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8), + dsi_hs_timing(ui_ns, 60, 4)), + DSI_HS_DLT4_TRAIL) | + VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); + + DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000, 5000), + DSI_HS_DLT5_INIT)); + + DSI_PORT_WRITE(HS_DLT6, + VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) | + VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) | + VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) | + VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX)); + + DSI_PORT_WRITE(HS_DLT7, + VC4_SET_FIELD(dsi_esc_timing(1000000), + DSI_HS_DLT7_LP_WUP)); + + /* Define EOT PKT in EOT reg. */ + + phyc = (DSI_PHYC_DLANE0_ENABLE | + (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | + (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | + (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | + (dsi->port == 0 ? + VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : + VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)) | + DSI_PORT_BIT(PHYC_CLANE_ENABLE)); + + DSI_PORT_WRITE(CTRL, + DSI_PORT_READ(CTRL) | + DSI_CTRL_CAL_BYTE); + + /* HS timeout in HS clock cycles: disabled. */ + DSI_PORT_WRITE(HSTX_TO_CNT, 0); + /* LP receive timeout in HS clocks. */ + DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff); + /* Bus turnaround timeout */ + DSI_PORT_WRITE(TA_TO_CNT, 100000); + /* Display reset sequence timeout */ + DSI_PORT_WRITE(TA_TO_CNT, 100000); + + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + DSI_PORT_WRITE(DISP0_CTRL, + VC4_SET_FIELD(divider, DSI_DISP0_PIX_CLK_DIV) | + VC4_SET_FIELD(format, DSI_DISP0_PFORMAT) | + VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME, + DSI_DISP0_LP_STOP_CTRL) | + DSI_DISP0_ST_END | + DSI_DISP0_ENABLE); + } else { + DSI_PORT_WRITE(DISP0_CTRL, + DSI_DISP0_COMMAND_MODE | + DSI_DISP0_ENABLE); + } + + /* Set up DISP1 for transferring long command payloads through + * the pixfifo. + */ + DSI_PORT_WRITE(DISP1_CTRL, + VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE, + DSI_DISP1_PFORMAT) | + DSI_DISP1_ENABLE); + + if (!(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) + phyc |= DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS); + + DSI_PORT_WRITE(PHYC, phyc); + + /* Ungate the block. */ + if (dsi->port == 0) + DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0); + else { + DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN); + } + + if (!dsi->use_firmware_setup) + vc4_dsi_ulps(dsi, false); + + if (debug_dump_regs) + vc4_dsi_dump_regs(dsi, "DSI after: "); + + ret = drm_panel_enable(dsi->panel); + if (ret) { + DRM_ERROR("Panel failed to enable\n"); + drm_panel_unprepare(dsi->panel); + return; + } +} + +static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + struct vc4_dsi *dsi = host_to_dsi(host); + struct mipi_dsi_packet packet; + u32 pkth = 0, pktc = 0; + int i, ret; + bool is_long = mipi_dsi_packet_format_is_long(msg->type); + u32 cmd_fifo_len = 0, pix_fifo_len = 0; + + mipi_dsi_create_packet(&packet, msg); + pr_err("DSI host xfer %db, %s\n", + packet.payload_length, + is_long ? "long" : "short"); + + pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT); + pkth |= VC4_SET_FIELD(packet.header[1] | + (packet.header[2] << 8), + DSI_TXPKT1H_BC_PARAM); + if (is_long) { + /* Divide data across the various FIFOs we have available. + * The command FIFO takes byte-oriented data, but is of + * limited size. The pixel FIFO (never actually used for + * pixel data in reality) is word oriented, and substantially + * larger. So, we use the pixel FIFO for most of the data, + * sending the residual bytes in the command FIFO at the start. + * + * With this arrangement, the command FIFO will never get full. + */ + cmd_fifo_len = packet.payload_length % DSI_PIX_FIFO_WIDTH; + pix_fifo_len = ((packet.payload_length - cmd_fifo_len) / + DSI_PIX_FIFO_WIDTH); + + WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH); + + pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO); + } + + if (msg->rx_len) { + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX, + DSI_TXPKT1C_CMD_CTRL); + } else { + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX, + DSI_TXPKT1C_CMD_CTRL); + } + + dev_info(&dsi->pdev->dev, "FIFO setup: %d, %d\n", + cmd_fifo_len, pix_fifo_len); + + for (i = 0; i < cmd_fifo_len; i++) + DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]); + for (i = 0; i < pix_fifo_len; i++) { + const uint8_t *pix = packet.payload + cmd_fifo_len + i * 4; + DSI_PORT_WRITE(TXPKT_PIX_FIFO, + pix[0] | + pix[1] << 8 | + pix[2] << 16 | + pix[3] << 24); + } + + if (msg->flags & MIPI_DSI_MSG_USE_LPM) + pktc |= DSI_TXPKT1C_CMD_MODE_LP; + if (is_long) + pktc |= DSI_TXPKT1C_CMD_TYPE_LONG; + + /* Send one copy of the packet. Larger repeats are used for pixel + * data in command mode. + */ + pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT); + + pktc |= DSI_TXPKT1C_CMD_EN; + if (pix_fifo_len) { + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY, + DSI_TXPKT1C_DISPLAY_NO); + } else { + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT, + DSI_TXPKT1C_DISPLAY_NO); + } + + /* Enable the appropriate interrupt for the transfer completion. */ + dsi->xfer_result = 0; + reinit_completion(&dsi->xfer_completion); + DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF); + if (msg->rx_len) { + DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | + DSI1_INT_PHY_DIR_RTF)); + } else { + DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | + DSI1_INT_TXPKT1_DONE)); + } + + /* Send the packet. */ + DSI_PORT_WRITE(TXPKT1H, pkth); + DSI_PORT_WRITE(TXPKT1C, pktc); + + if (!wait_for_completion_timeout(&dsi->xfer_completion, + msecs_to_jiffies(100))) { + u32 stat = DSI_PORT_READ(STAT); + + dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); + dev_err(&dsi->pdev->dev, "INT_STAT: 0x%08x, STAT: 0x%08x\n", + DSI_PORT_READ(INT_STAT), stat); + + if (stat & DSI1_STAT_TXPKT1_DONE) { + dev_info(&dsi->pdev->dev, + "STAT reports DONE, though.\n"); + ret = 0; + } else { + ret = -ETIMEDOUT; + } + } else { + ret = dsi->xfer_result; + } + + DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); + if (ret) + goto reset_fifo_and_return; + + if (ret == 0 && msg->rx_len) { + u32 rxpkt1h = DSI_PORT_READ(RXPKT1H); + u8 *msg_rx = msg->rx_buf; + + if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) { + u32 rxlen = VC4_GET_FIELD(rxpkt1h, DSI_RXPKT1H_BC_PARAM); + + if (rxlen != msg->rx_len) { + DRM_ERROR("DSI returned %db, expecting %db\n", + rxlen, msg->rx_len); + ret = -ENXIO; + goto reset_fifo_and_return; + } + + for (i = 0; i < msg->rx_len; i++) + msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO); + } else { + /* XXX: AWER */ + + msg_rx[0] = VC4_GET_FIELD(rxpkt1h, + DSI_RXPKT1H_SHORT_0); + if (msg->rx_len > 1) { + msg_rx[1] = VC4_GET_FIELD(rxpkt1h, + DSI_RXPKT1H_SHORT_1); + } + } + } + + return ret; + +reset_fifo_and_return: + DRM_ERROR("DSI TRANSFER failed, resetting: %d\n", ret); + + DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN); + udelay(1); + if (dsi->port == 0) { + DSI_PORT_WRITE(CTRL, + DSI_PORT_READ(CTRL) | DSI0_CTRL_RESET_FIFOS); + } else { + DSI_PORT_WRITE(CTRL, + DSI_PORT_READ(CTRL) | DSI1_CTRL_RESET_FIFOS); + } + + DSI_PORT_WRITE(TXPKT1C, 0); + DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); + + + return ret; +} + +static int vc4_dsi_host_attach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct vc4_dsi *dsi = host_to_dsi(host); + + dsi->lanes = device->lanes; + dsi->channel = device->channel; + dsi->format = device->format; + dsi->mode_flags = device->mode_flags; + + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { + dev_err(&dsi->pdev->dev, + "Only VIDEO mode panels supported currently.\n"); + return 0; + } + + dsi->panel = of_drm_find_panel(device->dev.of_node); + if (dsi->panel) + return drm_panel_attach(dsi->panel, dsi->connector); + + drm_helper_hpd_irq_event(dsi->connector->dev); + + return 0; +} + +static int vc4_dsi_host_detach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct vc4_dsi *dsi = host_to_dsi(host); + + if (dsi->panel) { + int ret = drm_panel_detach(dsi->panel); + if (ret) + return ret; + + dsi->panel = NULL; + } + + drm_helper_hpd_irq_event(dsi->connector->dev); + + return 0; +} + +static const struct mipi_dsi_host_ops vc4_dsi_host_ops = { + .attach = vc4_dsi_host_attach, + .detach = vc4_dsi_host_detach, + .transfer = vc4_dsi_host_transfer, +}; + +static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = { + .disable = vc4_dsi_encoder_disable, + .enable = vc4_dsi_encoder_enable, +}; + +static const struct of_device_id vc4_dsi_dt_match[] = { + { .compatible = "brcm,bcm2835-dsi0", (void *)(uintptr_t)0 }, + { .compatible = "brcm,bcm2835-dsi1", (void *)(uintptr_t)1 }, + {} +}; + +static long vc4_dsi_byte_clock_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return *parent_rate / 8; +} + +static unsigned long vc4_dsi_byte_clock_get_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate / 8; +} + +static int vc4_dsi_byte_clock_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + return 0; +} + +/* The byte clock has *no* ops filled. It's always running when the + * PHY is. + */ +static const struct clk_ops vc4_dsi_byte_clock_ops = { + .recalc_rate = vc4_dsi_byte_clock_get_rate, + .set_rate = vc4_dsi_byte_clock_set_rate, + .round_rate = vc4_dsi_byte_clock_round_rate, +}; + +static void dsi_handle_error(struct vc4_dsi *dsi, + irqreturn_t *ret, u32 stat, u32 bit, + const char *type) +{ + if (!(stat & bit)) + return; + + DRM_ERROR("DSI%d: %s error\n", dsi->port, type); + *ret = IRQ_HANDLED; +} + +static irqreturn_t vc4_dsi_irq_handler(int irq, void *data) +{ + struct vc4_dsi *dsi = data; + u32 stat = DSI_PORT_READ(INT_STAT); + irqreturn_t ret = IRQ_NONE; + + DSI_PORT_WRITE(INT_STAT, stat); + + dsi_handle_error(dsi, &ret, stat, + DSI1_INT_ERR_SYNC_ESC, "LPDT sync"); + dsi_handle_error(dsi, &ret, stat, + DSI1_INT_ERR_CONTROL, "data lane 0 sequence"); + dsi_handle_error(dsi, &ret, stat, + DSI1_INT_ERR_CONT_LP0, "LP0 contention"); + dsi_handle_error(dsi, &ret, stat, + DSI1_INT_ERR_CONT_LP1, "LP1 contention"); + dsi_handle_error(dsi, &ret, stat, + DSI1_INT_HSTX_TO, "HSTX timeout"); + dsi_handle_error(dsi, &ret, stat, + DSI1_INT_LPRX_TO, "LPRX timeout"); + dsi_handle_error(dsi, &ret, stat, + DSI1_INT_TA_TO, "turnaround timeout"); + dsi_handle_error(dsi, &ret, stat, + DSI1_INT_PR_TO, "peripheral reset timeout"); + + if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) { + complete(&dsi->xfer_completion); + ret = IRQ_HANDLED; + } else if (stat & DSI1_INT_HSTX_TO) { + complete(&dsi->xfer_completion); + dsi->xfer_result = -ETIMEDOUT; + ret = IRQ_HANDLED; + } + + return ret; +} + +static int +vc4_dsi_init_phy_byte_clock(struct vc4_dsi *dsi) +{ + struct device *dev = &dsi->pdev->dev; + const char *parent_name = __clk_get_name(dsi->pll_phy_clock); + struct clk_init_data init; + struct clk *clk; + + memset(&init, 0, sizeof(init)); + init.parent_names = &parent_name; + init.num_parents = 1; + if (dsi->port == 1) + init.name = "dsi1_byte"; + else + init.name = "dsi0_byte"; + init.ops = &vc4_dsi_byte_clock_ops; + init.flags = 0; + + dsi->phy_byte_clock.init = &init; + clk = devm_clk_register(dev, &dsi->phy_byte_clock); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + /* Use the onecell provider because we may need to expose the + * DDR and DDR2 clocks at some point, which we'd want to put + * in slots 1 and 2. + */ + dsi->clk_onecell.clk_num = 1; + dsi->clk_onecell.clks = devm_kcalloc(dev, + dsi->clk_onecell.clk_num, + sizeof(*dsi->clk_onecell.clks), + GFP_KERNEL); + if (!dsi->clk_onecell.clks) + return -ENOMEM; + + dsi->clk_onecell.clks[0] = clk; + + return of_clk_add_provider(dev->of_node, + of_clk_src_onecell_get, + &dsi->clk_onecell); +} + +static int vc4_dsi_bind(struct device *dev, struct device *master, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = to_vc4_dev(drm); + struct vc4_dsi *dsi; + struct vc4_dsi_encoder *vc4_dsi_encoder; + const struct of_device_id *match; + dma_cap_mask_t dma_mask; + int ret; + + dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); + if (!dsi) + return -ENOMEM; + + match = of_match_device(vc4_dsi_dt_match, dev); + if (!match) + return -ENODEV; + + dsi->port = (uintptr_t)match->data; + + vc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder), + GFP_KERNEL); + if (!vc4_dsi_encoder) + return -ENOMEM; + vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1; + vc4_dsi_encoder->dsi = dsi; + dsi->encoder = &vc4_dsi_encoder->base.base; + + dsi->pdev = pdev; + dsi->regs = vc4_ioremap_regs(pdev, 0); + if (IS_ERR(dsi->regs)) + return PTR_ERR(dsi->regs); + + if (DSI_PORT_READ(ID) != DSI_ID_VALUE) { + dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n", + DSI_PORT_READ(ID), DSI_ID_VALUE); + return -ENODEV; + } + + if (DSI_PORT_READ(CTRL) == 0) { + dev_info(dev, "DSI not set up by firmware.\n"); + return 0; + } + + /* Set this flag to indicate that we're relying on boot-time + * DSI state and can't successfully reconfigure DSI yet. + */ + dsi->use_firmware_setup = VC4_DSI_USE_FIRMWARE_SETUP; + + if (dsi->use_firmware_setup) { + /* Increment references to the various clocks so that + * they stay always enabled and the clock framework + * doesn't disable their parents. + */ + ret = clk_prepare_enable(dsi->escape_clock); + if (ret) { + DRM_ERROR("Failed to refcount DSI escape clock: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(dsi->pll_phy_clock); + if (ret) { + DRM_ERROR("Failed to refcount DSI PLL: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(dsi->pixel_clock); + if (ret) { + DRM_ERROR("Failed to refcount pixel clock: %d\n", ret); + return ret; + } + } + + /* DSI1 has a broken AXI slave that doesn't respond to writes + * from the ARM. It does handle writes from the DMA engine, + * so set up a channel for talking to it. + */ + if (dsi->port == 1) { + dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, + &dsi->reg_dma_paddr, + GFP_KERNEL); + if (!dsi->reg_dma_mem) { + DRM_ERROR("Failed to get DMA memory\n"); + return -ENOMEM; + } + + dma_cap_zero(dma_mask); + dma_cap_set(DMA_MEMCPY, dma_mask); + dsi->reg_dma_chan = dma_request_channel(dma_mask, NULL, NULL); + if (IS_ERR(dsi->reg_dma_chan)) { + ret = PTR_ERR(dsi->reg_dma_chan); + if (ret != -EPROBE_DEFER) + DRM_ERROR("Failed to get DMA channel: %d\n", + ret); + return ret; + } + + /* Get the physical address of the device's registers. The + * struct resource for the regs gives us the bus address + * instead. + */ + dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, + 0, NULL, NULL)); + } + + init_completion(&dsi->xfer_completion); + /* At startup enable error-reporting interrupts and nothing else. */ + DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); + /* Clear any existing interrupt state. */ + DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT)); + + ret = devm_request_irq(dev, platform_get_irq(pdev, 0), + vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get interrupt: %d\n", ret); + return ret; + } + + dsi->escape_clock = devm_clk_get(dev, "escape"); + if (IS_ERR(dsi->escape_clock)) { + ret = PTR_ERR(dsi->escape_clock); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get escape clock: %d\n", ret); + return ret; + } + + dsi->pll_phy_clock = devm_clk_get(dev, "phy"); + if (IS_ERR(dsi->pll_phy_clock)) { + ret = PTR_ERR(dsi->pll_phy_clock); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get phy clock: %d\n", ret); + return ret; + } + + dsi->pixel_clock = devm_clk_get(dev, "pixel"); + if (IS_ERR(dsi->pixel_clock)) { + ret = PTR_ERR(dsi->pixel_clock); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get pixel clock: %d\n", ret); + return ret; + } + + /* The esc clock rate is supposed to always be 100Mhz. */ + ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); + if (ret) { + dev_err(dev, "Failed to set esc clock: %d\n", ret); + return ret; + } + + ret = vc4_dsi_init_phy_byte_clock(dsi); + if (ret) + return ret; + + if (dsi->port == 1) + vc4->dsi1 = dsi; + + drm_encoder_init(drm, dsi->encoder, &vc4_dsi_encoder_funcs, + DRM_MODE_ENCODER_DSI); + drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs); + + dsi->connector = vc4_dsi_connector_init(drm, dsi); + if (IS_ERR(dsi->connector)) { + ret = PTR_ERR(dsi->connector); + goto err_destroy_encoder; + } + + dsi->dsi_host.ops = &vc4_dsi_host_ops; + dsi->dsi_host.dev = dev; + + mipi_dsi_host_register(&dsi->dsi_host); + + dev_set_drvdata(dev, dsi); + + return 0; + +err_destroy_encoder: + vc4_dsi_encoder_destroy(dsi->encoder); + + return ret; +} + +static void vc4_dsi_unbind(struct device *dev, struct device *master, + void *data) +{ + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = to_vc4_dev(drm); + struct vc4_dsi *dsi = dev_get_drvdata(dev); + + vc4_dsi_connector_destroy(dsi->connector); + vc4_dsi_encoder_destroy(dsi->encoder); + + mipi_dsi_host_unregister(&dsi->dsi_host); + + if (!dsi->use_firmware_setup) { + clk_disable_unprepare(dsi->pll_phy_clock); + clk_disable_unprepare(dsi->escape_clock); + clk_disable_unprepare(dsi->pixel_clock); + } + + if (dsi->port == 1) + vc4->dsi1 = NULL; +} + +static const struct component_ops vc4_dsi_ops = { + .bind = vc4_dsi_bind, + .unbind = vc4_dsi_unbind, +}; + +static int vc4_dsi_dev_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &vc4_dsi_ops); +} + +static int vc4_dsi_dev_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &vc4_dsi_ops); + return 0; +} + +struct platform_driver vc4_dsi_driver = { + .probe = vc4_dsi_dev_probe, + .remove = vc4_dsi_dev_remove, + .driver = { + .name = "vc4_dsi", + .of_match_table = vc4_dsi_dt_match, + }, +}; From 07ca869237609d94047e0973c33ff2060e73c3e2 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 26 Apr 2016 13:46:13 -0700 Subject: [PATCH 12/16] drm/panel: Add support for the Raspberry Pi 7" Touchscreen. Signed-off-by: Eric Anholt --- drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile | 1 + .../drm/panel/panel-raspberrypi-touchscreen.c | 347 ++++++++++++++++++ 3 files changed, 357 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 7d4704b1292b5b..409bd70a7929c8 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -31,6 +31,15 @@ config DRM_PANEL_LG_LG4573 Say Y here if you want to enable support for LG4573 RGB panel. To compile this driver as a module, choose M here. +config DRM_PANEL_RASPBERRYPI_TOUCHSCREEN + tristate "Raspberry Pi 7-inch touchscreen panel" + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for the Raspberry + Pi 7" Touchscreen. To compile this driver as a module, + choose M here. + config DRM_PANEL_SAMSUNG_S6E8AA0 tristate "Samsung S6E8AA0 DSI video mode panel" depends on OF diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index d0f016dd7ddb53..ebb6157d7f34c6 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o obj-$(CONFIG_DRM_PANEL_LG_LG4573) += panel-lg-lg4573.o +obj-$(CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN) += panel-raspberrypi-touchscreen.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_LD9040) += panel-samsung-ld9040.o obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0) += panel-samsung-s6e8aa0.o obj-$(CONFIG_DRM_PANEL_SHARP_LQ101R1SX01) += panel-sharp-lq101r1sx01.o diff --git a/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c new file mode 100644 index 00000000000000..dbc507cf2ef125 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-raspberrypi-touchscreen.c @@ -0,0 +1,347 @@ +/* + * Copyright © 2016 Broadcom Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Portions of this file (derived from panel-simple.c) are: + * + * Copyright (C) 2013, NVIDIA Corporation. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/** + * DOC: Raspberry Pi 7" touchscreen panel driver. + * + * The 7" touchscreen consists of a DPI LCD panel, a Toshiba + * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR + * controlling power management, the LCD PWM, and the touchscreen. + * + * This driver presents this device as a MIPI DSI panel to the DRM + * driver, and should expose the touchscreen as a HID device. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +struct rpi_touchscreen { + struct drm_panel base; + struct mipi_dsi_device *dsi; + struct i2c_client *bridge_i2c; + struct backlight_device *backlight; + + bool prepared; + bool enabled; + + /* Version of the firmware on the bridge chip */ + int atmel_ver; +}; + +static const struct drm_display_mode rpi_touchscreen_modes[] = { + { + /* This is assuming that we'll be running the DSI PLL + * at 2Ghz / 3 (since we only get integer dividers), + * so a pixel clock of 2Ghz / 3 / 8. + */ + .clock = 83333, + .hdisplay = 800, + .hsync_start = 800 + 61, + .hsync_end = 800 + 61 + 2, + .htotal = 800 + 61 + 2 + 44, + .vdisplay = 480, + .vsync_start = 480 + 7, + .vsync_end = 480 + 7 + 2, + .vtotal = 480 + 7 + 2 + 21, + .vrefresh = 60, + }, +}; + +static struct rpi_touchscreen *panel_to_ts(struct drm_panel *panel) +{ + return container_of(panel, struct rpi_touchscreen, base); +} + +struct regdump { + const char *reg; + u32 offset; +}; + +#define REGDUMP(reg) { #reg, reg } + +static int rpi_touchscreen_disable(struct drm_panel *panel) +{ + struct rpi_touchscreen *ts = panel_to_ts(panel); + pr_err("disable\n"); + + if (!ts->enabled) + return 0; + + if (ts->backlight) { + ts->backlight->props.power = FB_BLANK_POWERDOWN; + backlight_update_status(ts->backlight); + } + + ts->enabled = false; + + return 0; +} + +static int rpi_touchscreen_unprepare(struct drm_panel *panel) +{ + struct rpi_touchscreen *ts = panel_to_ts(panel); + + if (!ts->prepared) + return 0; + + ts->prepared = false; + + return 0; +} + +static int rpi_touchscreen_prepare(struct drm_panel *panel) +{ + struct rpi_touchscreen *ts = panel_to_ts(panel); + + if (ts->prepared) + return 0; + + ts->prepared = true; + + return 0; +} + +/* + * Powers on the panel once the DSI link is up. + * + * The TC358762 is run in PLLOFF mode, where it usees the MIPI DSI + * byte clock instead of an external reference clock. This means that + * we need the DSI host to be on and transmitting before we start + * talking to it. + */ +static int rpi_touchscreen_enable(struct drm_panel *panel) +{ + struct rpi_touchscreen *ts = panel_to_ts(panel); + + if (ts->enabled) + return 0; + + if (ts->backlight) { + ts->backlight->props.power = FB_BLANK_UNBLANK; + backlight_update_status(ts->backlight); + } + + ts->enabled = true; + + return 0; +} + +static int rpi_touchscreen_get_modes(struct drm_panel *panel) +{ + struct drm_connector *connector = panel->connector; + struct drm_device *drm = panel->drm; + unsigned int i, num = 0; + + for (i = 0; i < ARRAY_SIZE(rpi_touchscreen_modes); i++) { + const struct drm_display_mode *m = &rpi_touchscreen_modes[i]; + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(drm, m); + if (!mode) { + dev_err(drm->dev, "failed to add mode %ux%u@%u\n", + m->hdisplay, m->vdisplay, m->vrefresh); + continue; + } + + mode->type |= DRM_MODE_TYPE_DRIVER; + + if (i == 0) + mode->type |= DRM_MODE_TYPE_PREFERRED; + + drm_mode_set_name(mode); + + drm_mode_probed_add(connector, mode); + num++; + } + + connector->display_info.bpc = 8; + connector->display_info.width_mm = 217; /* XXX */ + connector->display_info.height_mm = 136; /* XXX */ + + return num; +} + +static int rpi_touchscreen_backlight_update(struct backlight_device *bl) +{ + int brightness = bl->props.brightness; + + if (bl->props.power != FB_BLANK_UNBLANK || + bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK)) + brightness = 0; + + return 0; +} + +static const struct backlight_ops rpi_touchscreen_backlight_ops = { + .update_status = rpi_touchscreen_backlight_update, +}; + +static const struct drm_panel_funcs rpi_touchscreen_funcs = { + .disable = rpi_touchscreen_disable, + .unprepare = rpi_touchscreen_unprepare, + .prepare = rpi_touchscreen_prepare, + .enable = rpi_touchscreen_enable, + .get_modes = rpi_touchscreen_get_modes, +}; + +static struct i2c_client *rpi_touchscreen_get_i2c(struct device *dev, + const char *name) +{ + struct device_node *node; + struct i2c_client *client; + + node = of_parse_phandle(dev->of_node, name, 0); + if (!node) + return ERR_PTR(-ENODEV); + + client = of_find_i2c_device_by_node(node); + + of_node_put(node); + + return client; +} + +static int rpi_touchscreen_dsi_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct rpi_touchscreen *ts; + int ret; + + ts = devm_kzalloc(dev, sizeof(*ts), GFP_KERNEL); + if (!ts) + return -ENOMEM; + + dev_set_drvdata(dev, ts); + + ts->dsi = dsi; + dsi->mode_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE); + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->lanes = 1; + + ts->bridge_i2c = + rpi_touchscreen_get_i2c(dev, "raspberrypi,touchscreen-bridge"); + if (!ts->bridge_i2c) { + ret = -EPROBE_DEFER; + return ret; + } + +#if 0 + ts->backlight = + devm_backlight_device_register(dev, + "raspberrypi-touchscreen-backlight", + dev, ts, + &rpi_touchscreen_backlight_ops, + NULL); + if (IS_ERR(ts->backlight)) { + DRM_ERROR("failed to register backlight\n"); + return PTR_ERR(ts->backlight); + } + ts->backlight->props.max_brightness = RPI_TOUCHSCREEN_MAX_BRIGHTNESS; + ts->backlight->props.brightness = RPI_TOUCHSCREEN_MAX_BRIGHTNESS; +#endif + + drm_panel_init(&ts->base); + ts->base.dev = dev; + ts->base.funcs = &rpi_touchscreen_funcs; + + ret = drm_panel_add(&ts->base); + if (ret < 0) + goto err_release_bridge; + + return mipi_dsi_attach(dsi); + +err_release_bridge: + put_device(&ts->bridge_i2c->dev); + return ret; +} + +static int rpi_touchscreen_dsi_remove(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct rpi_touchscreen *ts = dev_get_drvdata(dev); + int ret; + + ret = mipi_dsi_detach(dsi); + if (ret < 0) { + dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret); + return ret; + } + + drm_panel_detach(&ts->base); + drm_panel_remove(&ts->base); + + put_device(&ts->bridge_i2c->dev); + + return 0; +} + +static void rpi_touchscreen_dsi_shutdown(struct mipi_dsi_device *dsi) +{ + /* XXX: poweroff */ +} + +static const struct of_device_id rpi_touchscreen_of_match[] = { + { .compatible = "raspberrypi,touchscreen" }, + { } /* sentinel */ +}; +MODULE_DEVICE_TABLE(of, rpi_touchscreen_of_match); + +static struct mipi_dsi_driver rpi_touchscreen_driver = { + .driver = { + .name = "raspberrypi-touchscreen", + .of_match_table = rpi_touchscreen_of_match, + }, + .probe = rpi_touchscreen_dsi_probe, + .remove = rpi_touchscreen_dsi_remove, + .shutdown = rpi_touchscreen_dsi_shutdown, +}; +module_mipi_dsi_driver(rpi_touchscreen_driver); + +MODULE_AUTHOR("Eric Anholt "); +MODULE_DESCRIPTION("Raspberry Pi 7-inch touchscreen driver"); +MODULE_LICENSE("GPL v2"); From ba09079bd866ac1c907d10e84abacbcc0eefa76d Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 2 Jun 2016 12:29:45 -0700 Subject: [PATCH 13/16] BCM270X: Add the DSI panel to the defconfig. Signed-off-by: Eric Anholt --- arch/arm/configs/bcm2709_defconfig | 1 + arch/arm/configs/bcmrpi_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig index c6f9ad4814a8dc..3eff0fcd9c5ed1 100644 --- a/arch/arm/configs/bcm2709_defconfig +++ b/arch/arm/configs/bcm2709_defconfig @@ -822,6 +822,7 @@ CONFIG_DRM=m CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_UDL=m CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m CONFIG_DRM_VC4=m CONFIG_FB=y CONFIG_FB_BCM2708=y diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig index 26285ae593bd2f..ae819ab7aa785b 100644 --- a/arch/arm/configs/bcmrpi_defconfig +++ b/arch/arm/configs/bcmrpi_defconfig @@ -814,6 +814,7 @@ CONFIG_DRM=m CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_UDL=m CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m CONFIG_DRM_VC4=m CONFIG_FB=y CONFIG_FB_BCM2708=y From 92b71979bab8eba390b7343c34a9dceed66e471f Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Thu, 2 Jun 2016 15:09:35 -0700 Subject: [PATCH 14/16] BCM270X: Add the DSI and DSI panel nodes to the VC4 overlay. Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm2708_common.dtsi | 24 +++++++++++++++++-- .../boot/dts/overlays/vc4-kms-v3d-overlay.dts | 16 +++++++++++++ 2 files changed, 38 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/bcm2708_common.dtsi b/arch/arm/boot/dts/bcm2708_common.dtsi index 74434b986e3fbb..52d49d3181ce9c 100644 --- a/arch/arm/boot/dts/bcm2708_common.dtsi +++ b/arch/arm/boot/dts/bcm2708_common.dtsi @@ -2,6 +2,7 @@ #include #include "dt-bindings/power/raspberrypi-power.h" #include "dt-bindings/gpio/gpio.h" +#include "dt-bindings/pinctrl/bcm2835.h" #include "skeleton.dtsi" / { @@ -110,9 +111,10 @@ reg = <0x7e101000 0x2000>; /* CPRMAN derives everything from the platform's - * oscillator. + * oscillator except for a few clocks that may + * derive from something else derived from CPRMAN.. */ - clocks = <&clk_osc>; + clocks = <&clk_osc>, <&dsi1 0>, <&dsi1 1>, <&dsi1 2>; status = "disabled"; }; @@ -282,6 +284,24 @@ status = "disabled"; }; + dsi1: dsi@7e700000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + compatible = "brcm,bcm2835-dsi1"; + reg = <0x7e700000 0x8c>; + interrupts = <2 12>; + + clocks = <&cprman BCM2835_PLLD_DSI1>, + <&cprman BCM2835_CLOCK_DSI1E>, + <&cprman BCM2835_CLOCK_DSI1P>; + clock-names = "phy", "escape", "pixel"; + clock-output-names = "dsi1_byte", "dsi1_ddr2", "dsi1_ddr"; + status = "disabled"; + power-domains = <&power RPI_POWER_DOMAIN_DSI1>; + }; + i2c1: i2c@7e804000 { compatible = "brcm,bcm2708-i2c"; reg = <0x7e804000 0x1000>; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts index 4f1cc20f90dc67..a70f2e41369d44 100644 --- a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts +++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts @@ -126,6 +126,22 @@ }; }; + fragment@16 { + target = <&dsi1>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcm,panel = <&pitouchscreen>; + + pitouchscreen: panel { + compatible = "raspberrypi,touchscreen"; + reg = <0>; + }; + }; + }; + __overrides__ { cma-256 = <0>,"+0-1-2-3-4"; cma-192 = <0>,"-0+1-2-3-4"; From 4c4d16a7882ef86005cfadaa84370a8740d47836 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 9 Aug 2016 15:12:06 -0700 Subject: [PATCH 15/16] of: Export of_device_uevent_modalias for DRM_MIPI_DSI. In order to make DSI panel modules able to load automatically, we need to emit the OF modalias uevent so that their MODULE_DEVICE_TABLE(of, ...) can match against it. Signed-off-by: Eric Anholt --- drivers/of/device.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/of/device.c b/drivers/of/device.c index e5f47cec75f34e..58caa267469e7e 100644 --- a/drivers/of/device.c +++ b/drivers/of/device.c @@ -287,3 +287,4 @@ int of_device_uevent_modalias(struct device *dev, struct kobj_uevent_env *env) return 0; } +EXPORT_SYMBOL(of_device_uevent_modalias); From 8018f92e30f152acfa97c56e7719cf039e8732d1 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Tue, 9 Aug 2016 15:13:33 -0700 Subject: [PATCH 16/16] drm: Emit modalias uevents for the DSI devices we create. This gets the Raspberry Pi panel module to automatically load at boot time. Signed-off-by: Eric Anholt --- drivers/gpu/drm/drm_mipi_dsi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index b37274e8022016..fa6cc4de4b4a7d 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -50,6 +50,24 @@ static int mipi_dsi_device_match(struct device *dev, struct device_driver *drv) return of_driver_match_device(dev, drv); } +/** + * Send modalias events when devices are created on the bus, so that + * modules can load automatically. + */ +static int mipi_dsi_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + int rc; + + /* Just do the OF uevent, which emits the compatible string so + * that a MODULE_DEVICE_TABLE(of, ...) works. + */ + rc = of_device_uevent_modalias(dev, env); + if (rc != -ENODEV) + return rc; + + return 0; +} + static const struct dev_pm_ops mipi_dsi_device_pm_ops = { .runtime_suspend = pm_generic_runtime_suspend, .runtime_resume = pm_generic_runtime_resume, @@ -65,6 +83,7 @@ static struct bus_type mipi_dsi_bus_type = { .name = "mipi-dsi", .match = mipi_dsi_device_match, .pm = &mipi_dsi_device_pm_ops, + .uevent = mipi_dsi_uevent, }; static int of_device_match(struct device *dev, void *data)