@@ -246,6 +246,9 @@ static void ep93xx_dma_set_active(struct ep93xx_dma_chan *edmac,
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static struct ep93xx_dma_desc *
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ep93xx_dma_get_active (struct ep93xx_dma_chan * edmac )
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{
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+ if (list_empty (& edmac -> active ))
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+ return NULL ;
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+
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return list_first_entry (& edmac -> active , struct ep93xx_dma_desc , node );
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}
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@@ -263,16 +266,22 @@ ep93xx_dma_get_active(struct ep93xx_dma_chan *edmac)
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*/
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static bool ep93xx_dma_advance_active (struct ep93xx_dma_chan * edmac )
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{
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+ struct ep93xx_dma_desc * desc ;
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+
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list_rotate_left (& edmac -> active );
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if (test_bit (EP93XX_DMA_IS_CYCLIC , & edmac -> flags ))
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return true;
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+ desc = ep93xx_dma_get_active (edmac );
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+ if (!desc )
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+ return false;
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+
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/*
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* If txd.cookie is set it means that we are back in the first
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* descriptor in the chain and hence done with it.
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*/
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- return !ep93xx_dma_get_active ( edmac ) -> txd .cookie ;
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+ return !desc -> txd .cookie ;
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}
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/*
@@ -327,9 +336,15 @@ static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac)
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static void m2p_fill_desc (struct ep93xx_dma_chan * edmac )
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{
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- struct ep93xx_dma_desc * desc = ep93xx_dma_get_active ( edmac ) ;
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+ struct ep93xx_dma_desc * desc ;
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u32 bus_addr ;
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+ desc = ep93xx_dma_get_active (edmac );
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+ if (!desc ) {
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+ dev_warn (chan2dev (edmac ), "M2P: empty descriptor list\n" );
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+ return ;
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+ }
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+
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if (ep93xx_dma_chan_direction (& edmac -> chan ) == DMA_MEM_TO_DEV )
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bus_addr = desc -> src_addr ;
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else
@@ -491,7 +506,13 @@ static void m2m_hw_shutdown(struct ep93xx_dma_chan *edmac)
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static void m2m_fill_desc (struct ep93xx_dma_chan * edmac )
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{
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- struct ep93xx_dma_desc * desc = ep93xx_dma_get_active (edmac );
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+ struct ep93xx_dma_desc * desc ;
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+
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+ desc = ep93xx_dma_get_active (edmac );
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+ if (!desc ) {
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+ dev_warn (chan2dev (edmac ), "M2M: empty descriptor list\n" );
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+ return ;
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+ }
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if (edmac -> buffer == 0 ) {
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writel (desc -> src_addr , edmac -> regs + M2M_SAR_BASE0 );
@@ -669,24 +690,30 @@ static void ep93xx_dma_tasklet(unsigned long data)
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{
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struct ep93xx_dma_chan * edmac = (struct ep93xx_dma_chan * )data ;
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struct ep93xx_dma_desc * desc , * d ;
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- dma_async_tx_callback callback ;
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- void * callback_param ;
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+ dma_async_tx_callback callback = NULL ;
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+ void * callback_param = NULL ;
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LIST_HEAD (list );
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spin_lock_irq (& edmac -> lock );
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+ /*
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+ * If dma_terminate_all() was called before we get to run, the active
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+ * list has become empty. If that happens we aren't supposed to do
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+ * anything more than call ep93xx_dma_advance_work().
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+ */
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desc = ep93xx_dma_get_active (edmac );
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- if (desc -> complete ) {
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- edmac -> last_completed = desc -> txd .cookie ;
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- list_splice_init (& edmac -> active , & list );
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+ if (desc ) {
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+ if (desc -> complete ) {
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+ edmac -> last_completed = desc -> txd .cookie ;
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+ list_splice_init (& edmac -> active , & list );
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+ }
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+ callback = desc -> txd .callback ;
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+ callback_param = desc -> txd .callback_param ;
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}
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spin_unlock_irq (& edmac -> lock );
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/* Pick up the next descriptor from the queue */
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ep93xx_dma_advance_work (edmac );
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- callback = desc -> txd .callback ;
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- callback_param = desc -> txd .callback_param ;
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-
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/* Now we can release all the chained descriptors */
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list_for_each_entry_safe (desc , d , & list , node ) {
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/*
@@ -706,13 +733,22 @@ static void ep93xx_dma_tasklet(unsigned long data)
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static irqreturn_t ep93xx_dma_interrupt (int irq , void * dev_id )
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{
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struct ep93xx_dma_chan * edmac = dev_id ;
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+ struct ep93xx_dma_desc * desc ;
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irqreturn_t ret = IRQ_HANDLED ;
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spin_lock (& edmac -> lock );
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+ desc = ep93xx_dma_get_active (edmac );
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+ if (!desc ) {
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+ dev_warn (chan2dev (edmac ),
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+ "got interrupt while active list is empty\n" );
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+ spin_unlock (& edmac -> lock );
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+ return IRQ_NONE ;
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+ }
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+
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switch (edmac -> edma -> hw_interrupt (edmac )) {
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case INTERRUPT_DONE :
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- ep93xx_dma_get_active ( edmac ) -> complete = true;
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+ desc -> complete = true;
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tasklet_schedule (& edmac -> tasklet );
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break ;
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