diff --git a/examples/tiva-c-connected-launchpad/examples/spi_hello.rs b/examples/tiva-c-connected-launchpad/examples/spi_hello.rs
new file mode 100644
index 0000000..5996df9
--- /dev/null
+++ b/examples/tiva-c-connected-launchpad/examples/spi_hello.rs
@@ -0,0 +1,68 @@
+#![no_std]
+#![no_main]
+
+use panic_halt as _; // you can put a breakpoint on `rust_begin_unwind` to catch panics
+
+use core::fmt::Write;
+use cortex_m_rt::entry;
+use tm4c129x_hal::{self as hal, prelude::*};
+
+#[entry]
+fn main() -> ! {
+    let p = hal::Peripherals::take().unwrap();
+
+    let mut sc = p.SYSCTL.constrain();
+    sc.clock_setup.oscillator = hal::sysctl::Oscillator::Main(
+        hal::sysctl::CrystalFrequency::_16mhz,
+        hal::sysctl::SystemClock::UsePll(hal::sysctl::PllOutputFrequency::_120mhz),
+    );
+    let clocks = sc.clock_setup.freeze();
+
+    let cp = hal::CorePeripherals::take().unwrap();
+    let syst = cp.SYST;
+    let mut delay = hal::delay::Delay::new(syst, &clocks);
+
+    let mut porta = p.GPIO_PORTA_AHB.split(&sc.power_control);
+
+    // Initialise SPI
+    let mut spi = hal::spi::Spi::spi0(
+        p.SSI0,
+        (
+            // CLK
+            porta
+                .pa2
+                .into_af_push_pull::<hal::gpio::AF15>(&mut porta.control),
+            // MISO
+            porta
+                .pa5
+                .into_af_push_pull::<hal::gpio::AF15>(&mut porta.control),
+            // MOSI
+            porta
+                .pa4
+                .into_af_push_pull::<hal::gpio::AF15>(&mut porta.control),
+        ),
+        // Mode
+        hal::spi::MODE_0,
+        // Frequency
+        1_u32.mhz(),
+        // Clock
+        &clocks,
+        // Power Control
+        &sc.power_control,
+    );
+
+    // Initialise CS pin
+    let mut cs = porta
+        .pa3
+        .into_push_pull_output();
+    cs.set_high();
+
+    loop {
+        let message = "Hello, World!";
+        cs.set_low();
+        for c in message.chars() {
+            spi.send(c as u8);
+        }
+        cs.set_high();
+    }
+}
diff --git a/examples/tiva-c-connected-launchpad/examples/uart_hello.rs b/examples/tiva-c-connected-launchpad/examples/uart_hello.rs
new file mode 100644
index 0000000..44ce78c
--- /dev/null
+++ b/examples/tiva-c-connected-launchpad/examples/uart_hello.rs
@@ -0,0 +1,45 @@
+#![no_std]
+#![no_main]
+
+use panic_halt as _; // you can put a breakpoint on `rust_begin_unwind` to catch panics
+
+use core::fmt::Write;
+use cortex_m_rt::entry;
+use tm4c129x_hal::{self as hal, prelude::*};
+
+#[entry]
+fn main() -> ! {
+    let p = hal::Peripherals::take().unwrap();
+
+    let mut sc = p.SYSCTL.constrain();
+    sc.clock_setup.oscillator = hal::sysctl::Oscillator::Main(
+        hal::sysctl::CrystalFrequency::_16mhz,
+        hal::sysctl::SystemClock::UsePll(hal::sysctl::PllOutputFrequency::_120mhz),
+    );
+    let clocks = sc.clock_setup.freeze();
+
+    let mut porta = p.GPIO_PORTA_AHB.split(&sc.power_control);
+
+    // Activate UART
+    let mut uart = hal::serial::Serial::uart0(
+        p.UART0,
+        porta
+            .pa1
+            .into_af_push_pull::<hal::gpio::AF1>(&mut porta.control),
+        porta
+            .pa0
+            .into_af_push_pull::<hal::gpio::AF1>(&mut porta.control),
+        (),
+        (),
+        115200_u32.bps(),
+        hal::serial::NewlineMode::SwapLFtoCRLF,
+        &clocks,
+        &sc.power_control,
+    );
+
+    let mut counter = 0u32;
+    loop {
+        writeln!(uart, "Hello, world! counter={}", counter).unwrap();
+        counter = counter.wrapping_add(1);
+    }
+}
diff --git a/tm4c129x-hal/src/gpio.rs b/tm4c129x-hal/src/gpio.rs
index 19bee11..e9b336c 100644
--- a/tm4c129x-hal/src/gpio.rs
+++ b/tm4c129x-hal/src/gpio.rs
@@ -53,6 +53,30 @@ pub trait GpioExt {
     fn split(self, power_control: &sysctl::PowerControl) -> Self::Parts;
 }
 
+/// Alternate function 11 (type state)
+pub struct AF11;
+impl AlternateFunctionChoice for AF11 {
+    fn number() -> u32 {
+        11
+    }
+}
+
+/// Alternate function 13 (type state)
+pub struct AF13;
+impl AlternateFunctionChoice for AF13 {
+    fn number() -> u32 {
+        13
+    }
+}
+
+/// Alternate function 15 (type state)
+pub struct AF15;
+impl AlternateFunctionChoice for AF15 {
+    fn number() -> u32 {
+        15
+    }
+}
+
 gpio_macro!(tm4c129x, GPIO_PORTA_AHB, gpioa, GpioA, PAx, [
     PA0: (pa0, 0, Tristate),
     PA1: (pa1, 1, Tristate),
diff --git a/tm4c129x-hal/src/lib.rs b/tm4c129x-hal/src/lib.rs
index 562642f..30f3a98 100644
--- a/tm4c129x-hal/src/lib.rs
+++ b/tm4c129x-hal/src/lib.rs
@@ -45,7 +45,7 @@ pub mod hib;
 pub mod i2c;
 pub mod prelude;
 pub mod serial;
-// pub mod spi;
+pub mod spi;
 pub mod sysctl;
 
 use embedded_hal as hal;
diff --git a/tm4c129x-hal/src/spi.rs b/tm4c129x-hal/src/spi.rs
index 0900e85..74c8012 100644
--- a/tm4c129x-hal/src/spi.rs
+++ b/tm4c129x-hal/src/spi.rs
@@ -5,9 +5,12 @@ pub use crate::hal::spi::{Mode, MODE_0, MODE_1, MODE_2, MODE_3};
 use crate::{
     gpio::{
         gpioa::{PA2, PA4, PA5},
-        gpiob::{PB4, PB6, PB7},
-        gpiod::{PD0, PD2, PD3},
-        AlternateFunction, OutputMode, AF1, AF2,
+        gpiob::{PB5},
+        gpiod::{PD0, PD1, PD3},
+        gpioe::{PE4, PE5},
+        // gpiof::{PF0, PF1, PF3},
+        gpioq::{PQ0, PQ2, PQ3},
+        AlternateFunction, OutputMode, AF14, AF15,
     },
     hal::spi::{FullDuplex, Phase, Polarity},
     sysctl::{self, Clocks},
@@ -32,27 +35,32 @@ pub trait SckPin<SPI>: Sealed {}
 pub trait MisoPin<SPI>: Sealed {}
 
 /// MOSI pin
-pub unsafe trait MosiPin<SPI>: Sealed {}
+pub trait MosiPin<SPI>: Sealed {}
 
 // SSI0
-impl<T> SckPin<SSI0> for PA2<AlternateFunction<AF2, T>> where T: OutputMode {}
-impl<T> MisoPin<SSI0> for PA4<AlternateFunction<AF2, T>> where T: OutputMode {}
-impl<T> MosiPin<SSI0> for PA5<AlternateFunction<AF2, T>> where T: OutputMode {}
+impl<T> SckPin<SSI0> for PA2<AlternateFunction<AF15, T>> where T: OutputMode {}
+impl<T> MisoPin<SSI0> for PA5<AlternateFunction<AF15, T>> where T: OutputMode {}
+impl<T> MosiPin<SSI0> for PA4<AlternateFunction<AF15, T>> where T: OutputMode {}
 
 // SSI1
-impl<T> SckPin<SSI1> for PD0<AlternateFunction<AF2, T>> where T: OutputMode {}
-impl<T> MisoPin<SSI1> for PD2<AlternateFunction<AF2, T>> where T: OutputMode {}
-impl<T> MosiPin<SSI1> for PD3<AlternateFunction<AF2, T>> where T: OutputMode {}
+impl<T> SckPin<SSI1> for PB5<AlternateFunction<AF15, T>> where T: OutputMode {}
+impl<T> MisoPin<SSI1> for PE5<AlternateFunction<AF15, T>> where T: OutputMode {}
+impl<T> MosiPin<SSI1> for PE4<AlternateFunction<AF15, T>> where T: OutputMode {}
 
 // SSI2
-impl<T> SckPin<SSI2> for PB4<AlternateFunction<AF2, T>> where T: OutputMode {}
-impl<T> MisoPin<SSI2> for PB6<AlternateFunction<AF2, T>> where T: OutputMode {}
-impl<T> MosiPin<SSI2> for PB7<AlternateFunction<AF2, T>> where T: OutputMode {}
+impl<T> SckPin<SSI2> for PD3<AlternateFunction<AF15, T>> where T: OutputMode {}
+impl<T> MisoPin<SSI2> for PD0<AlternateFunction<AF15, T>> where T: OutputMode {}
+impl<T> MosiPin<SSI2> for PD1<AlternateFunction<AF15, T>> where T: OutputMode {}
 
 // SSI3
-impl<T> SckPin<SSI3> for PD0<AlternateFunction<AF1, T>> where T: OutputMode {}
-impl<T> MisoPin<SSI3> for PD2<AlternateFunction<AF1, T>> where T: OutputMode {}
-impl<T> MosiPin<SSI3> for PD3<AlternateFunction<AF1, T>> where T: OutputMode {}
+impl<T> SckPin<SSI3> for PQ0<AlternateFunction<AF14, T>> where T: OutputMode {}
+impl<T> MisoPin<SSI3> for PQ3<AlternateFunction<AF14, T>> where T: OutputMode {}
+impl<T> MosiPin<SSI3> for PQ2<AlternateFunction<AF14, T>> where T: OutputMode {}
+
+// SSI3 (alt)
+// impl<T> SckPin<SSI3> for PF3<AlternateFunction<AF14, T>> where T: OutputMode {}
+// impl<T> MisoPin<SSI3> for PF0<AlternateFunction<AF14, T>> where T: OutputMode {}
+// impl<T> MosiPin<SSI3> for PF1<AlternateFunction<AF14, T>> where T: OutputMode {}
 
 /// SPI peripheral operating in full duplex master mode
 pub struct Spi<SPI, PINS> {