From 5aeb7b95afd873d478cd8fb95d2ecc6fe7f269f7 Mon Sep 17 00:00:00 2001 From: XLE <38703509+tcaxle@users.noreply.github.com> Date: Thu, 14 Mar 2024 16:30:14 +0000 Subject: [PATCH 1/7] Exported SPI module for TM4C129x --- tm4c129x-hal/src/lib.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tm4c129x-hal/src/lib.rs b/tm4c129x-hal/src/lib.rs index 562642f..30f3a98 100644 --- a/tm4c129x-hal/src/lib.rs +++ b/tm4c129x-hal/src/lib.rs @@ -45,7 +45,7 @@ pub mod hib; pub mod i2c; pub mod prelude; pub mod serial; -// pub mod spi; +pub mod spi; pub mod sysctl; use embedded_hal as hal; From 80a0ee061febefced90e1a8a76343808c6ff2444 Mon Sep 17 00:00:00 2001 From: XLE <38703509+tcaxle@users.noreply.github.com> Date: Thu, 14 Mar 2024 16:47:04 +0000 Subject: [PATCH 2/7] Added AF11,13,15 to GPIO --- tm4c129x-hal/src/gpio.rs | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/tm4c129x-hal/src/gpio.rs b/tm4c129x-hal/src/gpio.rs index 19bee11..e9b336c 100644 --- a/tm4c129x-hal/src/gpio.rs +++ b/tm4c129x-hal/src/gpio.rs @@ -53,6 +53,30 @@ pub trait GpioExt { fn split(self, power_control: &sysctl::PowerControl) -> Self::Parts; } +/// Alternate function 11 (type state) +pub struct AF11; +impl AlternateFunctionChoice for AF11 { + fn number() -> u32 { + 11 + } +} + +/// Alternate function 13 (type state) +pub struct AF13; +impl AlternateFunctionChoice for AF13 { + fn number() -> u32 { + 13 + } +} + +/// Alternate function 15 (type state) +pub struct AF15; +impl AlternateFunctionChoice for AF15 { + fn number() -> u32 { + 15 + } +} + gpio_macro!(tm4c129x, GPIO_PORTA_AHB, gpioa, GpioA, PAx, [ PA0: (pa0, 0, Tristate), PA1: (pa1, 1, Tristate), From eba91eccdcc7be183cfea51e8942fb7193963f60 Mon Sep 17 00:00:00 2001 From: XLE <38703509+tcaxle@users.noreply.github.com> Date: Thu, 14 Mar 2024 16:59:28 +0000 Subject: [PATCH 3/7] Corrected pinout for SPI/SSI ports --- tm4c129x-hal/src/spi.rs | 38 +++++++++++++++++++++++--------------- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/tm4c129x-hal/src/spi.rs b/tm4c129x-hal/src/spi.rs index 0900e85..a59c79b 100644 --- a/tm4c129x-hal/src/spi.rs +++ b/tm4c129x-hal/src/spi.rs @@ -5,9 +5,12 @@ pub use crate::hal::spi::{Mode, MODE_0, MODE_1, MODE_2, MODE_3}; use crate::{ gpio::{ gpioa::{PA2, PA4, PA5}, - gpiob::{PB4, PB6, PB7}, - gpiod::{PD0, PD2, PD3}, - AlternateFunction, OutputMode, AF1, AF2, + gpiob::{PB5}, + gpiod::{PD0, PD1, PD3}, + gpiod::{PE4, PE5}, + // gpiod::{PF0, PF1, PF3}, + gpiod::{PQ0, PQ2, PQ3}, + AlternateFunction, OutputMode, AF14, AF15, }, hal::spi::{FullDuplex, Phase, Polarity}, sysctl::{self, Clocks}, @@ -35,24 +38,29 @@ pub trait MisoPin: Sealed {} pub unsafe trait MosiPin: Sealed {} // SSI0 -impl SckPin for PA2> where T: OutputMode {} -impl MisoPin for PA4> where T: OutputMode {} -impl MosiPin for PA5> where T: OutputMode {} +impl SckPin for PA2> where T: OutputMode {} +impl MisoPin for PA5> where T: OutputMode {} +impl MosiPin for PA4> where T: OutputMode {} // SSI1 -impl SckPin for PD0> where T: OutputMode {} -impl MisoPin for PD2> where T: OutputMode {} -impl MosiPin for PD3> where T: OutputMode {} +impl SckPin for PB5> where T: OutputMode {} +impl MisoPin for PE5> where T: OutputMode {} +impl MosiPin for PE4> where T: OutputMode {} // SSI2 -impl SckPin for PB4> where T: OutputMode {} -impl MisoPin for PB6> where T: OutputMode {} -impl MosiPin for PB7> where T: OutputMode {} +impl SckPin for PD3> where T: OutputMode {} +impl MisoPin for PD0> where T: OutputMode {} +impl MosiPin for PD1> where T: OutputMode {} // SSI3 -impl SckPin for PD0> where T: OutputMode {} -impl MisoPin for PD2> where T: OutputMode {} -impl MosiPin for PD3> where T: OutputMode {} +impl SckPin for PQ0> where T: OutputMode {} +impl MisoPin for PQ3> where T: OutputMode {} +impl MosiPin for PQ2> where T: OutputMode {} + +// SSI3 (alt) +// impl SckPin for PF3> where T: OutputMode {} +// impl MisoPin for PF0> where T: OutputMode {} +// impl MosiPin for PF1> where T: OutputMode {} /// SPI peripheral operating in full duplex master mode pub struct Spi { From 1adc69f98ba640ebf8c8bbc92c68b96d26a9617b Mon Sep 17 00:00:00 2001 From: XLE <38703509+tcaxle@users.noreply.github.com> Date: Thu, 14 Mar 2024 17:05:13 +0000 Subject: [PATCH 4/7] Fixed typo in GPIO uses. --- tm4c129x-hal/src/spi.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tm4c129x-hal/src/spi.rs b/tm4c129x-hal/src/spi.rs index a59c79b..a720e13 100644 --- a/tm4c129x-hal/src/spi.rs +++ b/tm4c129x-hal/src/spi.rs @@ -7,9 +7,9 @@ use crate::{ gpioa::{PA2, PA4, PA5}, gpiob::{PB5}, gpiod::{PD0, PD1, PD3}, - gpiod::{PE4, PE5}, - // gpiod::{PF0, PF1, PF3}, - gpiod::{PQ0, PQ2, PQ3}, + gpioe::{PE4, PE5}, + // gpiof::{PF0, PF1, PF3}, + gpioq::{PQ0, PQ2, PQ3}, AlternateFunction, OutputMode, AF14, AF15, }, hal::spi::{FullDuplex, Phase, Polarity}, From fbe61d107adba846760d07fc9e8da13d491a5575 Mon Sep 17 00:00:00 2001 From: XLE <38703509+tcaxle@users.noreply.github.com> Date: Thu, 14 Mar 2024 17:07:15 +0000 Subject: [PATCH 5/7] Swap MOSI/MISO --- tm4c129x-hal/src/spi.rs | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/tm4c129x-hal/src/spi.rs b/tm4c129x-hal/src/spi.rs index a720e13..7c11f0c 100644 --- a/tm4c129x-hal/src/spi.rs +++ b/tm4c129x-hal/src/spi.rs @@ -39,28 +39,28 @@ pub unsafe trait MosiPin: Sealed {} // SSI0 impl SckPin for PA2> where T: OutputMode {} -impl MisoPin for PA5> where T: OutputMode {} -impl MosiPin for PA4> where T: OutputMode {} +impl MisoPin for PA4> where T: OutputMode {} +impl MosiPin for PA5> where T: OutputMode {} // SSI1 impl SckPin for PB5> where T: OutputMode {} -impl MisoPin for PE5> where T: OutputMode {} -impl MosiPin for PE4> where T: OutputMode {} +impl MisoPin for PE4> where T: OutputMode {} +impl MosiPin for PE5> where T: OutputMode {} // SSI2 impl SckPin for PD3> where T: OutputMode {} -impl MisoPin for PD0> where T: OutputMode {} -impl MosiPin for PD1> where T: OutputMode {} +impl MisoPin for PD1> where T: OutputMode {} +impl MosiPin for PD0> where T: OutputMode {} // SSI3 impl SckPin for PQ0> where T: OutputMode {} -impl MisoPin for PQ3> where T: OutputMode {} -impl MosiPin for PQ2> where T: OutputMode {} +impl MisoPin for PQ2> where T: OutputMode {} +impl MosiPin for PQ3> where T: OutputMode {} // SSI3 (alt) // impl SckPin for PF3> where T: OutputMode {} -// impl MisoPin for PF0> where T: OutputMode {} -// impl MosiPin for PF1> where T: OutputMode {} +// impl MisoPin for PF1> where T: OutputMode {} +// impl MosiPin for PF0> where T: OutputMode {} /// SPI peripheral operating in full duplex master mode pub struct Spi { From 67775484e67aef2cede7d7ed2e0f302b73c501ea Mon Sep 17 00:00:00 2001 From: XLE <38703509+tcaxle@users.noreply.github.com> Date: Thu, 14 Mar 2024 17:13:17 +0000 Subject: [PATCH 6/7] Swapped MISO/MOSI back, removed unsafe from MOSI impp. --- tm4c129x-hal/src/spi.rs | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/tm4c129x-hal/src/spi.rs b/tm4c129x-hal/src/spi.rs index 7c11f0c..74c8012 100644 --- a/tm4c129x-hal/src/spi.rs +++ b/tm4c129x-hal/src/spi.rs @@ -35,32 +35,32 @@ pub trait SckPin: Sealed {} pub trait MisoPin: Sealed {} /// MOSI pin -pub unsafe trait MosiPin: Sealed {} +pub trait MosiPin: Sealed {} // SSI0 impl SckPin for PA2> where T: OutputMode {} -impl MisoPin for PA4> where T: OutputMode {} -impl MosiPin for PA5> where T: OutputMode {} +impl MisoPin for PA5> where T: OutputMode {} +impl MosiPin for PA4> where T: OutputMode {} // SSI1 impl SckPin for PB5> where T: OutputMode {} -impl MisoPin for PE4> where T: OutputMode {} -impl MosiPin for PE5> where T: OutputMode {} +impl MisoPin for PE5> where T: OutputMode {} +impl MosiPin for PE4> where T: OutputMode {} // SSI2 impl SckPin for PD3> where T: OutputMode {} -impl MisoPin for PD1> where T: OutputMode {} -impl MosiPin for PD0> where T: OutputMode {} +impl MisoPin for PD0> where T: OutputMode {} +impl MosiPin for PD1> where T: OutputMode {} // SSI3 impl SckPin for PQ0> where T: OutputMode {} -impl MisoPin for PQ2> where T: OutputMode {} -impl MosiPin for PQ3> where T: OutputMode {} +impl MisoPin for PQ3> where T: OutputMode {} +impl MosiPin for PQ2> where T: OutputMode {} // SSI3 (alt) // impl SckPin for PF3> where T: OutputMode {} -// impl MisoPin for PF1> where T: OutputMode {} -// impl MosiPin for PF0> where T: OutputMode {} +// impl MisoPin for PF0> where T: OutputMode {} +// impl MosiPin for PF1> where T: OutputMode {} /// SPI peripheral operating in full duplex master mode pub struct Spi { From 6d6e416820ca58e3d1bba4137a27cbf883134ede Mon Sep 17 00:00:00 2001 From: xle <38703509+tcaxle@users.noreply.github.com> Date: Fri, 15 Mar 2024 11:50:26 +0000 Subject: [PATCH 7/7] Added SPI Hello World example for Tiva C TM4C129x --- .../examples/spi_hello.rs | 68 +++++++++++++++++++ .../examples/uart_hello.rs | 45 ++++++++++++ 2 files changed, 113 insertions(+) create mode 100644 examples/tiva-c-connected-launchpad/examples/spi_hello.rs create mode 100644 examples/tiva-c-connected-launchpad/examples/uart_hello.rs diff --git a/examples/tiva-c-connected-launchpad/examples/spi_hello.rs b/examples/tiva-c-connected-launchpad/examples/spi_hello.rs new file mode 100644 index 0000000..5996df9 --- /dev/null +++ b/examples/tiva-c-connected-launchpad/examples/spi_hello.rs @@ -0,0 +1,68 @@ +#![no_std] +#![no_main] + +use panic_halt as _; // you can put a breakpoint on `rust_begin_unwind` to catch panics + +use core::fmt::Write; +use cortex_m_rt::entry; +use tm4c129x_hal::{self as hal, prelude::*}; + +#[entry] +fn main() -> ! { + let p = hal::Peripherals::take().unwrap(); + + let mut sc = p.SYSCTL.constrain(); + sc.clock_setup.oscillator = hal::sysctl::Oscillator::Main( + hal::sysctl::CrystalFrequency::_16mhz, + hal::sysctl::SystemClock::UsePll(hal::sysctl::PllOutputFrequency::_120mhz), + ); + let clocks = sc.clock_setup.freeze(); + + let cp = hal::CorePeripherals::take().unwrap(); + let syst = cp.SYST; + let mut delay = hal::delay::Delay::new(syst, &clocks); + + let mut porta = p.GPIO_PORTA_AHB.split(&sc.power_control); + + // Initialise SPI + let mut spi = hal::spi::Spi::spi0( + p.SSI0, + ( + // CLK + porta + .pa2 + .into_af_push_pull::(&mut porta.control), + // MISO + porta + .pa5 + .into_af_push_pull::(&mut porta.control), + // MOSI + porta + .pa4 + .into_af_push_pull::(&mut porta.control), + ), + // Mode + hal::spi::MODE_0, + // Frequency + 1_u32.mhz(), + // Clock + &clocks, + // Power Control + &sc.power_control, + ); + + // Initialise CS pin + let mut cs = porta + .pa3 + .into_push_pull_output(); + cs.set_high(); + + loop { + let message = "Hello, World!"; + cs.set_low(); + for c in message.chars() { + spi.send(c as u8); + } + cs.set_high(); + } +} diff --git a/examples/tiva-c-connected-launchpad/examples/uart_hello.rs b/examples/tiva-c-connected-launchpad/examples/uart_hello.rs new file mode 100644 index 0000000..44ce78c --- /dev/null +++ b/examples/tiva-c-connected-launchpad/examples/uart_hello.rs @@ -0,0 +1,45 @@ +#![no_std] +#![no_main] + +use panic_halt as _; // you can put a breakpoint on `rust_begin_unwind` to catch panics + +use core::fmt::Write; +use cortex_m_rt::entry; +use tm4c129x_hal::{self as hal, prelude::*}; + +#[entry] +fn main() -> ! { + let p = hal::Peripherals::take().unwrap(); + + let mut sc = p.SYSCTL.constrain(); + sc.clock_setup.oscillator = hal::sysctl::Oscillator::Main( + hal::sysctl::CrystalFrequency::_16mhz, + hal::sysctl::SystemClock::UsePll(hal::sysctl::PllOutputFrequency::_120mhz), + ); + let clocks = sc.clock_setup.freeze(); + + let mut porta = p.GPIO_PORTA_AHB.split(&sc.power_control); + + // Activate UART + let mut uart = hal::serial::Serial::uart0( + p.UART0, + porta + .pa1 + .into_af_push_pull::(&mut porta.control), + porta + .pa0 + .into_af_push_pull::(&mut porta.control), + (), + (), + 115200_u32.bps(), + hal::serial::NewlineMode::SwapLFtoCRLF, + &clocks, + &sc.power_control, + ); + + let mut counter = 0u32; + loop { + writeln!(uart, "Hello, world! counter={}", counter).unwrap(); + counter = counter.wrapping_add(1); + } +}