diff --git a/src/registers.rs b/src/registers.rs
index c4cf57f..5c36424 100644
--- a/src/registers.rs
+++ b/src/registers.rs
@@ -53,7 +53,13 @@ mod far_el1;
 mod far_el2;
 mod far_el3;
 mod fp;
+mod hafgrtr_el2;
 mod hcr_el2;
+mod hdfgrtr_el2;
+mod hdfgwtr_el2;
+mod hfgitr_el2;
+mod hfgrtr_el2;
+mod hfgwtr_el2;
 mod hpfar_el2;
 mod icc_ctlr_el1;
 mod icc_sre_el2;
@@ -181,7 +187,13 @@ pub use far_el1::FAR_EL1;
 pub use far_el2::FAR_EL2;
 pub use far_el3::FAR_EL3;
 pub use fp::FP;
+pub use hafgrtr_el2::HAFGRTR_EL2;
 pub use hcr_el2::HCR_EL2;
+pub use hdfgrtr_el2::HDFGRTR_EL2;
+pub use hdfgwtr_el2::HDFGWTR_EL2;
+pub use hfgitr_el2::HFGITR_EL2;
+pub use hfgrtr_el2::HFGRTR_EL2;
+pub use hfgwtr_el2::HFGWTR_EL2;
 pub use hpfar_el2::HPFAR_EL2;
 pub use icc_ctlr_el1::ICC_CTLR_EL1;
 pub use icc_sre_el2::ICC_SRE_EL2;
diff --git a/src/registers/hafgrtr_el2.rs b/src/registers/hafgrtr_el2.rs
new file mode 100644
index 0000000..a62c050
--- /dev/null
+++ b/src/registers/hafgrtr_el2.rs
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2025 by the author(s)
+//
+// Author(s):
+//   - lingfuyi. <lingfuyi@kylinos.cn>
+// https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/HDFGRTR-EL2--Hypervisor-Debug-Fine-Grained-Read-Trap-Register?lang=en
+
+//! Hypervisor Activity Monitors Fine-Grained Read Trap Register - EL2
+//!
+//! Provides controls for traps of MRS reads of Activity Monitors System registers.
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub HAFGRTR_EL2 [
+        // 63-50: RES0, 保留位，写0
+        /// Trap MRS reads of AMEVTYPER115_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER115_EL0 OFFSET(49) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR115_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR115_EL0  OFFSET(48) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER114_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER114_EL0 OFFSET(47) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR114_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR114_EL0  OFFSET(46) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER113_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER113_EL0 OFFSET(45) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR113_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR113_EL0  OFFSET(44) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER112_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER112_EL0 OFFSET(43) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR112_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR112_EL0  OFFSET(42) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER111_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER111_EL0 OFFSET(41) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR111_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR111_EL0  OFFSET(40) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER110_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER110_EL0 OFFSET(39) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR110_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR110_EL0  OFFSET(38) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER19_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER19_EL0  OFFSET(37) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR19_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR19_EL0   OFFSET(36) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER18_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER18_EL0  OFFSET(35) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR18_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR18_EL0   OFFSET(34) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER17_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER17_EL0  OFFSET(33) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR17_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR17_EL0   OFFSET(32) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER16_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER16_EL0  OFFSET(31) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR16_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR16_EL0   OFFSET(30) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER15_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER15_EL0  OFFSET(29) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR15_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR15_EL0   OFFSET(28) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER14_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER14_EL0  OFFSET(27) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR14_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR14_EL0   OFFSET(26) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER13_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER13_EL0  OFFSET(25) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR13_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR13_EL0   OFFSET(24) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER12_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER12_EL0  OFFSET(23) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR12_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR12_EL0   OFFSET(22) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER11_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER11_EL0  OFFSET(21) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR11_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR11_EL0   OFFSET(20) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVTYPER10_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVTYPER10_EL0  OFFSET(19) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR10_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR10_EL0   OFFSET(18) NUMBITS(1) [],
+        /// Trap MRS reads of AMCNTEN1 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMCNTEN1        OFFSET(17) NUMBITS(1) [],
+        // 16-5: RES0, 保留位，写0
+        /// Trap MRS reads of AMEVCNTR03_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR03_EL0  OFFSET(4) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR02_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR02_EL0  OFFSET(3) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR01_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR01_EL0  OFFSET(2) NUMBITS(1) [],
+        /// Trap MRS reads of AMEVCNTR00_EL0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMEVCNTR00_EL0  OFFSET(1) NUMBITS(1) [],
+        /// Trap MRS reads of AMCNTEN0 at EL1/EL0 using AArch64 or MRC at EL0 using AArch32 to EL2.
+        AMCNTEN0        OFFSET(0) NUMBITS(1) [],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = HAFGRTR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "S3_4_C3_C1_6", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = HAFGRTR_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "S3_4_C3_C1_6", "x");
+}
+
+pub const HAFGRTR_EL2: Reg = Reg {};
diff --git a/src/registers/hdfgrtr_el2.rs b/src/registers/hdfgrtr_el2.rs
new file mode 100644
index 0000000..6874607
--- /dev/null
+++ b/src/registers/hdfgrtr_el2.rs
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2025 by the author(s)
+//
+// Author(s):
+//   - lingfuyi. <lingfuyi@kylinos.cn>
+// https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/HDFGRTR-EL2--Hypervisor-Debug-Fine-Grained-Read-Trap-Register?lang=en
+
+//! Hypervisor Debug Fine-Grained Read Trap Register - EL2
+//!
+//! Provides controls for traps of MRS and MRC reads of debug, trace, PMU, and Statistical Profiling
+//! System registers.
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub HDFGRTR_EL2 [
+        /// Trap MRS reads of PMBIDR_EL1 at EL1 using AArch64 to EL2.
+        PMBIDR_EL1      OFFSET(63) NUMBITS(1) [],
+        /// Trap MRS reads of nPMSNEVFR_EL1 at EL1 using AArch64 to EL2.
+        nPMSNEVFR_EL1   OFFSET(62) NUMBITS(1) [],
+        /// Trap MRS reads of nBRBDATA at EL1 using AArch64 to EL2.
+        nBRBDATA        OFFSET(61) NUMBITS(1) [],
+        /// Trap MRS reads of nBRBCTL at EL1 using AArch64 to EL2.
+        nBRBCTL         OFFSET(60) NUMBITS(1) [],
+        /// Trap MRS reads of nBRBIDR at EL1 using AArch64 to EL2.
+        nBRBIDR         OFFSET(59) NUMBITS(1) [],
+        /// Trap MRS reads of PMCEIDn_EL0 at EL1 using AArch64 to EL2.
+        PMCEIDn_EL0     OFFSET(58) NUMBITS(1) [],
+        /// Trap MRS reads of PMUSERENR_EL0 at EL1 using AArch64 to EL2.
+        PMUSERENR_EL0   OFFSET(57) NUMBITS(1) [],
+        /// Trap MRS reads of TRBTRG_EL1 at EL1 using AArch64 to EL2.
+        TRBTRG_EL1      OFFSET(56) NUMBITS(1) [],
+        /// Trap MRS reads of TRBSR_EL1 at EL1 using AArch64 to EL2.
+        TRBSR_EL1       OFFSET(55) NUMBITS(1) [],
+        /// Trap MRS reads of TRBPTR_EL1 at EL1 using AArch64 to EL2.
+        TRBPTR_EL1      OFFSET(54) NUMBITS(1) [],
+        /// Trap MRS reads of TRBMAR_EL1 at EL1 using AArch64 to EL2.
+        TRBMAR_EL1      OFFSET(53) NUMBITS(1) [],
+        /// Trap MRS reads of TRBLIMITR_EL1 at EL1 using AArch64 to EL2.
+        TRBLIMITR_EL1   OFFSET(52) NUMBITS(1) [],
+        /// Trap MRS reads of TRBIDR_EL1 at EL1 using AArch64 to EL2.
+        TRBIDR_EL1      OFFSET(51) NUMBITS(1) [],
+        /// Trap MRS reads of TRBBASER_EL1 at EL1 using AArch64 to EL2.
+        TRBBASER_EL1    OFFSET(50) NUMBITS(1) [],
+        // 49: RES0, 保留位，写0
+        /// Trap MRS reads of TRCVICTLR at EL1 using AArch64 to EL2.
+        TRCVICTLR       OFFSET(48) NUMBITS(1) [],
+        /// Trap MRS reads of TRCSTATR at EL1 using AArch64 to EL2.
+        TRCSTATR        OFFSET(47) NUMBITS(1) [],
+        /// Trap MRS reads of TRCSSCSRn at EL1 using AArch64 to EL2.
+        TRCSSCSRn       OFFSET(46) NUMBITS(1) [],
+        /// Trap MRS reads of TRCSEQSTR at EL1 using AArch64 to EL2.
+        TRCSEQSTR       OFFSET(45) NUMBITS(1) [],
+        /// Trap MRS reads of TRCPRGCTLR at EL1 using AArch64 to EL2.
+        TRCPRGCTLR      OFFSET(44) NUMBITS(1) [],
+        /// Trap MRS reads of TRCOSLSR at EL1 using AArch64 to EL2.
+        TRCOSLSR        OFFSET(43) NUMBITS(1) [],
+        // 42: RES0, 保留位，写0
+        /// Trap MRS reads of TRCIMSPECn at EL1 using AArch64 to EL2.
+        TRCIMSPECn      OFFSET(41) NUMBITS(1) [],
+        /// Trap MRS reads of TRCID at EL1 using AArch64 to EL2.
+        TRCID           OFFSET(40) NUMBITS(1) [],
+        // 39-38: RES0, 保留位，写0
+        /// Trap MRS reads of TRCCNTVRn at EL1 using AArch64 to EL2.
+        TRCCNTVRn       OFFSET(37) NUMBITS(1) [],
+        /// Trap MRS reads of TRCCLAIM at EL1 using AArch64 to EL2.
+        TRCCLAIM        OFFSET(36) NUMBITS(1) [],
+        /// Trap MRS reads of TRCAUXCTLR at EL1 using AArch64 to EL2.
+        TRCAUXCTLR      OFFSET(35) NUMBITS(1) [],
+        /// Trap MRS reads of TRCAUTHSTATUS at EL1 using AArch64 to EL2.
+        TRCAUTHSTATUS   OFFSET(34) NUMBITS(1) [],
+        /// Trap MRS reads of TRC at EL1 using AArch64 to EL2.
+        TRC             OFFSET(33) NUMBITS(1) [],
+        /// Trap MRS reads of PMSLATFR_EL1 at EL1 using AArch64 to EL2.
+        PMSLATFR_EL1    OFFSET(32) NUMBITS(1) [],
+        /// Trap MRS reads of PMSIRR_EL1 at EL1 using AArch64 to EL2.
+        PMSIRR_EL1      OFFSET(31) NUMBITS(1) [],
+        /// Trap MRS reads of PMSIDR_EL1 at EL1 using AArch64 to EL2.
+        PMSIDR_EL1      OFFSET(30) NUMBITS(1) [],
+        /// Trap MRS reads of PMSICR_EL1 at EL1 using AArch64 to EL2.
+        PMSICR_EL1      OFFSET(29) NUMBITS(1) [],
+        /// Trap MRS reads of PMSFCR_EL1 at EL1 using AArch64 to EL2.
+        PMSFCR_EL1      OFFSET(28) NUMBITS(1) [],
+        /// Trap MRS reads of PMSEVFR_EL1 at EL1 using AArch64 to EL2.
+        PMSEVFR_EL1     OFFSET(27) NUMBITS(1) [],
+        /// Trap MRS reads of PMSCR_EL1 at EL1 using AArch64 to EL2.
+        PMSCR_EL1       OFFSET(26) NUMBITS(1) [],
+        /// Trap MRS reads of PMBSR_EL1 at EL1 using AArch64 to EL2.
+        PMBSR_EL1       OFFSET(25) NUMBITS(1) [],
+        /// Trap MRS reads of PMBPTR_EL1 at EL1 using AArch64 to EL2.
+        PMBPTR_EL1      OFFSET(24) NUMBITS(1) [],
+        /// Trap MRS reads of PMBLIMITR_EL1 at EL1 using AArch64 to EL2.
+        PMBLIMITR_EL1   OFFSET(23) NUMBITS(1) [],
+        /// Trap MRS reads of PMMIR_EL1 at EL1 using AArch64 to EL2.
+        PMMIR_EL1       OFFSET(22) NUMBITS(1) [],
+        // 21-20: RES0, 保留位，写0
+        /// Trap MRS reads of PMSELR_EL0 at EL1 using AArch64 to EL2.
+        PMSELR_EL0      OFFSET(19) NUMBITS(1) [],
+        /// Trap MRS reads of PMOVS at EL1 using AArch64 to EL2.
+        PMOVS           OFFSET(18) NUMBITS(1) [],
+        /// Trap MRS reads of PMINTEN at EL1 using AArch64 to EL2.
+        PMINTEN         OFFSET(17) NUMBITS(1) [],
+        /// Trap MRS reads of PMCNTEN at EL1 using AArch64 to EL2.
+        PMCNTEN         OFFSET(16) NUMBITS(1) [],
+        /// Trap MRS reads of PMCCNTR_EL0 at EL1 using AArch64 to EL2.
+        PMCCNTR_EL0     OFFSET(15) NUMBITS(1) [],
+        /// Trap MRS reads of PMCCFILTR_EL0 at EL1 using AArch64 to EL2.
+        PMCCFILTR_EL0   OFFSET(14) NUMBITS(1) [],
+        /// Trap MRS reads of PMEVTYPERn_EL0 at EL1 using AArch64 to EL2.
+        PMEVTYPERn_EL0  OFFSET(13) NUMBITS(1) [],
+        /// Trap MRS reads of PMEVCNTRn_EL0 at EL1 using AArch64 to EL2.
+        PMEVCNTRn_EL0   OFFSET(12) NUMBITS(1) [],
+        /// Trap MRS reads of OSDLR_EL1 at EL1 using AArch64 to EL2.
+        OSDLR_EL1       OFFSET(11) NUMBITS(1) [],
+        /// Trap MRS reads of OSECCR_EL1 at EL1 using AArch64 to EL2.
+        OSECCR_EL1      OFFSET(10) NUMBITS(1) [],
+        /// Trap MRS reads of OSLSR_EL1 at EL1 using AArch64 to EL2.
+        OSLSR_EL1       OFFSET(9) NUMBITS(1) [],
+        // 8: RES0, 保留位，写0
+        /// Trap MRS reads of DBGPRCR_EL1 at EL1 using AArch64 to EL2.
+        DBGPRCR_EL1     OFFSET(7) NUMBITS(1) [],
+        /// Trap MRS reads of DBGAUTHSTATUS_EL1 at EL1 using AArch64 to EL2.
+        DBGAUTHSTATUS_EL1 OFFSET(6) NUMBITS(1) [],
+        /// Trap MRS reads of DBGCLAIM at EL1 using AArch64 to EL2.
+        DBGCLAIM        OFFSET(5) NUMBITS(1) [],
+        /// Trap MRS reads of MDSCR_EL1 at EL1 using AArch64 to EL2.
+        MDSCR_EL1       OFFSET(4) NUMBITS(1) [],
+        /// Trap MRS reads of DBGWVRn_EL1 at EL1 using AArch64 to EL2.
+        DBGWVRn_EL1     OFFSET(3) NUMBITS(1) [],
+        /// Trap MRS reads of DBGWCRn_EL1 at EL1 using AArch64 to EL2.
+        DBGWCRn_EL1     OFFSET(2) NUMBITS(1) [],
+        /// Trap MRS reads of DBGBVRn_EL1 at EL1 using AArch64 to EL2.
+        DBGBVRn_EL1     OFFSET(1) NUMBITS(1) [],
+        /// Trap MRS reads of DBGBCRn_EL1 at EL1 using AArch64 to EL2.
+        DBGBCRn_EL1     OFFSET(0) NUMBITS(1) [],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = HDFGRTR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "S3_4_C3_C1_4", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = HDFGRTR_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "S3_4_C3_C1_4", "x");
+}
+
+pub const HDFGRTR_EL2: Reg = Reg {};
diff --git a/src/registers/hdfgwtr_el2.rs b/src/registers/hdfgwtr_el2.rs
new file mode 100644
index 0000000..b478572
--- /dev/null
+++ b/src/registers/hdfgwtr_el2.rs
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2025 by the author(s)
+//
+// Author(s):
+//   - lingfuyi. <lingfuyi@kylinos.cn>
+// https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/HDFGRTR-EL2--Hypervisor-Debug-Fine-Grained-Read-Trap-Register?lang=en
+
+//! Hypervisor Debug Fine-Grained Read Trap Register - EL2
+//!
+//! Provides controls for traps of MRS and MRC reads of debug, trace, PMU, and Statistical Profiling
+//! System registers.
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub HDFGWTR_EL2 [
+        // 63: RES0, 保留位，写0
+        /// Trap MSR writes of nPMSNEVFR_EL1 at EL1 using AArch64 to EL2.
+        nPMSNEVFR_EL1   OFFSET(62) NUMBITS(1) [],
+        /// Trap MSR writes of nBRBDATA at EL1 using AArch64 to EL2.
+        nBRBDATA        OFFSET(61) NUMBITS(1) [],
+        /// Trap MSR writes of nBRBCTL at EL1 using AArch64 to EL2.
+        nBRBCTL         OFFSET(60) NUMBITS(1) [],
+        // 59-58: RES0, 保留位，写0
+        /// Trap MSR writes of PMUSERENR_EL0 at EL1 using AArch64 to EL2.
+        PMUSERENR_EL0   OFFSET(57) NUMBITS(1) [],
+        /// Trap MSR writes of TRBTRG_EL1 at EL1 using AArch64 to EL2.
+        TRBTRG_EL1      OFFSET(56) NUMBITS(1) [],
+        /// Trap MSR writes of TRBSR_EL1 at EL1 using AArch64 to EL2.
+        TRBSR_EL1       OFFSET(55) NUMBITS(1) [],
+        /// Trap MSR writes of TRBPTR_EL1 at EL1 using AArch64 to EL2.
+        TRBPTR_EL1      OFFSET(54) NUMBITS(1) [],
+        /// Trap MSR writes of TRBMAR_EL1 at EL1 using AArch64 to EL2.
+        TRBMAR_EL1      OFFSET(53) NUMBITS(1) [],
+        /// Trap MSR writes of TRBLIMITR_EL1 at EL1 using AArch64 to EL2.
+        TRBLIMITR_EL1   OFFSET(52) NUMBITS(1) [],
+        // 51: RES0, 保留位，写0
+        /// Trap MSR writes of TRBBASER_EL1 at EL1 using AArch64 to EL2.
+        TRBBASER_EL1    OFFSET(50) NUMBITS(1) [],
+        /// Trap MSR writes of TRFCR_EL1 at EL1 using AArch64 to EL2.
+        TRFCR_EL1       OFFSET(49) NUMBITS(1) [],
+        /// Trap MSR writes of TRCVICTLR at EL1 using AArch64 to EL2.
+        TRCVICTLR       OFFSET(48) NUMBITS(1) [],
+        // 47: RES0, 保留位，写0
+        /// Trap MSR writes of TRCSSCSRn at EL1 using AArch64 to EL2.
+        TRCSSCSRn       OFFSET(46) NUMBITS(1) [],
+        /// Trap MSR writes of TRCSEQSTR at EL1 using AArch64 to EL2.
+        TRCSEQSTR       OFFSET(45) NUMBITS(1) [],
+        /// Trap MSR writes of TRCPRGCTLR at EL1 using AArch64 to EL2.
+        TRCPRGCTLR      OFFSET(44) NUMBITS(1) [],
+        // 43: RES0, 保留位，写0
+        /// Trap MSR writes of TRCOSLAR at EL1 using AArch64 to EL2.
+        TRCOSLAR        OFFSET(42) NUMBITS(1) [],
+        /// Trap MSR writes of TRCIMSPECn at EL1 using AArch64 to EL2.
+        TRCIMSPECn      OFFSET(41) NUMBITS(1) [],
+        // 40-38: RES0, 保留位，写0
+        /// Trap MSR writes of TRCCNTVRn at EL1 using AArch64 to EL2.
+        TRCCNTVRn       OFFSET(37) NUMBITS(1) [],
+        /// Trap MSR writes of TRCCLAIM at EL1 using AArch64 to EL2.
+        TRCCLAIM        OFFSET(36) NUMBITS(1) [],
+        /// Trap MSR writes of TRCAUXCTLR at EL1 using AArch64 to EL2.
+        TRCAUXCTLR      OFFSET(35) NUMBITS(1) [],
+        // 34: RES0, 保留位，写0
+        /// Trap MSR writes of TRC at EL1 using AArch64 to EL2.
+        TRC             OFFSET(33) NUMBITS(1) [],
+        /// Trap MSR writes of PMSLATFR_EL1 at EL1 using AArch64 to EL2.
+        PMSLATFR_EL1    OFFSET(32) NUMBITS(1) [],
+        /// Trap MSR writes of PMSIRR_EL1 at EL1 using AArch64 to EL2.
+        PMSIRR_EL1      OFFSET(31) NUMBITS(1) [],
+        // 30: RES0, 保留位，写0
+        /// Trap MSR writes of PMSICR_EL1 at EL1 using AArch64 to EL2.
+        PMSICR_EL1      OFFSET(29) NUMBITS(1) [],
+        /// Trap MSR writes of PMSFCR_EL1 at EL1 using AArch64 to EL2.
+        PMSFCR_EL1      OFFSET(28) NUMBITS(1) [],
+        /// Trap MSR writes of PMSEVFR_EL1 at EL1 using AArch64 to EL2.
+        PMSEVFR_EL1     OFFSET(27) NUMBITS(1) [],
+        /// Trap MSR writes of PMSCR_EL1 at EL1 using AArch64 to EL2.
+        PMSCR_EL1       OFFSET(26) NUMBITS(1) [],
+        /// Trap MSR writes of PMBSR_EL1 at EL1 using AArch64 to EL2.
+        PMBSR_EL1       OFFSET(25) NUMBITS(1) [],
+        /// Trap MSR writes of PMBPTR_EL1 at EL1 using AArch64 to EL2.
+        PMBPTR_EL1      OFFSET(24) NUMBITS(1) [],
+        /// Trap MSR writes of PMBLIMITR_EL1 at EL1 using AArch64 to EL2.
+        PMBLIMITR_EL1   OFFSET(23) NUMBITS(1) [],
+        // 22: RES0, 保留位，写0
+        /// Trap MSR writes of PMCR_EL0 at EL1 using AArch64 to EL2.
+        PMCR_EL0        OFFSET(21) NUMBITS(1) [],
+        /// Trap MSR writes of PMSWINC_EL0 at EL1 using AArch64 to EL2.
+        PMSWINC_EL0     OFFSET(20) NUMBITS(1) [],
+        /// Trap MSR writes of PMSELR_EL0 at EL1 using AArch64 to EL2.
+        PMSELR_EL0      OFFSET(19) NUMBITS(1) [],
+        /// Trap MSR writes of PMOVS at EL1 using AArch64 to EL2.
+        PMOVS           OFFSET(18) NUMBITS(1) [],
+        /// Trap MSR writes of PMINTEN at EL1 using AArch64 to EL2.
+        PMINTEN         OFFSET(17) NUMBITS(1) [],
+        /// Trap MSR writes of PMCNTEN at EL1 using AArch64 to EL2.
+        PMCNTEN         OFFSET(16) NUMBITS(1) [],
+        /// Trap MSR writes of PMCCNTR_EL0 at EL1 using AArch64 to EL2.
+        PMCCNTR_EL0     OFFSET(15) NUMBITS(1) [],
+        /// Trap MSR writes of PMCCFILTR_EL0 at EL1 using AArch64 to EL2.
+        PMCCFILTR_EL0   OFFSET(14) NUMBITS(1) [],
+        /// Trap MSR writes of PMEVTYPERn_EL0 at EL1 using AArch64 to EL2.
+        PMEVTYPERn_EL0  OFFSET(13) NUMBITS(1) [],
+        /// Trap MSR writes of PMEVCNTRn_EL0 at EL1 using AArch64 to EL2.
+        PMEVCNTRn_EL0   OFFSET(12) NUMBITS(1) [],
+        /// Trap MSR writes of OSDLR_EL1 at EL1 using AArch64 to EL2.
+        OSDLR_EL1       OFFSET(11) NUMBITS(1) [],
+        /// Trap MSR writes of OSECCR_EL1 at EL1 using AArch64 to EL2.
+        OSECCR_EL1      OFFSET(10) NUMBITS(1) [],
+        // 9: RES0, 保留位，写0
+        /// Trap MSR writes of OSLAR_EL1 at EL1 using AArch64 to EL2.
+        OSLAR_EL1       OFFSET(8) NUMBITS(1) [],
+        /// Trap MSR writes of DBGPRCR_EL1 at EL1 using AArch64 to EL2.
+        DBGPRCR_EL1     OFFSET(7) NUMBITS(1) [],
+        // 6: RES0, 保留位，写0
+        /// Trap MSR writes of DBGCLAIM at EL1 using AArch64 to EL2.
+        DBGCLAIM        OFFSET(5) NUMBITS(1) [],
+        /// Trap MSR writes of MDSCR_EL1 at EL1 using AArch64 to EL2.
+        MDSCR_EL1       OFFSET(4) NUMBITS(1) [],
+        /// Trap MSR writes of DBGWVRn_EL1 at EL1 using AArch64 to EL2.
+        DBGWVRn_EL1     OFFSET(3) NUMBITS(1) [],
+        /// Trap MSR writes of DBGWCRn_EL1 at EL1 using AArch64 to EL2.
+        DBGWCRn_EL1     OFFSET(2) NUMBITS(1) [],
+        /// Trap MSR writes of DBGBVRn_EL1 at EL1 using AArch64 to EL2.
+        DBGBVRn_EL1     OFFSET(1) NUMBITS(1) [],
+        /// Trap MSR writes of DBGBCRn_EL1 at EL1 using AArch64 to EL2.
+        DBGBCRn_EL1     OFFSET(0) NUMBITS(1) [],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = HDFGWTR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "S3_4_C3_C1_5", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = HDFGWTR_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "S3_4_C3_C1_5", "x");
+}
+
+pub const HDFGWTR_EL2: Reg = Reg {};
diff --git a/src/registers/hfgitr_el2.rs b/src/registers/hfgitr_el2.rs
new file mode 100644
index 0000000..fb2ff10
--- /dev/null
+++ b/src/registers/hfgitr_el2.rs
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2025 by the author(s)
+//
+// Author(s):
+//   - lingfuyi. <lingfuyi@kylinos.cn>
+// https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/HFGITR-EL2--Hypervisor-Fine-Grained-Instruction-Trap-Register?lang=en
+
+//! Hypervisor Fine-Grained Instruction Trap Register - EL2
+//!
+//! Provides instruction trap controls for EL2.
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub HFGITR_EL2 [
+        /// [63] Trap execution of PSBCSYNC at EL1 to EL2
+        PSBCSYNC     OFFSET(63) NUMBITS(1) [],
+        /// [62] Trap execution of AT S1E1A at EL1 using AArch64 to EL2
+        ATS1E1A      OFFSET(62) NUMBITS(1) [],
+        // 61: Reserved (RES0)
+        /// [60] Trap execution of COSP-related context instructions at EL1 to EL2
+        COSPRCTX     OFFSET(60) NUMBITS(1) [],
+        /// [59] Trap execution of GCSEPP at EL1 to EL2
+        nGCSEPP      OFFSET(59) NUMBITS(1) [],
+        /// [58] Trap execution of GCSSTR_EL1 at EL1 to EL2
+        nGCSSTR_EL1  OFFSET(58) NUMBITS(1) [],
+        /// [57] Trap execution of GCSPUSHM_EL1 at EL1 to EL2
+        nGCSPUSHM_EL1 OFFSET(57) NUMBITS(1) [],
+        /// [56] Trap execution of BRBIALL at EL1 to EL2
+        nBRBIALL     OFFSET(56) NUMBITS(1) [],
+        /// [55] Trap execution of BRBINJ at EL1 to EL2
+        nBRBINJ      OFFSET(55) NUMBITS(1) [],
+        /// [54] Trap execution of DCCVAC at EL1 to EL2
+        DCCVAC       OFFSET(54) NUMBITS(1) [],
+        /// [53] Trap execution of SVC at EL1 to EL2
+        SVC_EL1      OFFSET(53) NUMBITS(1) [],
+        /// [52] Trap execution of SVC at EL0 to EL2
+        SVC_EL0      OFFSET(52) NUMBITS(1) [],
+        /// [51] Trap execution of ERET at EL1 to EL2
+        ERET         OFFSET(51) NUMBITS(1) [],
+        /// [50] Trap execution of CPPRCTX at EL1 to EL2
+        CPPRCTX      OFFSET(50) NUMBITS(1) [],
+        /// [49] Trap execution of DVPRCTX at EL1 to EL2
+        DVPRCTX      OFFSET(49) NUMBITS(1) [],
+        /// [48] Trap execution of CFPRCTX at EL1 to EL2
+        CFPRCTX      OFFSET(48) NUMBITS(1) [],
+        /// [47] Trap execution of TLBIVAALE1 at EL1 to EL2
+        TLBIVAALE1   OFFSET(47) NUMBITS(1) [],
+        /// [46] Trap execution of TLBIVALE1 at EL1 to EL2
+        TLBIVALE1    OFFSET(46) NUMBITS(1) [],
+        /// [45] Trap execution of TLBIVAAE1 at EL1 to EL2
+        TLBIVAAE1    OFFSET(45) NUMBITS(1) [],
+        /// [44] Trap execution of TLBIASIDE1 at EL1 to EL2
+        TLBIASIDE1   OFFSET(44) NUMBITS(1) [],
+        /// [43] Trap execution of TLBIVAE1 at EL1 to EL2
+        TLBIVAE1     OFFSET(43) NUMBITS(1) [],
+        /// [42] Trap execution of TLBIVMALLE1 at EL1 to EL2
+        TLBIVMALLE1  OFFSET(42) NUMBITS(1) [],
+        /// [41] Trap execution of TLBIRVAALE1 at EL1 to EL2
+        TLBIRVAALE1  OFFSET(41) NUMBITS(1) [],
+        /// [40] Trap execution of TLBIRVALE1 at EL1 to EL2
+        TLBIRVALE1   OFFSET(40) NUMBITS(1) [],
+        /// [39] Trap execution of TLBIRVAAE1 at EL1 to EL2
+        TLBIRVAAE1   OFFSET(39) NUMBITS(1) [],
+        /// [38] Trap execution of TLBIRVAE1 at EL1 to EL2
+        TLBIRVAE1    OFFSET(38) NUMBITS(1) [],
+        /// [37] Trap execution of TLBIRVAALE1IS at EL1 to EL2
+        TLBIRVAALE1IS OFFSET(37) NUMBITS(1) [],
+        /// [36] Trap execution of TLBIRVALE1IS at EL1 to EL2
+        TLBIRVALE1IS OFFSET(36) NUMBITS(1) [],
+        /// [35] Trap execution of TLBIRVAAE1IS at EL1 to EL2
+        TLBIRVAAE1IS OFFSET(35) NUMBITS(1) [],
+        /// [34] Trap execution of TLBIRVAE1IS at EL1 to EL2
+        TLBIRVAE1IS  OFFSET(34) NUMBITS(1) [],
+        /// [33] Trap execution of TLBIVAALE1IS at EL1 to EL2
+        TLBIVAALE1IS OFFSET(33) NUMBITS(1) [],
+        /// [32] Trap execution of TLBIVALE1IS at EL1 to EL2
+        TLBIVALE1IS  OFFSET(32) NUMBITS(1) [],
+        /// [31] Trap execution of TLBIVAAE1IS at EL1 to EL2
+        TLBIVAAE1IS  OFFSET(31) NUMBITS(1) [],
+        /// [30] Trap execution of TLBIASIDE1IS at EL1 to EL2
+        TLBIASIDE1IS OFFSET(30) NUMBITS(1) [],
+        /// [29] Trap execution of TLBIVAE1IS at EL1 to EL2
+        TLBIVAE1IS   OFFSET(29) NUMBITS(1) [],
+        /// [28] Trap execution of TLBIVMALLE1IS at EL1 to EL2
+        TLBIVMALLE1IS OFFSET(28) NUMBITS(1) [],
+        /// [27] Trap execution of TLBIRVAALE1OS at EL1 to EL2
+        TLBIRVAALE1OS OFFSET(27) NUMBITS(1) [],
+        /// [26] Trap execution of TLBIRVALE1OS at EL1 to EL2
+        TLBIRVALE1OS OFFSET(26) NUMBITS(1) [],
+        /// [25] Trap execution of TLBIRVAAE1OS at EL1 to EL2
+        TLBIRVAAE1OS OFFSET(25) NUMBITS(1) [],
+        /// [24] Trap execution of TLBIRVAE1OS at EL1 to EL2
+        TLBIRVAE1OS  OFFSET(24) NUMBITS(1) [],
+        /// [23] Trap execution of TLBIVAALE1OS at EL1 to EL2
+        TLBIVAALE1OS OFFSET(23) NUMBITS(1) [],
+        /// [22] Trap execution of TLBIVALE1OS at EL1 to EL2
+        TLBIVALE1OS  OFFSET(22) NUMBITS(1) [],
+        /// [21] Trap execution of TLBIVAAE1OS at EL1 to EL2
+        TLBIVAAE1OS  OFFSET(21) NUMBITS(1) [],
+        /// [20] Trap execution of TLBIASIDE1OS at EL1 to EL2
+        TLBIASIDE1OS OFFSET(20) NUMBITS(1) [],
+        /// [19] Trap execution of TLBIVAE1OS at EL1 to EL2
+        TLBIVAE1OS   OFFSET(19) NUMBITS(1) [],
+        /// [18] Trap execution of TLBIVMALLE1OS at EL1 to EL2
+        TLBIVMALLE1OS OFFSET(18) NUMBITS(1) [],
+        /// [17] Trap execution of ATS1E1WP at EL1 to EL2
+        ATS1E1WP     OFFSET(17) NUMBITS(1) [],
+        /// [16] Trap execution of ATS1E1RP at EL1 to EL2
+        ATS1E1RP     OFFSET(16) NUMBITS(1) [],
+        /// [15] Trap execution of ATS1E0W at EL1 to EL2
+        ATS1E0W      OFFSET(15) NUMBITS(1) [],
+        /// [14] Trap execution of ATS1E0R at EL1 to EL2
+        ATS1E0R      OFFSET(14) NUMBITS(1) [],
+        /// [13] Trap execution of ATS1E1W at EL1 to EL2
+        ATS1E1W      OFFSET(13) NUMBITS(1) [],
+        /// [12] Trap execution of ATS1E1R at EL1 to EL2
+        ATS1E1R      OFFSET(12) NUMBITS(1) [],
+        /// [11] Trap execution of DCZVA at EL1 to EL2
+        DCZVA        OFFSET(11) NUMBITS(1) [],
+        /// [10] Trap execution of DCCIVAC at EL1 to EL2
+        DCCIVAC      OFFSET(10) NUMBITS(1) [],
+        /// [9] Trap execution of DCCVADP at EL1 to EL2
+        DCCVADP      OFFSET(9) NUMBITS(1) [],
+        /// [8] Trap execution of DCCVAP at EL1 to EL2
+        DCCVAP       OFFSET(8) NUMBITS(1) [],
+        /// [7] Trap execution of DCCVAU at EL1 to EL2
+        DCCVAU       OFFSET(7) NUMBITS(1) [],
+        /// [6] Trap execution of DCCISW at EL1 to EL2
+        DCCISW       OFFSET(6) NUMBITS(1) [],
+        /// [5] Trap execution of DCCSW at EL1 to EL2
+        DCCSW        OFFSET(5) NUMBITS(1) [],
+        /// [4] Trap execution of DCISW at EL1 to EL2
+        DCISW        OFFSET(4) NUMBITS(1) [],
+        /// [3] Trap execution of DCIVAC at EL1 to EL2
+        DCIVAC       OFFSET(3) NUMBITS(1) [],
+        /// [2] Trap execution of IC IVAU at EL1/EL0 to EL2
+        ICIVAU       OFFSET(2) NUMBITS(1) [],
+        /// [1] Trap execution of IC IALLU at EL1 to EL2
+        ICIALLU      OFFSET(1) NUMBITS(1) [],
+        /// [0] Trap execution of IC IALLUIS at EL1 to EL2
+        ICIALLUIS    OFFSET(0) NUMBITS(1) [],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = HFGITR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "S3_4_C1_C1_6", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = HFGITR_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "S3_4_C1_C1_6", "x");
+}
+
+pub const HFGITR_EL2: Reg = Reg {};
diff --git a/src/registers/hfgrtr_el2.rs b/src/registers/hfgrtr_el2.rs
new file mode 100644
index 0000000..b7e39fb
--- /dev/null
+++ b/src/registers/hfgrtr_el2.rs
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2025 by the author(s)
+//
+// Author(s):
+//   - lingfuyi. <lingfuyi@kylinos.cn>
+// https://developer.arm.com/documentation/ddi0601/2025-03/AArch64-Registers/HFGRTR-EL2--Hypervisor-Fine-Grained-Read-Trap-Register?lang=en
+
+//! Hypervisor Fine-Grained Read Trap Register - EL2
+//!
+//! Provides controls for traps of MRRS, MRS and MRC reads of System registers for EL2.
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub HFGRTR_EL2 [
+        /// Trap MRS reads of AMAIR2_EL1 at EL1 to EL2
+        nAMAIR2_EL1   OFFSET(63) NUMBITS(1) [],
+        /// Trap MRS reads of MAIR2_EL1 at EL1 to EL2
+        nMAIR2_EL1    OFFSET(62) NUMBITS(1) [],
+        /// Trap MRS reads of S2POR_EL1 at EL1 to EL2
+        nS2POR_EL1    OFFSET(61) NUMBITS(1) [],
+        /// Trap MRS reads of POR_EL1 at EL1 to EL2
+        nPOR_EL1      OFFSET(60) NUMBITS(1) [],
+        /// Trap MRS reads of POR_EL0 at EL1 to EL2
+        nPOR_EL0      OFFSET(59) NUMBITS(1) [],
+        /// Trap MRS reads of PIR_EL1 at EL1 to EL2
+        nPIR_EL1      OFFSET(58) NUMBITS(1) [],
+        /// Trap MRS reads of PIRE0_EL1 at EL1 to EL2
+        nPIRE0_EL1    OFFSET(57) NUMBITS(1) [],
+        /// Trap MRS reads of RCWMASK_EL1 at EL1 to EL2
+        nRCWMASK_EL1  OFFSET(56) NUMBITS(1) [],
+        /// Trap MRS reads of TPIDR2_EL0 at EL1 to EL2
+        nTPIDR2_EL0   OFFSET(55) NUMBITS(1) [],
+        /// Trap MRS reads of SMPRI_EL1 at EL1 to EL2
+        nSMPRI_EL1    OFFSET(54) NUMBITS(1) [],
+        /// Trap MRS reads of GCS_EL1 at EL1 to EL2
+        nGCS_EL1      OFFSET(53) NUMBITS(1) [],
+        /// Trap MRS reads of GCS_EL0 at EL1 to EL2
+        nGCS_EL0      OFFSET(52) NUMBITS(1) [],
+        // 51: RES0 (reserved)
+        /// Trap MRS reads of ACCDATA_EL1 at EL1 to EL2
+        nACCDATA_EL1  OFFSET(50) NUMBITS(1) [],
+        /// Trap MRS reads of ERXADDR_EL1 at EL1 to EL2
+        ERXADDR_EL1   OFFSET(49) NUMBITS(1) [],
+        /// Trap MRS reads of ERXPFGCDN_EL1 at EL1 to EL2
+        ERXPFGCDN_EL1 OFFSET(48) NUMBITS(1) [],
+        /// Trap MRS reads of ERXPFGCTL_EL1 at EL1 to EL2
+        ERXPFGCTL_EL1 OFFSET(47) NUMBITS(1) [],
+        /// Trap MRS reads of ERXPFGF_EL1 at EL1 to EL2
+        ERXPFGF_EL1   OFFSET(46) NUMBITS(1) [],
+        /// Trap MRS reads of ERXMISCn_EL1 at EL1 to EL2
+        ERXMISCn_EL1  OFFSET(45) NUMBITS(1) [],
+        /// Trap MRS reads of ERXSTATUS_EL1 at EL1 to EL2
+        ERXSTATUS_EL1 OFFSET(44) NUMBITS(1) [],
+        /// Trap MRS reads of ERXCTLR_EL1 at EL1 to EL2
+        ERXCTLR_EL1   OFFSET(43) NUMBITS(1) [],
+        /// Trap MRS reads of ERXFR_EL1 at EL1 to EL2
+        ERXFR_EL1     OFFSET(42) NUMBITS(1) [],
+        /// Trap MRS reads of ERRSELR_EL1 at EL1 to EL2
+        ERRSELR_EL1   OFFSET(41) NUMBITS(1) [],
+        /// Trap MRS reads of ERRIDR_EL1 at EL1 to EL2
+        ERRIDR_EL1    OFFSET(40) NUMBITS(1) [],
+        /// Trap MRS reads of ICC_IGRPENn_EL1 at EL1 to EL2
+        ICC_IGRPENn_EL1 OFFSET(39) NUMBITS(1) [],
+        /// Trap MRS reads of VBAR_EL1 at EL1 to EL2
+        VBAR_EL1      OFFSET(38) NUMBITS(1) [],
+        /// Trap MRS reads of TTBR1_EL1 at EL1 to EL2
+        TTBR1_EL1     OFFSET(37) NUMBITS(1) [],
+        /// Trap MRS reads of TTBR0_EL1 at EL1 to EL2
+        TTBR0_EL1     OFFSET(36) NUMBITS(1) [],
+        /// Trap MRS reads of TPIDR_EL0 at EL1 to EL2
+        TPIDR_EL0     OFFSET(35) NUMBITS(1) [],
+        /// Trap MRS reads of TPIDRRO_EL0 at EL1 to EL2
+        TPIDRRO_EL0   OFFSET(34) NUMBITS(1) [],
+        /// Trap MRS reads of TPIDR_EL1 at EL1 to EL2
+        TPIDR_EL1     OFFSET(33) NUMBITS(1) [],
+        /// Trap MRS reads of TCR_EL1 at EL1 to EL2
+        TCR_EL1       OFFSET(32) NUMBITS(1) [],
+        /// Trap MRS reads of SCXTNUM_EL0 at EL1 to EL2
+        SCXTNUM_EL0   OFFSET(31) NUMBITS(1) [],
+        /// Trap MRS reads of SCXTNUM_EL1 at EL1 to EL2
+        SCXTNUM_EL1   OFFSET(30) NUMBITS(1) [],
+        /// Trap MRS reads of SCTLR_EL1 at EL1 to EL2
+        SCTLR_EL1     OFFSET(29) NUMBITS(1) [],
+        /// Trap MRS reads of REVIDR_EL1 at EL1 to EL2
+        REVIDR_EL1    OFFSET(28) NUMBITS(1) [],
+        /// Trap MRS reads of PAR_EL1 at EL1 to EL2
+        PAR_EL1       OFFSET(27) NUMBITS(1) [],
+        /// Trap MRS reads of MPIDR_EL1 at EL1 to EL2
+        MPIDR_EL1     OFFSET(26) NUMBITS(1) [],
+        /// Trap MRS reads of MIDR_EL1 at EL1 to EL2
+        MIDR_EL1      OFFSET(25) NUMBITS(1) [],
+        /// Trap MRS reads of MAIR_EL1 at EL1 to EL2
+        MAIR_EL1      OFFSET(24) NUMBITS(1) [],
+        /// Trap MRS reads of LORSA_EL1 at EL1 to EL2
+        LORSA_EL1     OFFSET(23) NUMBITS(1) [],
+        /// Trap MRS reads of LORN_EL1 at EL1 to EL2
+        LORN_EL1      OFFSET(22) NUMBITS(1) [],
+        /// Trap MRS reads of LORID_EL1 at EL1 to EL2
+        LORID_EL1     OFFSET(21) NUMBITS(1) [],
+        /// Trap MRS reads of LOREA_EL1 at EL1 to EL2
+        LOREA_EL1     OFFSET(20) NUMBITS(1) [],
+        /// Trap MRS reads of LORC_EL1 at EL1 to EL2
+        LORC_EL1      OFFSET(19) NUMBITS(1) [],
+        /// Trap MRS reads of ISR_EL1 at EL1 to EL2
+        ISR_EL1       OFFSET(18) NUMBITS(1) [],
+        /// Trap MRS reads of FAR_EL1 at EL1 to EL2
+        FAR_EL1       OFFSET(17) NUMBITS(1) [],
+        /// Trap MRS reads of ESR_EL1 at EL1 to EL2
+        ESR_EL1       OFFSET(16) NUMBITS(1) [],
+        /// Trap MRS reads of DCZID_EL0 at EL1 to EL2
+        DCZID_EL0     OFFSET(15) NUMBITS(1) [],
+        /// Trap MRS reads of CTR_EL0 at EL1 to EL2
+        CTR_EL0       OFFSET(14) NUMBITS(1) [],
+        /// Trap MRS reads of CSSELR_EL1 at EL1 to EL2
+        CSSELR_EL1    OFFSET(13) NUMBITS(1) [],
+        /// Trap MRS reads of CPACR_EL1 at EL1 to EL2
+        CPACR_EL1     OFFSET(12) NUMBITS(1) [],
+        /// Trap MRS reads of CONTEXTIDR_EL1 at EL1 to EL2
+        CONTEXTIDR_EL1 OFFSET(11) NUMBITS(1) [],
+        /// Trap MRS reads of CLIDR_EL1 at EL1 to EL2
+        CLIDR_EL1     OFFSET(10) NUMBITS(1) [],
+        /// Trap MRS reads of CCSIDR_EL1 at EL1 to EL2
+        CCSIDR_EL1    OFFSET(9) NUMBITS(1) [],
+        /// Trap MRS reads of APIBKey at EL1 to EL2
+        APIBKey       OFFSET(8) NUMBITS(1) [],
+        /// Trap MRS reads of APIAKey at EL1 to EL2
+        APIAKey       OFFSET(7) NUMBITS(1) [],
+        /// Trap MRS reads of APGAKey at EL1 to EL2
+        APGAKey       OFFSET(6) NUMBITS(1) [],
+        /// Trap MRS reads of APDBKey at EL1 to EL2
+        APDBKey       OFFSET(5) NUMBITS(1) [],
+        /// Trap MRS reads of APDAKey at EL1 to EL2
+        APDAKey       OFFSET(4) NUMBITS(1) [],
+        /// Trap MRS reads of AMAIR_EL1 at EL1 to EL2
+        AMAIR_EL1     OFFSET(3) NUMBITS(1) [],
+        /// Trap MRS reads of AIDR_EL1 at EL1 to EL2
+        AIDR_EL1      OFFSET(2) NUMBITS(1) [],
+        /// Trap MRS reads of AFSR1_EL1 at EL1 to EL2
+        AFSR1_EL1     OFFSET(1) NUMBITS(1) [],
+        /// Trap MRS reads of AFSR0_EL1 at EL1 to EL2
+        AFSR0_EL1     OFFSET(0) NUMBITS(1) [],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = HFGRTR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "S3_4_C1_C1_4", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = HFGRTR_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "S3_4_C1_C1_4", "x");
+}
+
+pub const HFGRTR_EL2: Reg = Reg {};
diff --git a/src/registers/hfgwtr_el2.rs b/src/registers/hfgwtr_el2.rs
new file mode 100644
index 0000000..26bb2bb
--- /dev/null
+++ b/src/registers/hfgwtr_el2.rs
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2025 by the author(s)
+//
+// Author(s):
+//   - lingfuyi. <lingfuyi@kylinos.cn>
+
+//! Hypervisor Fine-Grained Write Trap Register - EL2
+//!
+//! Provides controls for traps of MSR and MCR writes of System registers
+
+use tock_registers::{
+    interfaces::{Readable, Writeable},
+    register_bitfields,
+};
+
+register_bitfields! {u64,
+    pub HFGWTR_EL2 [
+        /// Trap MSR writes of AMAIR2_EL1 at EL1 to EL2
+        nAMAIR2_EL1   OFFSET(63) NUMBITS(1) [],
+        /// Trap MSR writes of MAIR2_EL1 at EL1 to EL2
+        nMAIR2_EL1    OFFSET(62) NUMBITS(1) [],
+        /// Trap MSR writes of S2POR_EL1 at EL1 to EL2
+        nS2POR_EL1    OFFSET(61) NUMBITS(1) [],
+        /// Trap MSR writes of POR_EL1 at EL1 to EL2
+        nPOR_EL1      OFFSET(60) NUMBITS(1) [],
+        /// Trap MSR writes of POR_EL0 at EL1 to EL2
+        nPOR_EL0      OFFSET(59) NUMBITS(1) [],
+        /// Trap MSR writes of PIR_EL1 at EL1 to EL2
+        nPIR_EL1      OFFSET(58) NUMBITS(1) [],
+        /// Trap MSR writes of PIRE0_EL1 at EL1 to EL2
+        nPIRE0_EL1    OFFSET(57) NUMBITS(1) [],
+        /// Trap MSR writes of RCWMASK_EL1 at EL1 to EL2
+        nRCWMASK_EL1  OFFSET(56) NUMBITS(1) [],
+        /// Trap MSR writes of TPIDR2_EL0 at EL1 to EL2
+        nTPIDR2_EL0   OFFSET(55) NUMBITS(1) [],
+        /// Trap MSR writes of SMPRI_EL1 at EL1 to EL2
+        nSMPRI_EL1    OFFSET(54) NUMBITS(1) [],
+        /// Trap MSR writes of GCS_EL1 at EL1 to EL2
+        nGCS_EL1      OFFSET(53) NUMBITS(1) [],
+        /// Trap MSR writes of GCS_EL0 at EL1 to EL2
+        nGCS_EL0      OFFSET(52) NUMBITS(1) [],
+        // 51: RES0 (reserved)
+        /// Trap MSR writes of ACCDATA_EL1 at EL1 to EL2
+        nACCDATA_EL1  OFFSET(50) NUMBITS(1) [],
+        /// Trap MSR writes of ERXADDR_EL1 at EL1 to EL2
+        ERXADDR_EL1   OFFSET(49) NUMBITS(1) [],
+        /// Trap MSR writes of ERXPFGCDN_EL1 at EL1 to EL2
+        ERXPFGCDN_EL1 OFFSET(48) NUMBITS(1) [],
+        /// Trap MSR writes of ERXPFGCTL_EL1 at EL1 to EL2
+        ERXPFGCTL_EL1 OFFSET(47) NUMBITS(1) [],
+        // 46: RES0 (reserved)
+        /// Trap MSR writes of ERXMISCn_EL1 at EL1 to EL2
+        ERXMISCn_EL1  OFFSET(45) NUMBITS(1) [],
+        /// Trap MSR writes of ERXSTATUS_EL1 at EL1 to EL2
+        ERXSTATUS_EL1 OFFSET(44) NUMBITS(1) [],
+        /// Trap MSR writes of ERXCTLR_EL1 at EL1 to EL2
+        ERXCTLR_EL1   OFFSET(43) NUMBITS(1) [],
+        // 42: RES0 (reserved)
+        /// Trap MSR writes of ERRSELR_EL1 at EL1 to EL2
+        ERRSELR_EL1   OFFSET(41) NUMBITS(1) [],
+        // 40: RES0 (reserved)
+        /// Trap MSR writes of ICC_IGRPENn_EL1 at EL1 to EL2
+        ICC_IGRPENn_EL1 OFFSET(39) NUMBITS(1) [],
+        /// Trap MSR writes of VBAR_EL1 at EL1 to EL2
+        VBAR_EL1      OFFSET(38) NUMBITS(1) [],
+        /// Trap MSR writes of TTBR1_EL1 at EL1 to EL2
+        TTBR1_EL1     OFFSET(37) NUMBITS(1) [],
+        /// Trap MSR writes of TTBR0_EL1 at EL1 to EL2
+        TTBR0_EL1     OFFSET(36) NUMBITS(1) [],
+        /// Trap MSR writes of TPIDR_EL0 at EL1 to EL2
+        TPIDR_EL0     OFFSET(35) NUMBITS(1) [],
+        /// Trap MSR writes of TPIDRRO_EL0 at EL1 to EL2
+        TPIDRRO_EL0   OFFSET(34) NUMBITS(1) [],
+        /// Trap MSR writes of TPIDR_EL1 at EL1 to EL2
+        TPIDR_EL1     OFFSET(33) NUMBITS(1) [],
+        /// Trap MSR writes of TCR_EL1 at EL1 to EL2
+        TCR_EL1       OFFSET(32) NUMBITS(1) [],
+        /// Trap MSR writes of SCXTNUM_EL0 at EL1 to EL2
+        SCXTNUM_EL0   OFFSET(31) NUMBITS(1) [],
+        /// Trap MSR writes of SCXTNUM_EL1 at EL1 to EL2
+        SCXTNUM_EL1   OFFSET(30) NUMBITS(1) [],
+        /// Trap MSR writes of SCTLR_EL1 at EL1 to EL2
+        SCTLR_EL1     OFFSET(29) NUMBITS(1) [],
+        // 28: RES0 (reserved)
+        /// Trap MSR writes of PAR_EL1 at EL1 to EL2
+        PAR_EL1       OFFSET(27) NUMBITS(1) [],
+        // 26: RES0 (reserved)
+        // 25: RES0 (reserved)
+        /// Trap MSR writes of MAIR_EL1 at EL1 to EL2
+        MAIR_EL1      OFFSET(24) NUMBITS(1) [],
+        /// Trap MSR writes of LORSA_EL1 at EL1 to EL2
+        LORSA_EL1     OFFSET(23) NUMBITS(1) [],
+        /// Trap MSR writes of LORN_EL1 at EL1 to EL2
+        LORN_EL1      OFFSET(22) NUMBITS(1) [],
+        // 21: RES0 (reserved)
+        /// Trap MSR writes of LOREA_EL1 at EL1 to EL2
+        LOREA_EL1     OFFSET(20) NUMBITS(1) [],
+        /// Trap MSR writes of LORC_EL1 at EL1 to EL2
+        LORC_EL1      OFFSET(19) NUMBITS(1) [],
+        // 18: RES0 (reserved)
+        /// Trap MSR writes of FAR_EL1 at EL1 to EL2
+        FAR_EL1       OFFSET(17) NUMBITS(1) [],
+        /// Trap MSR writes of ESR_EL1 at EL1 to EL2
+        ESR_EL1       OFFSET(16) NUMBITS(1) [],
+        // 15: RES0 (reserved)
+        // 14: RES0 (reserved)
+        /// Trap MSR writes of CSSELR_EL1 at EL1 to EL2
+        CSSELR_EL1    OFFSET(13) NUMBITS(1) [],
+        /// Trap MSR writes of CPACR_EL1 at EL1 to EL2
+        CPACR_EL1     OFFSET(12) NUMBITS(1) [],
+        /// Trap MSR writes of CONTEXTIDR_EL1 at EL1 to EL2
+        CONTEXTIDR_EL1 OFFSET(11) NUMBITS(1) [],
+        // 10: RES0 (reserved)
+        // 9: RES0 (reserved)
+        /// Trap MSR writes of APIBKey at EL1 to EL2
+        APIBKey       OFFSET(8) NUMBITS(1) [],
+        /// Trap MSR writes of APIAKey at EL1 to EL2
+        APIAKey       OFFSET(7) NUMBITS(1) [],
+        /// Trap MSR writes of APGAKey at EL1 to EL2
+        APGAKey       OFFSET(6) NUMBITS(1) [],
+        /// Trap MSR writes of APDBKey at EL1 to EL2
+        APDBKey       OFFSET(5) NUMBITS(1) [],
+        /// Trap MSR writes of APDAKey at EL1 to EL2
+        APDAKey       OFFSET(4) NUMBITS(1) [],
+        /// Trap MSR writes of AMAIR_EL1 at EL1 to EL2
+        AMAIR_EL1     OFFSET(3) NUMBITS(1) [],
+        // 2: RES0 (reserved)
+        /// Trap MSR writes of AFSR1_EL1 at EL1 to EL2
+        AFSR1_EL1     OFFSET(1) NUMBITS(1) [],
+        /// Trap MSR writes of AFSR0_EL1 at EL1 to EL2
+        AFSR0_EL1     OFFSET(0) NUMBITS(1) [],
+    ]
+}
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = HFGWTR_EL2::Register;
+
+    sys_coproc_read_raw!(u64, "S3_4_C1_C1_5", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = HFGWTR_EL2::Register;
+
+    sys_coproc_write_raw!(u64, "S3_4_C1_C1_5", "x");
+}
+
+pub const HFGWTR_EL2: Reg = Reg {};