From 002dce0033b44683a0c1660093e45474fe75c84c Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Tue, 12 Mar 2019 19:54:51 +0000 Subject: [PATCH 1/4] Add thumbv8m.main support. Add feature flags into build.rs so SecureFault gets included. --- assemble.sh | 3 +++ bin/thumbv6m-none-eabi.a | Bin 940 -> 940 bytes bin/thumbv7em-none-eabi.a | Bin 940 -> 940 bytes bin/thumbv7em-none-eabihf.a | Bin 940 -> 940 bytes bin/thumbv7m-none-eabi.a | Bin 940 -> 940 bytes bin/thumbv8m.base-none-eabi.a | Bin 944 -> 944 bytes bin/thumbv8m.main-none-eabi.a | Bin 0 -> 944 bytes build.rs | 30 +++++++++++++++++++----------- 8 files changed, 22 insertions(+), 11 deletions(-) create mode 100644 bin/thumbv8m.main-none-eabi.a diff --git a/assemble.sh b/assemble.sh index 27c10de3..bd04c5bc 100755 --- a/assemble.sh +++ b/assemble.sh @@ -22,4 +22,7 @@ ar crs bin/thumbv7em-none-eabihf.a bin/$crate.o arm-none-eabi-as -march=armv8-m.base asm.s -o bin/$crate.o ar crs bin/thumbv8m.base-none-eabi.a bin/$crate.o +arm-none-eabi-as -march=armv8-m.main asm.s -o bin/$crate.o +ar crs bin/thumbv8m.main-none-eabi.a bin/$crate.o + rm bin/$crate.o diff --git a/bin/thumbv6m-none-eabi.a b/bin/thumbv6m-none-eabi.a index 6a6a54702f4eb87c5ea0161a92a9e0bdb4ca22cb..51c1dc01be9a4227c8a4d911bb953c91a31dfae6 100644 GIT binary patch delta 32 ocmZ3(zJ`6mIY#!4=XIGFIVS&QGN0VStTEYyS%Q&svM;ka0JNV8mH+?% delta 32 ocmZ3(zJ`6mIY!Qn=XIGF*(d*HGM^m7EWyYzxs=&_vI(;W0J3QbmH+?% diff --git a/bin/thumbv7em-none-eabi.a b/bin/thumbv7em-none-eabi.a index 51d9aef4767948e5b33318aa4b2f00d22b811e92..6daed97b9631a3966f5f882ef914f7adb7cad5ee 100644 GIT binary patch delta 32 ocmZ3(zJ`6mIY#!4=XIGFIVS&QGN0VStTEYyS%Q&svM;ka0JNV8mH+?% delta 32 ocmZ3(zJ`6mIY!Qn=XIGF*(d*HGM^m7EWyYzxs=&_vI(;W0J3QbmH+?% diff --git a/bin/thumbv7em-none-eabihf.a b/bin/thumbv7em-none-eabihf.a index 51d9aef4767948e5b33318aa4b2f00d22b811e92..6daed97b9631a3966f5f882ef914f7adb7cad5ee 100644 GIT binary patch delta 32 ocmZ3(zJ`6mIY#!4=XIGFIVS&QGN0VStTEYyS%Q&svM;ka0JNV8mH+?% delta 32 ocmZ3(zJ`6mIY!Qn=XIGF*(d*HGM^m7EWyYzxs=&_vI(;W0J3QbmH+?% diff --git a/bin/thumbv7m-none-eabi.a b/bin/thumbv7m-none-eabi.a index dc37fbf0404c2a27212652a1fb72b009e3b2d193..d6da5d8ffcb1a10c112e4466accadff3b064be57 100644 GIT binary patch delta 32 ocmZ3(zJ`6mIY#!4=XIGFIVS&QGN0VStTEYyS%Q&svM;ka0JNV8mH+?% delta 32 ocmZ3(zJ`6mIY!Qn=XIGF*(d*HGM^m7EWyYzxs=&_vI(;W0J3QbmH+?% diff --git a/bin/thumbv8m.base-none-eabi.a b/bin/thumbv8m.base-none-eabi.a index dda8dcc75a9d831309f2498525f6d5ace57c30eb..e8fd3686dada47bc451ef279dd99a0e3fc9213c9 100644 GIT binary patch delta 32 ocmdnMzJYzhIY#!4=M9+{IVLkQn@{dw)|hO;EWyY*Igr^L0Hvo0vj6}9 delta 32 ncmdnMzJYzhIY!Qn=M9+{*(WnHn@>()mSE(VTnS`ZFlzt+qiG1U diff --git a/bin/thumbv8m.main-none-eabi.a b/bin/thumbv8m.main-none-eabi.a new file mode 100644 index 0000000000000000000000000000000000000000..9335af0807e57e3efaf1476a85696a15ec3943d8 GIT binary patch literal 944 zcma)3PfG$(5T9-RyL8AX2nt#w$b-Hlq&!4qpcu3rqVB%c4Fyek`-D2xp%2hk>r-^} z;H6VEvu~e0MWKQD|9dm@X7cA;w7VD1u{%#?!&SB^UH7D_0WAjrEaX;`i%x@&`|@7! z!D!g;Jq6Gn3K=|?1|=cc5Sy&3ds?YP1<$IwaLakE-!v?XN-MIU5H-^NyGkW1QJ?@0 zq+!%ZWo=z=nYQOT0@$!N z2eUC^k`0N47YQ?s=oBKt5!-r6Eg zU;7Ag_`TV7SK-QWJ+to?#x&`^MGRz-FXO}>Hlkfq54s02*>z-`ZG literal 0 HcmV?d00001 diff --git a/build.rs b/build.rs index a9781463..9d069359 100644 --- a/build.rs +++ b/build.rs @@ -8,7 +8,6 @@ fn main() { let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap()); has_fpu(&target); - let is_armv6m = is_armv6m(&target); if target.starts_with("thumbv") { fs::copy( @@ -43,7 +42,21 @@ INCLUDE device.x"# f }; - let max_int_handlers = if is_armv6m { 32 } else { 240 }; + let max_int_handlers = if target.starts_with("thumbv6m-") { + println!("cargo:rustc-cfg=cortex_m"); + println!("cargo:rustc-cfg=armv6m"); + 32 + } else if target.starts_with("thumbv7m-") || target.starts_with("thumbv7em-") { + println!("cargo:rustc-cfg=cortex_m"); + println!("cargo:rustc-cfg=armv7m"); + 240 + } else if target.starts_with("thumbv8m") { + println!("cargo:rustc-cfg=cortex_m"); + println!("cargo:rustc-cfg=armv8m"); + 240 + } else { + panic!("Unexpected target {:?}", target); + }; // checking the size of the interrupts portion of the vector table is sub-architecture dependent writeln!( @@ -58,6 +71,10 @@ handlers."); max_int_handlers ).unwrap(); + if target.ends_with("-eabihf") { + println!("cargo:rustc-cfg=has_fpu"); + } + println!("cargo:rustc-link-search={}", out.display()); println!("cargo:rerun-if-changed=build.rs"); @@ -69,12 +86,3 @@ fn has_fpu(target: &str) { println!("cargo:rustc-cfg=has_fpu"); } } - -fn is_armv6m(target: &str) -> bool { - if target.starts_with("thumbv6m-") { - println!("cargo:rustc-cfg=armv6m"); - true - } else { - false - } -} From 6e072a76bd93d2787323a0200bf9411757b11aac Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Sat, 16 Mar 2019 21:47:03 +0000 Subject: [PATCH 2/4] Build on x86 (even if that's weird for a Cortex-M support crate) --- build.rs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/build.rs b/build.rs index 9d069359..5a8fb9c5 100644 --- a/build.rs +++ b/build.rs @@ -55,7 +55,9 @@ INCLUDE device.x"# println!("cargo:rustc-cfg=armv8m"); 240 } else { - panic!("Unexpected target {:?}", target); + // Non ARM target. We assume you're just testing the syntax. + // This value seems as soon as any + 240 }; // checking the size of the interrupts portion of the vector table is sub-architecture dependent From d24d3e6bba5a8ff6150f337078631045e2d2f1bd Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Sat, 16 Mar 2019 22:00:32 +0000 Subject: [PATCH 3/4] Add thumv8m.main-none-eabi to Travis test matrix --- .travis.yml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/.travis.yml b/.travis.yml index f28520bf..e53d7a69 100644 --- a/.travis.yml +++ b/.travis.yml @@ -22,6 +22,10 @@ matrix: rust: stable if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master) + - env: TARGET=thumbv8m.main-none-eabi + rust: stable + if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master) + - env: TARGET=x86_64-unknown-linux-gnu rust: nightly if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master) @@ -42,6 +46,10 @@ matrix: rust: nightly if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master) + - env: TARGET=thumbv8m.main-none-eabi + rust: nightly + if: (branch = staging OR branch = trying) OR (type = pull_request AND branch = master) + before_install: set -e install: From 5027cea0bbfcc8188f162a61094b22d5bddf7949 Mon Sep 17 00:00:00 2001 From: Jonathan 'theJPster' Pallant Date: Sat, 16 Mar 2019 22:46:18 +0000 Subject: [PATCH 4/4] Bump cortex-m dev-dep to 0.6 (it's only a dev-dep and so doesn't affect other packages) Disable the semihosting test on thumbv8, as it's currently unsupported in cortex-m-semihosting --- Cargo.toml | 15 +++++++++++++-- examples/qemu.rs | 19 +++++++++++++++---- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/Cargo.toml b/Cargo.toml index 949bdadc..29310d7c 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -19,10 +19,21 @@ autoexamples = true r0 = "0.2.2" cortex-m-rt-macros = { path = "macros", version = "0.1.5" } +[target.thumbv7em-none-eabihf.dev-dependencies] +cortex-m-semihosting = "0.3.1" + +[target.thumbv7em-none-eabi.dev-dependencies] +cortex-m-semihosting = "0.3.1" + +[target.thumbv7m-none-eabi.dev-dependencies] +cortex-m-semihosting = "0.3.1" + +[target.thumbv6m-none-eabi.dev-dependencies] +cortex-m-semihosting = "0.3.1" + [dev-dependencies] -cortex-m = ">= 0.5.7, <0.7" +cortex-m = "0.6" panic-halt = "0.2.0" -cortex-m-semihosting = "0.3.1" [dev-dependencies.rand] default-features = false diff --git a/examples/qemu.rs b/examples/qemu.rs index e2cd895c..7553e70b 100644 --- a/examples/qemu.rs +++ b/examples/qemu.rs @@ -2,18 +2,22 @@ #![no_main] #![no_std] -extern crate cortex_m; +extern crate cortex_m; extern crate cortex_m_rt as rt; + +#[cfg(not(armv8m))] extern crate cortex_m_semihosting as semihosting; + extern crate panic_halt; -use core::fmt::Write; use cortex_m::asm; use rt::entry; +#[cfg(not(armv8m))] #[entry] fn main() -> ! { + use core::fmt::Write; let x = 42; loop { @@ -21,9 +25,16 @@ fn main() -> ! { // write something through semihosting interface let mut hstdout = semihosting::hio::hstdout().unwrap(); - write!(hstdout, "x = {}\n", x); - + write!(hstdout, "x = {}\n", x).unwrap(); // exit from qemu semihosting::debug::exit(semihosting::debug::EXIT_SUCCESS); } } + +#[cfg(armv8m)] +#[entry] +fn main() -> ! { + loop { + asm::nop(); + } +}