move non Cortex-M specific bits into a crate

closes #50

Author: japaric

Cargo.toml

@@ -10,5 +10,6 @@ repository = "https://github.com/japaric/cortex-m"
 version = "0.3.0"
 
 [dependencies]
+mcu = { git = "https://github.com/japaric/mcu" }
 aligned = "0.1.1"
 volatile-register = "0.2.0"

src/interrupt.rs

@@ -1,40 +1,6 @@
 //! Interrupts
 
-use core::cell::UnsafeCell;
-
-/// A "mutex" based on critical sections
-pub struct Mutex<T> {
-    inner: UnsafeCell<T>,
-}
-
-impl<T> Mutex<T> {
-    /// Creates a new mutex
-    pub const fn new(value: T) -> Self {
-        Mutex { inner: UnsafeCell::new(value) }
-    }
-}
-
-impl<T> Mutex<T> {
-    /// Borrows the data for the duration of the critical section
-    pub fn borrow<'cs>(&self, _ctxt: &'cs CriticalSection) -> &'cs T {
-        unsafe { &*self.inner.get() }
-    }
-}
-
-/// Interrupt number
-pub unsafe trait Nr {
-    /// Returns the number associated with this interrupt
-    fn nr(&self) -> u8;
-}
-
-// NOTE `Mutex` can be used as a channel so, the protected data must be `Send`
-// to prevent sending non-Sendable stuff (e.g. interrupt tokens) across
-// different execution contexts (e.g. interrupts)
-unsafe impl<T> Sync for Mutex<T>
-where
-    T: Send,
-{
-}
+pub use mcu::{CriticalSection, Mutex, Nr};
 
 /// Disables all interrupts
 #[inline(always)]
@@ -74,13 +40,6 @@ pub unsafe fn enable() {
     }
 }
 
-/// Critical section context
-///
-/// Indicates that you are executing code within a critical section
-pub struct CriticalSection {
-    _0: (),
-}
-
 /// Execute closure `f` in an interrupt-free context.
 ///
 /// This as also known as a "critical section".
@@ -93,7 +52,7 @@ where
     // disable interrupts
     disable();
 
-    let r = f(&CriticalSection { _0: () });
+    let r = f(unsafe { &CriticalSection::new() });
 
     // If the interrupts were active before our `disable` call, then re-enable
     // them. Otherwise, keep them disabled

src/lib.rs

@@ -15,6 +15,7 @@
 #![no_std]
 
 extern crate aligned;
+extern crate mcu;
 extern crate volatile_register;
 
 #[macro_use]

src/peripheral/mod.rs

@@ -5,12 +5,12 @@
 //! - ARMv7-M Architecture Reference Manual (Issue E.b) - Chapter B3
 
 use core::cell::UnsafeCell;
-use core::marker::PhantomData;
 use core::ptr;
 
+pub use mcu::Peripheral;
 use volatile_register::{RO, RW, WO};
 
-use interrupt::{CriticalSection, Nr};
+use interrupt::Nr;
 
 #[cfg(test)]
 mod test;
@@ -54,38 +54,6 @@ pub const CBP: Peripheral<CBP> = unsafe { Peripheral::new(0xE000_EF50) };
 
 // TODO stand-alone registers: ICTR, ACTLR and STIR
 
-/// A peripheral
-#[derive(Debug)]
-pub struct Peripheral<T>
-where
-    T: 'static,
-{
-    address: usize,
-    _marker: PhantomData<&'static mut T>,
-}
-
-impl<T> Peripheral<T> {
-    /// Creates a new peripheral
-    ///
-    /// `address` is the base address of the register block
-    pub const unsafe fn new(address: usize) -> Self {
-        Peripheral {
-            address: address,
-            _marker: PhantomData,
-        }
-    }
-
-    /// Borrows the peripheral for the duration of a critical section
-    pub fn borrow<'cs>(&self, _ctxt: &'cs CriticalSection) -> &'cs T {
-        unsafe { &*self.get() }
-    }
-
-    /// Returns a pointer to the register block
-    pub fn get(&self) -> *mut T {
-        self.address as *mut T
-    }
-}
-
 /// CPUID register block
 #[repr(C)]
 pub struct CPUID {