From 19d35340e77ec9ed11ec44f44a2047148a15f66e Mon Sep 17 00:00:00 2001 From: qwerty19106 Date: Mon, 24 Sep 2018 13:29:50 +0400 Subject: [PATCH 1/5] Added Pending SV (Service Call) and SysTick flags --- src/peripheral/scb.rs | 56 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 939d5a78..31c6861d 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -297,6 +297,12 @@ impl VectActive { mod scb_consts { pub const SCB_CCR_IC_MASK: u32 = (1 << 17); pub const SCB_CCR_DC_MASK: u32 = (1 << 16); + + pub const SCB_ICSR_PENDSVSET_MASK: u32 = 1 << 28; + pub const SCB_ICSR_PENDSVCLR_MASK: u32 = 1 << 27; + + pub const SCB_ICSR_PENDSTSET_MASK: u32 = 1 << 26; + pub const SCB_ICSR_PENDSTCLR_MASK: u32 = 1 << 25; } #[cfg(not(armv6m))] @@ -576,6 +582,56 @@ impl SCB { ::asm::dsb(); ::asm::isb(); } + + /// Pending SV Flag + /// + /// return true if PendSV exception is pending, otherwise false + #[inline] + pub fn is_pendsv() -> bool { + // NOTE(unsafe) atomic read with no side effects + unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET_MASK != 0 } + } + + /// Changes PendSV exception state to pending Set Pending SV Flag + #[inline] + pub fn set_pendsv(&mut self) { + unsafe { + self.icsr.write(SCB_ICSR_PENDSVSET_MASK); + } + } + + /// Removes the pending state from the PendSV exception + #[inline] + pub fn clear_pendsv(&mut self) { + unsafe { + self.icsr.write(SCB_ICSR_PENDSVCLR_MASK); + } + } + + /// ICSR SysTick flag + /// + /// return true if SysTick exception is pending, otherwise false + #[inline] + pub fn is_systick_pending() -> bool { + // NOTE(unsafe) atomic read with no side effects + unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET_MASK != 0 } + } + + /// Changes SysTick exception state to pending + #[inline] + pub fn set_systick_pending(&mut self) { + unsafe { + self.icsr.write(SCB_ICSR_PENDSTSET_MASK); + } + } + + /// Removes the pending state from the SysTick exception + #[inline] + pub fn clear_systick_pending(&mut self) { + unsafe { + self.icsr.write(SCB_ICSR_PENDSTCLR_MASK); + } + } } const SCB_SCR_SLEEPDEEP: u32 = 0x1 << 2; From 454bb4ee49be3f877a5df4a85b295c840b735f9d Mon Sep 17 00:00:00 2001 From: qwerty19106 Date: Mon, 24 Sep 2018 19:01:37 +0400 Subject: [PATCH 2/5] Fix duplicate PendSV. --- src/peripheral/scb.rs | 84 +++++++++++++++---------------------------- 1 file changed, 28 insertions(+), 56 deletions(-) diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 31c6861d..cb004549 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -297,12 +297,6 @@ impl VectActive { mod scb_consts { pub const SCB_CCR_IC_MASK: u32 = (1 << 17); pub const SCB_CCR_DC_MASK: u32 = (1 << 16); - - pub const SCB_ICSR_PENDSVSET_MASK: u32 = 1 << 28; - pub const SCB_ICSR_PENDSVCLR_MASK: u32 = 1 << 27; - - pub const SCB_ICSR_PENDSTSET_MASK: u32 = 1 << 26; - pub const SCB_ICSR_PENDSTCLR_MASK: u32 = 1 << 25; } #[cfg(not(armv6m))] @@ -582,56 +576,6 @@ impl SCB { ::asm::dsb(); ::asm::isb(); } - - /// Pending SV Flag - /// - /// return true if PendSV exception is pending, otherwise false - #[inline] - pub fn is_pendsv() -> bool { - // NOTE(unsafe) atomic read with no side effects - unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET_MASK != 0 } - } - - /// Changes PendSV exception state to pending Set Pending SV Flag - #[inline] - pub fn set_pendsv(&mut self) { - unsafe { - self.icsr.write(SCB_ICSR_PENDSVSET_MASK); - } - } - - /// Removes the pending state from the PendSV exception - #[inline] - pub fn clear_pendsv(&mut self) { - unsafe { - self.icsr.write(SCB_ICSR_PENDSVCLR_MASK); - } - } - - /// ICSR SysTick flag - /// - /// return true if SysTick exception is pending, otherwise false - #[inline] - pub fn is_systick_pending() -> bool { - // NOTE(unsafe) atomic read with no side effects - unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET_MASK != 0 } - } - - /// Changes SysTick exception state to pending - #[inline] - pub fn set_systick_pending(&mut self) { - unsafe { - self.icsr.write(SCB_ICSR_PENDSTSET_MASK); - } - } - - /// Removes the pending state from the SysTick exception - #[inline] - pub fn clear_systick_pending(&mut self) { - unsafe { - self.icsr.write(SCB_ICSR_PENDSTCLR_MASK); - } - } } const SCB_SCR_SLEEPDEEP: u32 = 0x1 << 2; @@ -675,6 +619,9 @@ impl SCB { const SCB_ICSR_PENDSVSET: u32 = 1 << 28; const SCB_ICSR_PENDSVCLR: u32 = 1 << 27; +const SCB_ICSR_PENDSTSET: u32 = 1 << 26; +const SCB_ICSR_PENDSTCLR: u32 = 1 << 25; + impl SCB { /// Set the PENDSVSET bit in the ICSR register which will pend the PendSV interrupt pub fn set_pendsv() { @@ -696,4 +643,29 @@ impl SCB { (*Self::ptr()).icsr.write(SCB_ICSR_PENDSVCLR); } } + + /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt + #[inline] + pub fn set_systick(&mut self) { + unsafe { + (*Self::ptr()).icsr.write(SCB_ICSR_PENDSTSET); + } + } + + /// Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending + #[inline] + pub fn is_systick_pending() -> bool { + unsafe { + (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET + } + } + + + /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt + #[inline] + pub fn clear_systick_pending(&mut self) { + unsafe { + (*Self::ptr()).icsr.write(SCB_ICSR_PENDSTCLR); + } + } } From d9ad9d48bbfc494f18b0f51c0249af2178fe91df Mon Sep 17 00:00:00 2001 From: qwerty19106 Date: Mon, 1 Oct 2018 11:37:25 +0400 Subject: [PATCH 3/5] Fix function names and remove exclusive access --- src/peripheral/scb.rs | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index cb004549..8e2e7af4 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -646,7 +646,7 @@ impl SCB { /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt #[inline] - pub fn set_systick(&mut self) { + pub fn set_pendst() { unsafe { (*Self::ptr()).icsr.write(SCB_ICSR_PENDSTSET); } @@ -654,7 +654,7 @@ impl SCB { /// Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending #[inline] - pub fn is_systick_pending() -> bool { + pub fn is_pendst_pending() -> bool { unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET } @@ -663,7 +663,7 @@ impl SCB { /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt #[inline] - pub fn clear_systick_pending(&mut self) { + pub fn clear_pendst() { unsafe { (*Self::ptr()).icsr.write(SCB_ICSR_PENDSTCLR); } From fac7e856f75e5ceff87d2e1107ffd683117f6e15 Mon Sep 17 00:00:00 2001 From: qwerty19106 Date: Mon, 1 Oct 2018 12:10:12 +0400 Subject: [PATCH 4/5] Remove blank line --- src/peripheral/scb.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 8e2e7af4..14eaa695 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -660,7 +660,6 @@ impl SCB { } } - /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt #[inline] pub fn clear_pendst() { From 2cb6f4ba35b40337d6406acf5b565ccd0fb652c0 Mon Sep 17 00:00:00 2001 From: qwerty19106 Date: Mon, 1 Oct 2018 12:20:34 +0400 Subject: [PATCH 5/5] Autoformat scb.rs by rustfmt --- src/peripheral/scb.rs | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs index 14eaa695..e773c9c7 100644 --- a/src/peripheral/scb.rs +++ b/src/peripheral/scb.rs @@ -7,9 +7,9 @@ use volatile_register::RW; #[cfg(not(armv6m))] use super::cpuid::CsselrCacheType; #[cfg(not(armv6m))] -use super::CPUID; -#[cfg(not(armv6m))] use super::CBP; +#[cfg(not(armv6m))] +use super::CPUID; use super::SCB; /// Register block @@ -604,13 +604,18 @@ impl SCB { /// Initiate a system reset request to reset the MCU pub fn system_reset(&mut self) -> ! { ::asm::dsb(); - unsafe { self.aircr.modify(|r| - SCB_AIRCR_VECTKEY | // otherwise the write is ignored + unsafe { + self.aircr.modify( + |r| { + SCB_AIRCR_VECTKEY | // otherwise the write is ignored r & SCB_AIRCR_PRIGROUP_MASK | // keep priority group unchanged - SCB_AIRCR_SYSRESETREQ // set the bit - ) }; + SCB_AIRCR_SYSRESETREQ + }, // set the bit + ) + }; ::asm::dsb(); - loop { // wait for the reset + loop { + // wait for the reset ::asm::nop(); // avoid rust-lang/rust#28728 } } @@ -632,9 +637,7 @@ impl SCB { /// Check if PENDSVSET bit in the ICSR register is set meaning PendSV interrupt is pending pub fn is_pendsv_pending() -> bool { - unsafe { - (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET - } + unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSVSET == SCB_ICSR_PENDSVSET } } /// Set the PENDSVCLR bit in the ICSR register which will clear a pending PendSV interrupt @@ -655,9 +658,7 @@ impl SCB { /// Check if PENDSTSET bit in the ICSR register is set meaning SysTick interrupt is pending #[inline] pub fn is_pendst_pending() -> bool { - unsafe { - (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET - } + unsafe { (*Self::ptr()).icsr.read() & SCB_ICSR_PENDSTSET == SCB_ICSR_PENDSTSET } } /// Set the PENDSTCLR bit in the ICSR register which will clear a pending SysTick interrupt