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| 1 | +//! Blocking I2C API |
| 2 | +
|
| 3 | +/// Blocking read |
| 4 | +pub trait Read { |
| 5 | + /// Error type |
| 6 | + type Error; |
| 7 | + |
| 8 | + /// Reads enough bytes from slave with `address` to fill `buffer` |
| 9 | + /// |
| 10 | + /// # I2C Events (contract) |
| 11 | + /// |
| 12 | + /// ``` text |
| 13 | + /// Master: ST SAD+R MAK MAK ... NMAK SP |
| 14 | + /// Slave: SAK B0 B1 ... BN |
| 15 | + /// ``` |
| 16 | + /// |
| 17 | + /// Where |
| 18 | + /// |
| 19 | + /// - `ST` = start condition |
| 20 | + /// - `SAD+R` = slave address with 8th bit set to 1 |
| 21 | + /// - `SAK` = slave acknowledge |
| 22 | + /// - `Bi` = ith byte of data |
| 23 | + /// - `MAK` = master acknowledge |
| 24 | + /// - `NMAK` = master no acknowledge |
| 25 | + /// - `SP` = stop condition |
| 26 | + fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error>; |
| 27 | +} |
| 28 | + |
| 29 | +/// Blocking write |
| 30 | +pub trait Write { |
| 31 | + /// Error type |
| 32 | + type Error; |
| 33 | + |
| 34 | + /// Sends bytes to slave with address `addr` |
| 35 | + /// |
| 36 | + /// # I2C Events (contract) |
| 37 | + /// |
| 38 | + /// ``` text |
| 39 | + /// Master: ST SAD+W B0 B1 ... BN SP |
| 40 | + /// Slave: SAK SAK SAK ... SAK |
| 41 | + /// ``` |
| 42 | + /// |
| 43 | + /// Where |
| 44 | + /// |
| 45 | + /// - `ST` = start condition |
| 46 | + /// - `SAD+W` = slave address with 8th bit set to 0 |
| 47 | + /// - `SAK` = slave acknowledge |
| 48 | + /// - `Bi` = ith byte of data |
| 49 | + /// - `SP` = stop condition |
| 50 | + fn write(&mut self, addr: u8, bytes: &[u8]) -> Result<(), Self::Error>; |
| 51 | +} |
| 52 | + |
| 53 | +/// Blocking write + read |
| 54 | +pub trait WriteRead { |
| 55 | + /// Error type |
| 56 | + type Error; |
| 57 | + |
| 58 | + /// Sends bytes to slave with address `addr` and then reads enough bytes to fill `buffer` *in a |
| 59 | + /// single transaction* |
| 60 | + /// |
| 61 | + /// # I2C Events (contract) |
| 62 | + /// |
| 63 | + /// ``` text |
| 64 | + /// Master: ST SAD+W O0 O1 ... OM SR SAD+R MAK MAK ... NMAK SP |
| 65 | + /// Slave: SAK SAK SAK ... SAK SAK I0 I1 ... IN |
| 66 | + /// ``` |
| 67 | + /// |
| 68 | + /// Where |
| 69 | + /// |
| 70 | + /// - `ST` = start condition |
| 71 | + /// - `SAD+W` = slave address with 8th bit set to 0 |
| 72 | + /// - `SAK` = slave acknowledge |
| 73 | + /// - `Oi` = ith outgoing byte of data |
| 74 | + /// - `SR` = repeated start condition |
| 75 | + /// - `SAD+R` = slave address with 8th bit set to 1 |
| 76 | + /// - `Ii` = ith incoming byte of data |
| 77 | + /// - `MAK` = master acknowledge |
| 78 | + /// - `NMAK` = master no acknowledge |
| 79 | + /// - `SP` = stop condition |
| 80 | + fn write_read( |
| 81 | + &mut self, |
| 82 | + address: u8, |
| 83 | + bytes: &[u8], |
| 84 | + buffer: &mut [u8], |
| 85 | + ) -> Result<(), Self::Error>; |
| 86 | +} |
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