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src/generate/register.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,8 @@ pub fn render(
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&self.bits
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}
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}
66-
impl vcell::FromBits<#rty> for R {
67-
fn from_bits(bits: #rty) -> Self {
66+
impl core::convert::Into<R> for #rty {
67+
fn into(bits: #rty) -> Self {
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Self { bits }
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}
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}
@@ -91,8 +91,8 @@ pub fn render(
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&self.bits
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}
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}
94-
impl vcell::FromBits<#rty> for W {
95-
fn from_bits(bits: #rty) -> Self {
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impl core::convert::Into<W> for #rty {
95+
fn into(bits: #rty) -> Self {
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Self { bits }
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}
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}

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