From 0efab66edeeec1d346ee6933196178c13b57b019 Mon Sep 17 00:00:00 2001 From: Daniel Egger Date: Sun, 28 Jul 2019 20:24:57 +0200 Subject: [PATCH 1/8] Get rid of #[macro_use] Signed-off-by: Daniel Egger --- ci/svd2rust-regress/src/main.rs | 1 - 1 file changed, 1 deletion(-) diff --git a/ci/svd2rust-regress/src/main.rs b/ci/svd2rust-regress/src/main.rs index ccd5a223..0b1d82b0 100644 --- a/ci/svd2rust-regress/src/main.rs +++ b/ci/svd2rust-regress/src/main.rs @@ -3,7 +3,6 @@ extern crate error_chain; extern crate inflections; extern crate rayon; extern crate reqwest; -#[macro_use] extern crate structopt; mod errors; From 4b765b61f4e53d9b9221e156bcd3d95f86b27b0c Mon Sep 17 00:00:00 2001 From: Daniel Egger Date: Sun, 28 Jul 2019 20:25:19 +0200 Subject: [PATCH 2/8] Replace deprecated trim_right() by trim_end() Signed-off-by: Daniel Egger --- ci/svd2rust-regress/src/main.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci/svd2rust-regress/src/main.rs b/ci/svd2rust-regress/src/main.rs index 0b1d82b0..ef90ee7e 100644 --- a/ci/svd2rust-regress/src/main.rs +++ b/ci/svd2rust-regress/src/main.rs @@ -284,7 +284,7 @@ fn main() { "Failed: {} - {} seconds. {}{}", t.name(), start.elapsed().as_secs(), - e.display_chain().to_string().trim_right(), + e.display_chain().to_string().trim_end(), additional_info, ); } From dbdd6304ed0814d07cfde561abad53414fb01b99 Mon Sep 17 00:00:00 2001 From: Daniel Egger Date: Sun, 28 Jul 2019 20:26:20 +0200 Subject: [PATCH 3/8] The manufacturer is called NXP not Nxp I wonder how that might have ever resulted in a working URL Signed-off-by: Daniel Egger --- ci/svd2rust-regress/src/tests.rs | 40 ++++++++++++++++---------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/ci/svd2rust-regress/src/tests.rs b/ci/svd2rust-regress/src/tests.rs index 32d382cc..efeb8225 100644 --- a/ci/svd2rust-regress/src/tests.rs +++ b/ci/svd2rust-regress/src/tests.rs @@ -17,7 +17,7 @@ pub enum Manufacturer { Holtek, Nordic, Nuvoton, - Nxp, + NXP, SiliconLabs, Spansion, STMicro, @@ -2736,7 +2736,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ // BAD-SVD two enumeratedValues have the same name &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC11Exx_v5", svd_url: None, should_pass: false, @@ -2744,7 +2744,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC11Uxx_v7", svd_url: None, should_pass: false, @@ -2752,7 +2752,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC11xx_v6a", svd_url: None, should_pass: false, @@ -2760,7 +2760,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC11xx_v6", svd_url: None, should_pass: false, @@ -2768,7 +2768,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC13Uxx_v1", svd_url: None, should_pass: false, @@ -2776,7 +2776,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC15xx_v0.7", svd_url: None, should_pass: false, @@ -2784,7 +2784,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC800_v0.3", svd_url: None, should_pass: false, @@ -2792,7 +2792,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC11E6x_v0.8", svd_url: None, should_pass: false, @@ -2800,7 +2800,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC176x5x_v0.2", svd_url: None, should_pass: false, @@ -2808,7 +2808,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC11Cxx_v9", svd_url: None, should_pass: false, @@ -2817,7 +2817,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ // BAD-SVD missing resetValue &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC178x_7x", svd_url: None, should_pass: false, @@ -2825,7 +2825,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC178x_7x_v0.8", svd_url: None, should_pass: false, @@ -2833,7 +2833,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC408x_7x_v0.7", svd_url: None, should_pass: false, @@ -2841,7 +2841,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC11Axxv0.6", svd_url: None, should_pass: false, @@ -2850,7 +2850,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ // BAD-SVD bad identifier: contains a '.' &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC11D14_svd_v4", svd_url: None, should_pass: false, @@ -2858,7 +2858,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC13xx_svd_v1", svd_url: None, should_pass: false, @@ -2867,7 +2867,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ // BAD-SVD bad identifier: contains a '/' &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC18xx_svd_v18", svd_url: None, should_pass: false, @@ -2884,7 +2884,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ // BAD-SVD uses the identifier '_' to name a reserved bitfield value &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC1102_4_v4", svd_url: None, should_pass: false, @@ -2894,7 +2894,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ // #99 regression test &TestCase { arch: CortexM, - mfgr: Nxp, + mfgr: NXP, chip: "LPC5410x_v0.4", svd_url: None, should_pass: false, From a24a5881de9e0e1ee68701eb70ab7e7bbe7817b1 Mon Sep 17 00:00:00 2001 From: Daniel Egger Date: Sun, 28 Jul 2019 20:28:21 +0200 Subject: [PATCH 4/8] Use the correct base URL for file download Signed-off-by: Daniel Egger --- ci/svd2rust-regress/src/tests.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci/svd2rust-regress/src/tests.rs b/ci/svd2rust-regress/src/tests.rs index efeb8225..ab9d6c8a 100644 --- a/ci/svd2rust-regress/src/tests.rs +++ b/ci/svd2rust-regress/src/tests.rs @@ -48,7 +48,7 @@ impl TestCase { pub fn svd_url(&self) -> String { match self.svd_url { Some(u) => u.to_owned(), - None => format!("https://raw.githubusercontent.com/posborne/cmsis-svd/python-0.4/data/{vendor:?}/{chip}.svd", + None => format!("https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/{vendor:?}/{chip}.svd", vendor = self.mfgr, chip = self.chip ) From e1c21b406d01a208f40b8bba6993158c62ebce6e Mon Sep 17 00:00:00 2001 From: Daniel Egger Date: Sun, 28 Jul 2019 20:29:07 +0200 Subject: [PATCH 5/8] Replace "." in weirly name chip names by "_" so cargo init works Signed-off-by: Daniel Egger --- ci/svd2rust-regress/src/tests.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ci/svd2rust-regress/src/tests.rs b/ci/svd2rust-regress/src/tests.rs index ab9d6c8a..7f3d1011 100644 --- a/ci/svd2rust-regress/src/tests.rs +++ b/ci/svd2rust-regress/src/tests.rs @@ -64,7 +64,7 @@ impl TestCase { } pub fn name(&self) -> String { - format!("{:?}-{}", self.mfgr, self.chip).to_sanitized_snake_case() + format!("{:?}-{}", self.mfgr, self.chip.replace(".", "_")).to_sanitized_snake_case() } } From cddba105b0c40e38b5f94eb77a15a536c7a68122 Mon Sep 17 00:00:00 2001 From: Daniel Egger Date: Sun, 28 Jul 2019 20:30:02 +0200 Subject: [PATCH 6/8] Fix one NXP chip and added 3 more which actually compile Signed-off-by: Daniel Egger --- ci/svd2rust-regress/src/tests.rs | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/ci/svd2rust-regress/src/tests.rs b/ci/svd2rust-regress/src/tests.rs index 7f3d1011..2e51ffca 100644 --- a/ci/svd2rust-regress/src/tests.rs +++ b/ci/svd2rust-regress/src/tests.rs @@ -2875,8 +2875,8 @@ pub const TESTS: &'static [&'static TestCase] = &[ }, &TestCase { arch: CortexM, - mfgr: Nxp, - chip: "LPC43xx_svd_v5", + mfgr: NXP, + chip: "LPC43xx_43Sxx", svd_url: None, should_pass: false, run_when: Never, @@ -2900,6 +2900,30 @@ pub const TESTS: &'static [&'static TestCase] = &[ should_pass: false, run_when: Never, }, + &TestCase { + arch: CortexM, + mfgr: NXP, + chip: "MK22F25612", + svd_url: None, + should_pass: true, + run_when: NotShort, + }, + &TestCase { + arch: CortexM, + mfgr: NXP, + chip: "MK22F51212", + svd_url: None, + should_pass: true, + run_when: NotShort, + }, + &TestCase { + arch: CortexM, + mfgr: NXP, + chip: "MKW41Z4", + svd_url: None, + should_pass: true, + run_when: NotShort, + }, &TestCase { arch: CortexM, mfgr: SiliconLabs, From babadce7826c5a1ab938e797493f6e87f726eaec Mon Sep 17 00:00:00 2001 From: Daniel Egger Date: Sun, 28 Jul 2019 21:24:04 +0200 Subject: [PATCH 7/8] Fixed STM testcases and added a lot more Signed-off-by: Daniel Egger --- ci/svd2rust-regress/src/tests.rs | 132 ++++++++++++++++++++++++++----- 1 file changed, 114 insertions(+), 18 deletions(-) diff --git a/ci/svd2rust-regress/src/tests.rs b/ci/svd2rust-regress/src/tests.rs index 2e51ffca..1d57872f 100644 --- a/ci/svd2rust-regress/src/tests.rs +++ b/ci/svd2rust-regress/src/tests.rs @@ -3825,7 +3825,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F301x", + chip: "STM32F301", svd_url: None, should_pass: true, run_when: Always, @@ -3833,7 +3833,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F302x", + chip: "STM32F302", svd_url: None, should_pass: true, run_when: Always, @@ -3841,7 +3841,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F303xE", + chip: "STM32F303", svd_url: None, should_pass: true, run_when: Always, @@ -3849,7 +3849,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F303x", + chip: "STM32F3x4", svd_url: None, should_pass: true, run_when: Always, @@ -3857,7 +3857,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F30x", + chip: "STM32F373", svd_url: None, should_pass: true, run_when: Always, @@ -3865,7 +3865,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F334x", + chip: "STM32F401", svd_url: None, should_pass: true, run_when: Always, @@ -3873,7 +3873,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F37x", + chip: "STM32F405", svd_url: None, should_pass: true, run_when: Always, @@ -3881,7 +3881,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F401xE", + chip: "STM32F407", svd_url: None, should_pass: true, run_when: Always, @@ -3889,7 +3889,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F401x", + chip: "STM32F410", svd_url: None, should_pass: true, run_when: Always, @@ -3897,7 +3897,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F40x", + chip: "STM32F411", svd_url: None, should_pass: true, run_when: Always, @@ -3905,7 +3905,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F411xx", + chip: "STM32F412", svd_url: None, should_pass: true, run_when: Always, @@ -3913,7 +3913,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F41x", + chip: "STM32F413", svd_url: None, should_pass: true, run_when: Always, @@ -3921,7 +3921,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F427x", + chip: "STM32F427", svd_url: None, should_pass: true, run_when: Always, @@ -3929,7 +3929,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F429x", + chip: "STM32F429", svd_url: None, should_pass: true, run_when: Always, @@ -3937,7 +3937,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F437x", + chip: "STM32F446", svd_url: None, should_pass: true, run_when: Always, @@ -3945,7 +3945,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F439x", + chip: "STM32F469", svd_url: None, should_pass: true, run_when: Always, @@ -3953,7 +3953,7 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F446x", + chip: "STM32F7x", svd_url: None, should_pass: true, run_when: Always, @@ -3961,7 +3961,103 @@ pub const TESTS: &'static [&'static TestCase] = &[ &TestCase { arch: CortexM, mfgr: STMicro, - chip: "STM32F46_79x", + chip: "STM32F7x2", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32F7x3", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32F7x5", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32F7x6", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32F7x7", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32F7x9", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32G07x", + svd_url: None, + should_pass: false, + run_when: Never, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32G431xx", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32G441xx", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32G471xx", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32G474xx", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32G483xx", + svd_url: None, + should_pass: true, + run_when: Always, + }, + &TestCase { + arch: CortexM, + mfgr: STMicro, + chip: "STM32G484xx", svd_url: None, should_pass: true, run_when: Always, From 0637dc01945278586dd09a5f9a6f347401f97fc7 Mon Sep 17 00:00:00 2001 From: Daniel Egger Date: Sun, 28 Jul 2019 21:24:28 +0200 Subject: [PATCH 8/8] Edition-2018-fied code and fixed a lot of clippy lints Signed-off-by: Daniel Egger --- ci/svd2rust-regress/Cargo.toml | 9 ++++---- ci/svd2rust-regress/src/main.rs | 11 +++------- ci/svd2rust-regress/src/svd_test.rs | 33 +++++++++++++---------------- ci/svd2rust-regress/src/tests.rs | 12 +++++------ 4 files changed, 29 insertions(+), 36 deletions(-) diff --git a/ci/svd2rust-regress/Cargo.toml b/ci/svd2rust-regress/Cargo.toml index 499861b5..bc3a1c5a 100644 --- a/ci/svd2rust-regress/Cargo.toml +++ b/ci/svd2rust-regress/Cargo.toml @@ -1,11 +1,12 @@ [package] +edition = "2018" name = "svd2rust-regress" version = "0.1.0" authors = ["James Munns ", "The svd2rust developers"] [dependencies] -reqwest = "0.8" -rayon = "1.0" +reqwest = "0.9" +rayon = "1.1" structopt = "0.2" -error-chain = "0.11" -inflections = "1.1.0" +error-chain = "0.12" +inflections = "1.1" diff --git a/ci/svd2rust-regress/src/main.rs b/ci/svd2rust-regress/src/main.rs index ef90ee7e..e92c1285 100644 --- a/ci/svd2rust-regress/src/main.rs +++ b/ci/svd2rust-regress/src/main.rs @@ -1,9 +1,5 @@ #[macro_use] extern crate error_chain; -extern crate inflections; -extern crate rayon; -extern crate reqwest; -extern crate structopt; mod errors; mod svd_test; @@ -176,8 +172,7 @@ fn main() { // FIXME: Use Option::filter instead when stable, rust-lang/rust#45860 if default_rustfmt .iter() - .filter(|p| p.is_file()) - .next() + .find(|p| p.is_file()) .is_none() { panic!("No rustfmt found"); @@ -264,8 +259,8 @@ fn main() { Err(e) => { any_fails.store(true, Ordering::Release); let additional_info = if opt.verbose > 0 { - match e.kind() { - &errors::ErrorKind::ProcessFailed(_, _, Some(ref stderr), ref previous_processes_stderr) => { + match *e.kind() { + errors::ErrorKind::ProcessFailed(_, _, Some(ref stderr), ref previous_processes_stderr) => { let mut buf = String::new(); if opt.verbose > 1 { for stderr in previous_processes_stderr { diff --git a/ci/svd2rust-regress/src/svd_test.rs b/ci/svd2rust-regress/src/svd_test.rs index ee4b5f1f..20b53ea3 100644 --- a/ci/svd2rust-regress/src/svd_test.rs +++ b/ci/svd2rust-regress/src/svd_test.rs @@ -1,10 +1,10 @@ -use errors::*; +use crate::errors::*; use reqwest; use std::fs::{self, File, OpenOptions}; use std::io::prelude::*; use std::path::PathBuf; use std::process::{Command, Output}; -use tests::TestCase; +use crate::tests::TestCase; static CRATES_ALL: &[&str] = &["bare-metal = \"0.2.0\"", "vcell = \"0.1.0\""]; static CRATES_MSP430: &[&str] = &["msp430 = \"0.1.0\""]; @@ -42,7 +42,7 @@ trait CommandHelper { name: &str, stdout: Option<&PathBuf>, stderr: Option<&PathBuf>, - previous_processes_stderr: &Vec, + previous_processes_stderr: &[PathBuf], ) -> Result<()>; } @@ -53,7 +53,7 @@ impl CommandHelper for Output { name: &str, stdout: Option<&PathBuf>, stderr: Option<&PathBuf>, - previous_processes_stderr: &Vec, + previous_processes_stderr: &[PathBuf], ) -> Result<()> { if let Some(out) = stdout { let out_payload = String::from_utf8_lossy(&self.stdout); @@ -70,7 +70,7 @@ impl CommandHelper for Output { ErrorKind::ProcessFailed(name.into(), stdout.cloned(), stderr.cloned(), - previous_processes_stderr.clone(), + previous_processes_stderr.to_vec(), ).into() ); } @@ -109,7 +109,7 @@ pub fn test(t: &TestCase, bin_path: &PathBuf, rustfmt_bin_path: Option<&PathBuf> .arg(&chip_dir) .output() .chain_err(|| "Failed to cargo init")? - .capture_outputs(true, "cargo init", None, None, &vec![])?; + .capture_outputs(true, "cargo init", None, None, &[])?; // Add some crates to the Cargo.toml of our new project let svd_toml = path_helper_base(&chip_dir, &["Cargo.toml"]); @@ -119,7 +119,7 @@ pub fn test(t: &TestCase, bin_path: &PathBuf, rustfmt_bin_path: Option<&PathBuf> .open(svd_toml) .chain_err(|| "Failed to open Cargo.toml for appending")?; - use tests::Architecture::*; + use crate::tests::Architecture::*; let crates = CRATES_ALL .iter() .chain(match &t.arch { @@ -154,10 +154,10 @@ pub fn test(t: &TestCase, bin_path: &PathBuf, rustfmt_bin_path: Option<&PathBuf> // If the architecture is cortex-m we move the generated lib.rs file to src/ let lib_rs_file = path_helper_base(&chip_dir, &["src", "lib.rs"]); let svd2rust_err_file = path_helper_base(&chip_dir, &["svd2rust.err.log"]); - let target = match &t.arch { - &CortexM => "cortex-m", - &Msp430 => "msp430", - &RiscV => "riscv", + let target = match t.arch { + CortexM => "cortex-m", + Msp430 => "msp430", + RiscV => "riscv", }; let mut svd2rust_bin = Command::new(bin_path); if nightly { @@ -175,16 +175,13 @@ pub fn test(t: &TestCase, bin_path: &PathBuf, rustfmt_bin_path: Option<&PathBuf> "svd2rust", if t.arch != CortexM { Some(&lib_rs_file) } else { None }, // use Option.filter Some(&svd2rust_err_file), - &vec![], + &[], )?; process_stderr_paths.push(svd2rust_err_file); - match &t.arch { - &CortexM => { - // TODO: Give error the path to stderr - fs::rename(path_helper_base(&chip_dir, &["lib.rs"]), &lib_rs_file).chain_err(|| "While moving lib.rs file")? - } - _ => (), + if let CortexM = t.arch { + // TODO: Give error the path to stderr + fs::rename(path_helper_base(&chip_dir, &["lib.rs"]), &lib_rs_file).chain_err(|| "While moving lib.rs file")? } let rustfmt_err_file = path_helper_base(&chip_dir, &["rustfmt.err.log"]); diff --git a/ci/svd2rust-regress/src/tests.rs b/ci/svd2rust-regress/src/tests.rs index 1d57872f..d23ee136 100644 --- a/ci/svd2rust-regress/src/tests.rs +++ b/ci/svd2rust-regress/src/tests.rs @@ -74,7 +74,7 @@ use self::RunWhen::*; /// List of chars that some vendors use in their peripheral/field names but /// that are not valid in Rust ident -const BLACKLIST_CHARS: &'static [char] = &['(', ')', '[', ']']; +const BLACKLIST_CHARS: &[char] = &['(', ')', '[', ']']; /// Lovingly stolen from `svd2rust`. Probably could be `Cow` pub trait ToSanitizedSnakeCase { @@ -96,7 +96,7 @@ impl ToSanitizedSnakeCase for str { match s.chars().next().unwrap_or('\0') { '0' | '1' | '2' | '3' | '4' | '5' | '6' | '7' | '8' | '9' => { - String::from(format!("_{}", s.to_snake_case())) + format!("_{}", s.to_snake_case()) } _ => { keywords! { @@ -104,8 +104,8 @@ impl ToSanitizedSnakeCase for str { abstract, alignof, as, - async, - await, + r#async, + r#await, become, box, break, @@ -145,7 +145,7 @@ impl ToSanitizedSnakeCase for str { super, trait, true, - try, + r#try, type, typeof, unsafe, @@ -166,7 +166,7 @@ impl ToSanitizedSnakeCase for str { } // NOTE: All chip names must be unique! -pub const TESTS: &'static [&'static TestCase] = &[ +pub const TESTS: &[&TestCase] = &[ // BAD-SVD missing resetValue &TestCase { arch: CortexM,