diff --git a/.cargo/config.toml b/.cargo/config.toml index 3c32d251..43ca37f1 100644 --- a/.cargo/config.toml +++ b/.cargo/config.toml @@ -1,2 +1,5 @@ [target.aarch64-unknown-linux-gnu] linker = "aarch64-linux-gnu-gcc" + +[alias] +regress = "run -p svd2rust-regress --" diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index ca0b9cf1..5d239663 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -21,7 +21,12 @@ jobs: runs-on: ubuntu-latest strategy: matrix: - TARGET: [x86_64-unknown-linux-gnu, x86_64-apple-darwin, x86_64-pc-windows-msvc] + TARGET: + [ + x86_64-unknown-linux-gnu, + x86_64-apple-darwin, + x86_64-pc-windows-msvc, + ] steps: - uses: actions/checkout@v4 @@ -171,3 +176,40 @@ jobs: uses: Swatinem/rust-cache@v2 - run: cargo fmt --all -- --check + + artifact: + name: Build svd2rust artifact + if: github.event_name == 'pull_request' + needs: [check] + runs-on: ${{ matrix.runs-on }} + strategy: + matrix: + include: + - target: x86_64-unknown-linux-gnu + runs-on: ubuntu-latest + - target: aarch64-apple-darwin + runs-on: macos-latest + - target: x86_64-pc-windows-msvc + runs-on: windows-latest + suffix: .exe + steps: + - uses: actions/checkout@v3 + + - uses: dtolnay/rust-toolchain@master + with: + toolchain: stable + targets: ${{ matrix.target }} + + - name: Cache Dependencies + uses: Swatinem/rust-cache@v2 + + - name: Build svd2rust artifact + run: cargo build --release --target ${{ matrix.target }} + + - run: mv target/${{ matrix.target }}/release/svd2rust${{ matrix.suffix || '' }} svd2rust-${{ matrix.target }}-$(git rev-parse --short HEAD)${{ matrix.suffix || '' }} + + - name: Upload artifact + uses: actions/upload-artifact@v3 + with: + name: artifact-svd2rust-${{ matrix.target }} + path: svd2rust-${{ matrix.target }}* diff --git a/.github/workflows/diff.yml b/.github/workflows/diff.yml new file mode 100644 index 00000000..a6d40960 --- /dev/null +++ b/.github/workflows/diff.yml @@ -0,0 +1,76 @@ +name: Diff +on: + issue_comment: + types: [created] + +jobs: + generate: + runs-on: ubuntu-latest + outputs: + diffs: ${{ steps.regress-ci.outputs.diffs }} + if: ${{ github.event.issue.pull_request }} + steps: + - uses: actions/checkout@v4 + + - uses: dtolnay/rust-toolchain@master + with: + toolchain: stable + + - name: Cache + uses: Swatinem/rust-cache@v2 + with: + shared-key: "diff" + + - run: cargo regress ci + id: regress-ci + env: + GITHUB_COMMENT: ${{ github.event.comment.body }} + GITHUB_COMMENT_PR: ${{ github.event.comment.issue_url }} + diff: + runs-on: ubuntu-latest + needs: [generate] + if: needs.generate.outputs.diffs != '{}' && needs.generate.outputs.diffs != '[]' && needs.generate.outputs.diffs != '' + strategy: + matrix: + include: ${{ fromJson(needs.generate.outputs.diffs) }} + steps: + - uses: actions/checkout@v4 + + - uses: dtolnay/rust-toolchain@master + with: + toolchain: stable + + - name: Cache + uses: Swatinem/rust-cache@v2 + with: + shared-key: "diff" + + - uses: taiki-e/install-action@v2 + if: matrix.needs_semver_checks + with: + tool: cargo-semver-checks + + # if a new line is added here, make sure to update the `summary` job to reference the new step index + - uses: taiki-e/install-action@v2 + with: + tool: git-delta + + - run: cargo regress diff ${{ matrix.command }} --use-pager-directly + env: + GH_TOKEN: ${{ github.token }} + GITHUB_PR: ${{ matrix.pr }} + GIT_PAGER: delta --hunk-header-style omit + summary: + runs-on: ubuntu-latest + needs: [diff, generate] + if: always() && needs.generate.outputs.diffs != '{}' && needs.generate.outputs.diffs != '[]' && needs.generate.outputs.diffs != '' + steps: + - uses: actions/checkout@v4 + + - run: | + PR_ID=$(echo "${{ github.event.comment.issue_url }}" | grep -o '[0-9]\+$') + gh run view ${{ github.run_id }} --json jobs | \ + jq -r '"Diff for [comment]("+$comment+")\n\n" + ([.jobs[] | select(.name | startswith("diff")) | "- [" + (.name | capture("\\((?[^,]+),.*") | .name) + "](" + .url + "?pr=" + $pr_id + "#step:7:45)"] | join("\n"))' --arg pr_id "$PR_ID" --arg comment "${{ github.event.comment.url }}"| \ + gh pr comment "$PR_ID" --body "$(< /dev/stdin)" + env: + GH_TOKEN: ${{ github.token }} diff --git a/.gitignore b/.gitignore index f6537508..33b07514 100644 --- a/.gitignore +++ b/.gitignore @@ -3,4 +3,4 @@ *.rs.bk *.svd target -ci/svd2rust-regress/Cargo.lock +output diff --git a/Cargo.lock b/Cargo.lock index 16ba7348..b88d138c 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -2,6 +2,21 @@ # It is not intended for manual editing. version = 3 +[[package]] +name = "addr2line" +version = "0.21.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "8a30b2e23b9e17a9f90641c7ab1549cd9b44f296d3ccbf309d2863cfe398a0cb" +dependencies = [ + "gimli", +] + +[[package]] +name = "adler" +version = "1.0.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f26201604c87b1e01bd3d98f8d5d9a8fcbb815e8cedb41ffccbeb4bf593a35fe" + [[package]] name = "aho-corasick" version = "1.1.2" @@ -33,30 +48,30 @@ checksum = "7079075b41f533b8c61d2a4d073c4676e1f8b249ff94a393b0595db304e0dd87" [[package]] name = "anstyle-parse" -version = "0.2.2" +version = "0.2.3" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "317b9a89c1868f5ea6ff1d9539a69f45dffc21ce321ac1fd1160dfa48c8e2140" +checksum = "c75ac65da39e5fe5ab759307499ddad880d724eed2f6ce5b5e8a26f4f387928c" dependencies = [ "utf8parse", ] [[package]] name = "anstyle-query" -version = "1.0.0" +version = "1.0.1" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "5ca11d4be1bab0c8bc8734a9aa7bf4ee8316d462a08c6ac5052f888fef5b494b" +checksum = "a3a318f1f38d2418400f8209655bfd825785afd25aa30bb7ba6cc792e4596748" dependencies = [ - "windows-sys 0.48.0", + "windows-sys 0.52.0", ] [[package]] name = "anstyle-wincon" -version = "3.0.1" +version = "3.0.2" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "f0699d10d2f4d628a98ee7b57b289abbc98ff3bad977cb3152709d4bf2330628" +checksum = "1cd54b81ec8d6180e24654d0b371ad22fc3dd083b6ff8ba325b72e00c87660a7" dependencies = [ "anstyle", - "windows-sys 0.48.0", + "windows-sys 0.52.0", ] [[package]] @@ -77,6 +92,39 @@ version = "0.7.4" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "96d30a06541fbafbc7f82ed10c06164cfbd2c401138f6addd8404629c4b16711" +[[package]] +name = "autocfg" +version = "1.1.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa" + +[[package]] +name = "backtrace" +version = "0.3.69" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "2089b7e3f35b9dd2d0ed921ead4f6d318c27680d4a5bd167b3ee120edb105837" +dependencies = [ + "addr2line", + "cc", + "cfg-if", + "libc", + "miniz_oxide", + "object", + "rustc-demangle", +] + +[[package]] +name = "base64" +version = "0.21.5" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "35636a1494ede3b646cc98f74f8e62c773a38a659ebc777a2cf26b9b74171df9" + +[[package]] +name = "bitflags" +version = "1.3.2" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a" + [[package]] name = "bitflags" version = "2.4.1" @@ -94,20 +142,48 @@ dependencies = [ "constant_time_eq", ] +[[package]] +name = "bumpalo" +version = "3.14.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7f30e7476521f6f8af1a1c4c0b8cc94f0bee37d91763d0ca2665f299b6cd8aec" + +[[package]] +name = "bytes" +version = "1.5.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a2bd12c1caf447e69cd4528f47f94d203fd2582878ecb9e9465484c4148a8223" + +[[package]] +name = "cc" +version = "1.0.83" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f1174fb0b6ec23863f8b971027804a42614e347eafb0a95bf0b12cdae21fc4d0" +dependencies = [ + "libc", +] + +[[package]] +name = "cfg-if" +version = "1.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd" + [[package]] name = "clap" -version = "4.4.10" +version = "4.4.11" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "41fffed7514f420abec6d183b1d3acfd9099c79c3a10a06ade4f8203f1411272" +checksum = "bfaff671f6b22ca62406885ece523383b9b64022e341e53e009a62ebc47a45f2" dependencies = [ "clap_builder", + "clap_derive", ] [[package]] name = "clap_builder" -version = "4.4.9" +version = "4.4.11" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "63361bae7eef3771745f02d8d892bec2fee5f6e34af316ba556e7f97a7069ff1" +checksum = "a216b506622bb1d316cd51328dce24e07bdff4a6128a47c7e7fad11878d5adbb" dependencies = [ "anstream", "anstyle", @@ -115,6 +191,18 @@ dependencies = [ "strsim", ] +[[package]] +name = "clap_derive" +version = "4.4.7" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "cf9804afaaf59a91e75b022a30fb7229a7901f60c755489cc61c9b423b836442" +dependencies = [ + "heck", + "proc-macro2", + "quote", + "syn 2.0.39", +] + [[package]] name = "clap_lex" version = "0.6.0" @@ -133,6 +221,55 @@ version = "0.3.0" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "f7144d30dcf0fafbce74250a3963025d8d52177934239851c917d29f1df280c2" +[[package]] +name = "core-foundation" +version = "0.9.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "91e195e091a93c46f7102ec7818a2aa394e1e1771c3ab4825963fa03e45afb8f" +dependencies = [ + "core-foundation-sys", + "libc", +] + +[[package]] +name = "core-foundation-sys" +version = "0.8.6" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "06ea2b9bc92be3c2baa9334a323ebca2d6f074ff852cd1d7b11064035cd3868f" + +[[package]] +name = "crossbeam-deque" +version = "0.8.3" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ce6fd6f855243022dcecf8702fef0c297d4338e226845fe067f6341ad9fa0cef" +dependencies = [ + "cfg-if", + "crossbeam-epoch", + "crossbeam-utils", +] + +[[package]] +name = "crossbeam-epoch" +version = "0.9.15" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ae211234986c545741a7dc064309f67ee1e5ad243d0e48335adc0484d960bcc7" +dependencies = [ + "autocfg", + "cfg-if", + "crossbeam-utils", + "memoffset", + "scopeguard", +] + +[[package]] +name = "crossbeam-utils" +version = "0.8.16" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "5a22b2d63d4d1dc0b7f1b6b2747dd0088008a9be28b6ddf0b1e7d335e3037294" +dependencies = [ + "cfg-if", +] + [[package]] name = "darling" version = "0.14.4" @@ -199,6 +336,21 @@ dependencies = [ "syn 1.0.109", ] +[[package]] +name = "either" +version = "1.9.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "a26ae43d7bcc3b814de94796a5e736d4029efb0ee900c12e2d54c993ad1a1e07" + +[[package]] +name = "encoding_rs" +version = "0.8.33" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7268b386296a025e474d5140678f75d6de9493ae55a5d709eeb9dd08149945e1" +dependencies = [ + "cfg-if", +] + [[package]] name = "env_logger" version = "0.10.1" @@ -228,24 +380,142 @@ dependencies = [ "windows-sys 0.52.0", ] +[[package]] +name = "fastrand" +version = "2.0.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "25cbce373ec4653f1a01a31e8a5e5ec0c622dc27ff9c4e6606eefef5cbbed4a5" + [[package]] name = "fnv" version = "1.0.7" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "3f9eec918d3f24069decb9af1554cad7c880e2da24a9afd88aca000531ab82c1" +[[package]] +name = "foreign-types" +version = "0.3.2" +source = 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[ + "bumpalo", + "log", + "once_cell", + "proc-macro2", + "quote", + "syn 2.0.39", + "wasm-bindgen-shared", +] + +[[package]] +name = "wasm-bindgen-futures" +version = "0.4.39" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ac36a15a220124ac510204aec1c3e5db8a22ab06fd6706d881dc6149f8ed9a12" +dependencies = [ + "cfg-if", + "js-sys", + "wasm-bindgen", + "web-sys", +] + +[[package]] +name = "wasm-bindgen-macro" +version = "0.2.89" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "0162dbf37223cd2afce98f3d0785506dcb8d266223983e4b5b525859e6e182b2" +dependencies = [ + "quote", + "wasm-bindgen-macro-support", +] + +[[package]] +name = "wasm-bindgen-macro-support" +version = "0.2.89" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "f0eb82fcb7930ae6219a7ecfd55b217f5f0893484b7a13022ebb2b2bf20b5283" +dependencies = [ + "proc-macro2", + "quote", + "syn 2.0.39", + "wasm-bindgen-backend", + "wasm-bindgen-shared", +] + +[[package]] +name = "wasm-bindgen-shared" +version = "0.2.89" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "7ab9b36309365056cd639da3134bf87fa8f3d86008abf99e612384a6eecd459f" + +[[package]] +name = "web-sys" +version = "0.3.66" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "50c24a44ec86bb68fbecd1b3efed7e85ea5621b39b35ef2766b66cd984f8010f" +dependencies = [ + "js-sys", + "wasm-bindgen", +] + +[[package]] +name = "which" +version = "5.0.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "9bf3ea8596f3a0dd5980b46430f2058dfe2c36a27ccfbb1845d6fbfcd9ba6e14" +dependencies = [ + "either", + "home", + "once_cell", + "rustix", + "windows-sys 0.48.0", +] + +[[package]] +name = "wildmatch" +version = "2.1.1" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ee583bdc5ff1cf9db20e9db5bb3ff4c3089a8f6b8b31aff265c9aba85812db86" + [[package]] name = "winapi" version = "0.3.9" @@ -801,13 +1871,23 @@ checksum = "dff9641d1cd4be8d1a070daf9e3773c5f67e78b4d9d42263020c057706765c04" [[package]] name = "winnow" -version = "0.5.19" +version = "0.5.25" source = "registry+https://github.com/rust-lang/crates.io-index" -checksum = "829846f3e3db426d4cee4510841b71a8e58aa2a76b1132579487ae430ccd9c7b" +checksum = "b7e87b8dfbe3baffbe687eef2e164e32286eff31a5ee16463ce03d991643ec94" dependencies = [ "memchr", ] +[[package]] +name = "winreg" +version = "0.50.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "524e57b2c537c0f9b1e69f1965311ec12182b4122e45035b1508cd24d2adadb1" +dependencies = [ + "cfg-if", + "windows-sys 0.48.0", +] + [[package]] name = "xmlparser" version = "0.13.6" diff --git a/Cargo.toml b/Cargo.toml index d861cdc2..507c8000 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -69,3 +69,8 @@ version = "0.14.6" [dependencies.syn] version = "2.0" features = ["full","extra-traits"] + +[workspace] +members = ["ci/svd2rust-regress"] +default-members = ["."] +exclude = ["output"] diff --git a/ci/script.sh b/ci/script.sh index afcaebf9..1e4ab69a 100755 --- a/ci/script.sh +++ b/ci/script.sh @@ -1,7 +1,7 @@ set -euxo pipefail test_svd() { - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/$VENDOR/${1}.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/$VENDOR/${1}.svd } test_patched_stm32() { @@ -510,15 +510,15 @@ main() { SiliconLabs) # #99 regression tests - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/SiliconLabs/SiM3_NRND/SIM3C1x4.svd - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/SiliconLabs/SiM3_NRND/SIM3C1x6.svd - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/SiliconLabs/SiM3_NRND/SIM3C1x7.svd - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/SiliconLabs/SiM3_NRND/SIM3L1x4.svd - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/SiliconLabs/SiM3_NRND/SIM3L1x6.svd - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/SiliconLabs/SiM3_NRND/SIM3L1x7.svd - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/SiliconLabs/SiM3_NRND/SIM3U1x4.svd - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/SiliconLabs/SiM3_NRND/SIM3U1x6.svd - test_svd_for_target cortex-m https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/SiliconLabs/SiM3_NRND/SIM3U1x7.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3C1x4.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3C1x6.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3C1x7.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3L1x4.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3L1x6.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3L1x7.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3U1x4.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3U1x6.svd + test_svd_for_target cortex-m https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/SiliconLabs/SiM3_NRND/SIM3U1x7.svd # FIXME(???) panicked at "c.text.clone()" # test_svd SIM3L1x8_SVD diff --git a/ci/svd2rust-regress/Cargo.toml b/ci/svd2rust-regress/Cargo.toml index 641368f9..10709734 100644 --- a/ci/svd2rust-regress/Cargo.toml +++ b/ci/svd2rust-regress/Cargo.toml @@ -5,8 +5,18 @@ version = "0.1.0" authors = ["James Munns ", "The svd2rust developers"] [dependencies] -clap = { version = "4.1", features = ["color", "derive"] } +clap = { version = "4.1", features = ["color", "derive", "string", "env"] } svd2rust = { path = "../../" } -reqwest = { version = "0.11", features= ["blocking"] } +reqwest = { version = "0.11", features = ["blocking"] } rayon = "1.4" -error-chain = "0.12" +anyhow = "1" +thiserror = "1" +serde = "1" +serde_json = "1" +serde_yaml = "0.9" +prettyplease = "0.2" +syn = "2" +wildmatch = "2.1.1" +which = "5.0.0" +tracing = "0.1.40" +tracing-subscriber = { version = "0.3.18", features = ["env-filter", "fmt"] } diff --git a/ci/svd2rust-regress/src/ci.rs b/ci/svd2rust-regress/src/ci.rs new file mode 100644 index 00000000..e8c4d2b1 --- /dev/null +++ b/ci/svd2rust-regress/src/ci.rs @@ -0,0 +1,43 @@ +use crate::Opts; + +#[derive(clap::Parser, Debug)] +#[clap(name = "continuous-integration")] +pub struct Ci { + #[clap(long)] + pub format: bool, + /// Enable splitting `lib.rs` with `form` + #[clap(long)] + pub form_lib: bool, + #[clap(env = "GITHUB_COMMENT")] + pub comment: String, + #[clap(env = "GITHUB_COMMENT_PR")] + pub comment_pr: String, +} + +#[derive(serde::Serialize)] +struct Diff { + command: String, + needs_semver_checks: bool, + pr: usize, +} + +impl Ci { + pub fn run(&self, _opts: &Opts) -> Result<(), anyhow::Error> { + let mut diffs = vec![]; + for line in self.comment.lines() { + let Some(command) = line.strip_prefix("/ci diff ") else { + continue; + }; + + diffs.push(Diff { + needs_semver_checks: command.contains("semver"), + command: command.to_owned(), + pr: self.comment_pr.split('/').last().unwrap().parse()?, + }); + } + let json = serde_json::to_string(&diffs)?; + crate::gha_print(&json); + crate::gha_output("diffs", &json)?; + Ok(()) + } +} diff --git a/ci/svd2rust-regress/src/command.rs b/ci/svd2rust-regress/src/command.rs new file mode 100644 index 00000000..2c873bb8 --- /dev/null +++ b/ci/svd2rust-regress/src/command.rs @@ -0,0 +1,70 @@ +use std::process::Command; + +use anyhow::Context; + +pub trait CommandExt { + #[track_caller] + fn run(&mut self, hide: bool) -> Result<(), anyhow::Error>; + + #[track_caller] + fn get_output(&mut self, can_fail: bool) -> Result; + + #[track_caller] + fn get_output_string(&mut self) -> Result; + + fn display(&self) -> String; +} + +impl CommandExt for Command { + #[track_caller] + fn run(&mut self, hide: bool) -> Result<(), anyhow::Error> { + if hide { + self.stdout(std::process::Stdio::null()) + .stdin(std::process::Stdio::null()); + } + let status = self + .status() + .with_context(|| format!("fail! {}", self.display()))?; + if status.success() { + Ok(()) + } else { + anyhow::bail!("command `{}` failed", self.display()) + } + } + + #[track_caller] + fn get_output(&mut self, can_fail: bool) -> Result { + let output = self + .output() + .with_context(|| format!("command `{}` couldn't be run", self.display()))?; + if output.status.success() || can_fail { + Ok(output) + } else { + anyhow::bail!( + "command `{}` failed: stdout: {}\nstderr: {}", + self.display(), + String::from_utf8_lossy(&output.stdout), + String::from_utf8_lossy(&output.stderr), + ) + } + } + + #[track_caller] + fn get_output_string(&mut self) -> Result { + String::from_utf8(self.get_output(true)?.stdout).map_err(Into::into) + } + + fn display(&self) -> String { + format!( + "{}{} {}", + self.get_current_dir() + .map(|d| format!("{} ", d.display())) + .unwrap_or_default(), + self.get_program().to_string_lossy(), + self.get_args() + .map(|s| s.to_string_lossy()) + .collect::>() + .join(" ") + ) + } +} diff --git a/ci/svd2rust-regress/src/diff.rs b/ci/svd2rust-regress/src/diff.rs new file mode 100644 index 00000000..dd4623f6 --- /dev/null +++ b/ci/svd2rust-regress/src/diff.rs @@ -0,0 +1,339 @@ +use std::path::PathBuf; + +use anyhow::Context; + +use crate::github; +use crate::Opts; + +#[derive(clap::Parser, Debug)] +#[clap(name = "diff")] +pub struct Diffing { + /// The base version of svd2rust to use and the command input, defaults to latest master build + /// + /// Change the base version by starting with `@` followed by the source. + /// + /// supports `@pr` for current pr, `@master` for latest master build, or a version tag like `@v0.30.0` + #[clap(global = true, long = "baseline", alias = "base")] + pub baseline: Option, + + #[clap(global = true, long = "current", alias = "head")] + pub current: Option, + + /// Enable formatting with `rustfmt` + #[clap(global = true, short = 'f', long)] + pub format: bool, + + /// Enable splitting `lib.rs` with `form` + #[clap(global = true, long)] + pub form_split: bool, + + #[clap(subcommand)] + pub sub: Option, + + #[clap(global = true, long, short = 'c')] + pub chip: Vec, + + /// Filter by manufacturer, case sensitive, may be combined with other filters + #[clap( + short = 'm', + long = "manufacturer", + ignore_case = true, + value_parser = crate::manufacturers(), + )] + pub mfgr: Option, + + /// Filter by architecture, case sensitive, may be combined with other filters + #[clap( + short = 'a', + long = "architecture", + ignore_case = true, + value_parser = crate::architectures(), + )] + pub arch: Option, + + #[clap(global = true, long)] + pub diff_folder: Option, + + #[clap(hide = true, env = "GITHUB_PR")] + pub pr: Option, + + #[clap(env = "GIT_PAGER", long)] + pub pager: Option, + + /// if set, will use pager directly instead of `git -c core.pager` + #[clap(long, short = 'P')] + pub use_pager_directly: bool, + + #[clap(last = true)] + pub last_args: Option, +} + +#[derive(clap::Parser, Debug, Clone)] +pub enum DiffingMode { + Semver { + #[clap(last = true)] + last_args: Option, + }, + Diff { + #[clap(last = true)] + last_args: Option, + }, + Pr { + #[clap(last = true)] + last_args: Option, + }, +} + +impl DiffingMode { + /// Returns `true` if the diffing mode is [`Pr`]. + /// + /// [`Pr`]: DiffingMode::Pr + #[must_use] + pub fn is_pr(&self) -> bool { + matches!(self, Self::Pr { .. }) + } +} + +type Source<'s> = Option<&'s str>; +type Command<'s> = Option<&'s str>; + +impl Diffing { + pub fn run(&self, opts: &Opts) -> Result<(), anyhow::Error> { + let [baseline, current] = self + .make_case(opts) + .with_context(|| "couldn't setup test case")?; + match self.sub.as_ref() { + None | Some(DiffingMode::Diff { .. } | DiffingMode::Pr { .. }) => { + let mut command; + if let Some(pager) = &self.pager { + if self.use_pager_directly { + let mut pager = pager.split_whitespace(); + command = std::process::Command::new(pager.next().unwrap()); + command.args(pager); + } else { + command = std::process::Command::new("git"); + command.env("GIT_PAGER", pager); + } + } else { + command = std::process::Command::new("git"); + command.arg("--no-pager"); + } + if !self.use_pager_directly { + command.args(["diff", "--no-index", "--minimal"]); + } + command + .args([&*baseline.0, &*current.0]) + .status() + .with_context(|| "couldn't run diff") + .map(|_| ()) + } + Some(DiffingMode::Semver { .. }) => std::process::Command::new("cargo") + .args(["semver-checks", "check-release"]) + .arg("--baseline-root") + .arg(baseline.0) + .arg("--manifest-path") + .arg(current.0.join("Cargo.toml")) + .status() + .with_context(|| "couldn't run semver-checks") + .map(|_| ()), + } + } + + pub fn make_case(&self, opts: &Opts) -> Result<[(PathBuf, Vec); 2], anyhow::Error> { + let [(baseline_bin, baseline_cmd), (current_bin, current_cmd)] = self + .svd2rust_setup(opts) + .with_context(|| "couldn't setup svd2rust")?; + let tests = crate::tests::tests(Some(opts.test_cases.as_ref())) + .with_context(|| "no tests found")?; + + let tests = tests + .iter() + .filter(|t| { + if let Some(ref arch) = self.arch { + arch.to_ascii_lowercase() + .eq_ignore_ascii_case(&t.arch.to_string()) + } else { + true + } + }) + // selected manufacturer? + .filter(|t| { + if let Some(ref mfgr) = self.mfgr { + mfgr.to_ascii_lowercase() + .eq_ignore_ascii_case(&t.mfgr.to_string().to_ascii_lowercase()) + } else { + true + } + }) + .filter(|t| { + if self.chip.is_empty() { + true + } else { + self.chip.iter().any(|c| { + wildmatch::WildMatch::new(&c.to_ascii_lowercase()) + .matches(&t.chip.to_ascii_lowercase()) + }) + } + }) + .collect::>(); + let test = match (tests.len(), self.sub.as_ref()) { + (1, _) => tests[0], + (_, Some(DiffingMode::Pr { .. })) => tests + .iter() + .find(|t| t.chip == "STM32F103") + .unwrap_or(&tests[0]), + _ => { + let error = anyhow::anyhow!("diff requires exactly one test case"); + let len = tests.len(); + return Err(match len { + 0 => error.context("matched no tests"), + 10.. => error.context(format!("matched multiple ({len}) tests")), + _ => error.context(format!( + "matched multiple ({len}) tests\n{:?}", + tests.iter().map(|t| t.name()).collect::>() + )), + }); + } + }; + + let last_args = self.last_args.as_deref().or(match &self.sub { + Some( + DiffingMode::Diff { last_args } + | DiffingMode::Pr { last_args } + | DiffingMode::Semver { last_args }, + ) => last_args.as_deref(), + None => None, + }); + let join = |opt1: Option<&str>, opt2: Option<&str>| -> Option { + match (opt1, opt2) { + (Some(str1), Some(str2)) => Some(format!("{} {}", str1, str2)), + (Some(str), None) | (None, Some(str)) => Some(str.to_owned()), + (None, None) => None, + } + }; + let baseline = test + .setup_case( + &opts.output_dir.join("baseline"), + &baseline_bin, + join(baseline_cmd, last_args).as_deref(), + ) + .with_context(|| "couldn't create head")?; + let current = test + .setup_case( + &opts.output_dir.join("current"), + ¤t_bin, + join(current_cmd, last_args).as_deref(), + ) + .with_context(|| "couldn't create base")?; + + Ok([baseline, current]) + } + + fn get_source_and_command<'s>(&'s self) -> [Option<(Source, Command)>; 2] { + let split = |s: &'s str| -> (Source, Command) { + if let Some(s) = s.strip_prefix('@') { + if let Some((source, cmd)) = s.split_once(' ') { + (Some(source), Some(cmd.trim())) + } else { + (Some(s), None) + } + } else { + (None, Some(s.trim())) + } + }; + + let baseline = self.baseline.as_deref().map(split); + + let current = self.current.as_deref().map(split); + [baseline, current] + } + + pub fn svd2rust_setup(&self, opts: &Opts) -> Result<[(PathBuf, Command); 2], anyhow::Error> { + // FIXME: refactor this to be less ugly + let [baseline_sc, current_sc] = self.get_source_and_command(); + let baseline = match baseline_sc.and_then(|(source, _)| source) { + reference @ (None | Some("" | "master")) => { + github::get_release_binary_artifact(reference.unwrap_or("master"), &opts.output_dir) + .with_context(|| "couldn't get svd2rust latest unreleased artifact")? + } + Some("pr") if self.pr.is_none() => { + let (number, sha) = + github::get_current_pr().with_context(|| "couldn't get current pr")?; + github::get_pr_binary_artifact(number, &sha, &opts.output_dir) + .with_context(|| "couldn't get pr artifact")? + } + Some("pr") => { + let (number, sha) = + github::get_pr(self.pr.unwrap()).with_context(|| "couldn't get current pr")?; + github::get_pr_binary_artifact(number, &sha, &opts.output_dir) + .with_context(|| "couldn't get pr artifact")? + } + Some("debug") => crate::get_cargo_metadata() + .target_directory + .join(format!("debug/svd2rust{}", std::env::consts::EXE_SUFFIX)), + Some("release") => crate::get_cargo_metadata() + .target_directory + .join(format!("release/svd2rust{}", std::env::consts::EXE_SUFFIX)), + Some(reference) => github::get_release_binary_artifact(reference, &opts.output_dir) + .with_context(|| format!("could not get svd2rust for {reference}"))?, + }; + + let current = match current_sc.and_then(|(source, _)| source) { + None | Some("" | "pr") if self.pr.is_none() => { + let (number, sha) = + github::get_current_pr().with_context(|| "couldn't get current pr")?; + github::get_pr_binary_artifact(number, &sha, &opts.output_dir) + .with_context(|| "couldn't get pr artifact")? + } + None | Some("" | "pr") => { + let (number, sha) = + github::get_pr(self.pr.unwrap()).with_context(|| "couldn't get current pr")?; + github::get_pr_binary_artifact(number, &sha, &opts.output_dir) + .with_context(|| "couldn't get pr artifact")? + } + Some("debug") => crate::get_cargo_metadata() + .target_directory + .join(format!("debug/svd2rust{}", std::env::consts::EXE_SUFFIX)), + Some("release") => crate::get_cargo_metadata() + .target_directory + .join(format!("release/svd2rust{}", std::env::consts::EXE_SUFFIX)), + Some(reference) => github::get_release_binary_artifact(reference, &opts.output_dir) + .with_context(|| format!("could not get svd2rust for {reference}"))?, + }; + + Ok([ + ( + baseline.canonicalize()?, + baseline_sc.and_then(|(_, cmd)| cmd), + ), + (current.canonicalize()?, current_sc.and_then(|(_, cmd)| cmd)), + ]) + } +} + +#[cfg(test)] +#[test] +pub fn diffing_cli_works() { + use clap::Parser; + + Diffing::parse_from(["diff", "pr"]); + Diffing::parse_from(["diff", "--base", "", "--head", "\"--atomics\""]); + Diffing::parse_from(["diff", "--base", "\"@master\"", "--head", "\"@pr\""]); + Diffing::parse_from([ + "diff", + "--base", + "\"@master\"", + "--head", + "\"@pr\"", + "--chip", + "STM32F401", + ]); + Diffing::parse_from([ + "diff", + "--base", + "\"@master\"", + "--head", + "\"@pr --atomics\"", + ]); + Diffing::parse_from(["diff", "--head", "\"--atomics\""]); +} diff --git a/ci/svd2rust-regress/src/errors.rs b/ci/svd2rust-regress/src/errors.rs deleted file mode 100644 index cf598bf5..00000000 --- a/ci/svd2rust-regress/src/errors.rs +++ /dev/null @@ -1,9 +0,0 @@ -use std::path::PathBuf; -error_chain! { - errors { - ProcessFailed(command: String, stderr: Option, stdout: Option, previous_processes_stderr: Vec) { - description("Process Failed") - display("Process Failed - {}", command) - } - } -} diff --git a/ci/svd2rust-regress/src/github.rs b/ci/svd2rust-regress/src/github.rs new file mode 100644 index 00000000..1a5b0ecb --- /dev/null +++ b/ci/svd2rust-regress/src/github.rs @@ -0,0 +1,230 @@ +use std::process::Command; +use std::{ffi::OsStr, path::Path}; +use std::{iter::IntoIterator, path::PathBuf}; + +use anyhow::Context; + +use crate::command::CommandExt; + +pub fn run_gh(args: I) -> Command +where + I: IntoIterator, + S: AsRef, +{ + let mut command = Command::new("gh"); + command.args(args); + command +} + +pub fn get_current_pr() -> Result<(usize, String), anyhow::Error> { + #[derive(serde::Deserialize)] + struct Pr { + number: usize, + #[serde(rename = "headRefOid")] + head_ref_oid: String, + } + let pr = run_gh(["pr", "view", "--json", "headRefOid,number"]).get_output_string()?; + let Pr { + number, + head_ref_oid, + } = serde_json::from_str(&pr)?; + + Ok((number, head_ref_oid)) +} + +pub fn get_pr(pr: usize) -> Result<(usize, String), anyhow::Error> { + #[derive(serde::Deserialize)] + struct Pr { + number: usize, + #[serde(rename = "headRefOid")] + head_ref_oid: String, + } + let pr = run_gh(["pr", "view", &pr.to_string(), "--json", "headRefOid,number"]) + .get_output_string()?; + let Pr { + number, + head_ref_oid, + } = serde_json::from_str(&pr)?; + + Ok((number, head_ref_oid)) +} + +pub fn get_sha_run_id(sha: &str) -> Result { + let run_id = run_gh([ + "api", + &format!("repos/:owner/:repo/actions/runs?event=pull_request&head_sha={sha}"), + "--jq", + r#"[.workflow_runs[] | select(.name == "Continuous integration")][0] | .id"#, + ]) + .get_output_string()?; + if run_id.trim().is_empty() { + anyhow::bail!("no run id found for sha `{}`", sha); + } + run_id + .trim() + .parse() + .with_context(|| anyhow::anyhow!("couldn't parse api output: {run_id}")) +} + +pub fn get_release_run_id(event: &str) -> Result { + let query = match event { + "master" => "branch=master".to_owned(), + _ => anyhow::bail!("unknown event"), + }; + let run_id = run_gh([ + "api", + &format!("repos/:owner/:repo/actions/runs?{query}"), + "--jq", + r#"[.workflow_runs[] | select(.name == "release")][0] | .id"#, + ]) + .get_output_string()?; + run_id.trim().parse().map_err(Into::into) +} + +fn find_executable(dir: &Path, begins: &str) -> Result, anyhow::Error> { + let find = |entry, begins: &str| -> Result, std::io::Error> { + let entry: std::fs::DirEntry = entry?; + let filename = entry.file_name(); + let filename = filename.to_string_lossy(); + if entry.metadata()?.is_file() + && filename.starts_with(begins) + && (entry.path().extension().is_none() + || entry + .path() + .extension() + .is_some_and(|s| s == std::env::consts::EXE_EXTENSION)) + && !entry.path().extension().is_some_and(|s| s == "gz") + { + Ok(Some(entry.path())) + } else { + Ok(None) + } + }; + let mut read_dir = std::fs::read_dir(dir)?; + read_dir + .find_map(|entry| find(entry, begins).transpose()) + .transpose() + .map_err(Into::into) +} + +pub fn get_release_binary_artifact( + reference: &str, + output_dir: &Path, +) -> Result { + let output_dir = output_dir.join(".binary").join(reference); + + match reference { + reference if reference.starts_with('v') || matches!(reference, "master" | "latest") => { + let tag = if reference == "master" { + Some("Unreleased") + } else if reference == "latest" { + None + } else { + Some(reference) + }; + + let artifact = if cfg!(target_os = "linux") && cfg!(target_arch = "x86_64") { + "svd2rust-x86_64-unknown-linux-gnu.gz" + } else if cfg!(target_os = "linux") && cfg!(target_arch = "aarch64") { + "svd2rust-aarch64-unknown-linux-gnu.gz" + } else if cfg!(windows) { + "svd2rust-x86_64-pc-windows-msvc.exe" + } else if cfg!(target_os = "macos") && cfg!(target_arch = "x86_64") { + "svd2rust-x86_64-apple-darwin.gz" + } else if cfg!(target_os = "macos") && cfg!(target_arch = "aarch64") { + "svd2rust-aarch64-apple-darwin.gz" + } else { + anyhow::bail!("regress with release artifact doesn't support current platform") + }; + + std::fs::remove_dir_all(&output_dir).ok(); + + run_gh(["release", "download", "--pattern", artifact, "--dir"]) + .arg(&output_dir) + .args(tag) + .run(true)?; + + if cfg!(target_os = "linux") || cfg!(target_os = "macos") { + Command::new("gzip") + .arg("-d") + .arg(output_dir.join(artifact)) + .get_output(false)?; + } + } + _ => { + let run_id = + get_release_run_id(reference).with_context(|| "couldn't get release run id")?; + run_gh([ + "run", + "download", + &run_id.to_string(), + "-n", + "svd2rust-x86_64-unknown-linux-gnu", + "--dir", + ]) + .arg(&output_dir) + .run(true)?; + } + } + let binary = + find_executable(&output_dir, "svd2rust").with_context(|| "couldn't find svd2rust")?; + let binary = binary.ok_or_else(|| anyhow::anyhow!("no binary found"))?; + + #[cfg(unix)] + { + use std::os::unix::fs::PermissionsExt; + std::fs::set_permissions(&binary, std::fs::Permissions::from_mode(0o755))?; + } + + Ok(binary) +} + +pub fn get_pr_binary_artifact( + pr: usize, + sha: &str, + output_dir: &Path, +) -> Result { + let output_dir = output_dir.join(".binary").join(pr.to_string()).join(sha); + + if let Some(binary) = find_executable(&output_dir, "svd2rust").unwrap_or_default() { + return Ok(binary); + } + + let target = if cfg!(target_os = "linux") && cfg!(target_arch = "x86_64") { + "x86_64-unknown-linux-gnu" + } else if cfg!(target_os = "linux") && cfg!(target_arch = "aarch64") { + "aarch64-unknown-linux-gnu" + } else if cfg!(windows) { + "x86_64-pc-windows-msvc" + } else if cfg!(target_os = "macos") && cfg!(target_arch = "x86_64") { + "x86_64-apple-darwin" + } else if cfg!(target_os = "macos") && cfg!(target_arch = "aarch64") { + "aarch64-apple-darwin" + } else { + anyhow::bail!("regress with pr artifact doesn't support current platform"); + }; + + let run_id = get_sha_run_id(sha).context("when getting run id")?; + run_gh([ + "run", + "download", + &run_id.to_string(), + "-n", + &format!("artifact-svd2rust-{}", target), + "--dir", + ]) + .arg(&output_dir) + .run(true)?; + + let binary = + find_executable(&output_dir, "svd2rust").with_context(|| "couldn't find svd2rust")?; + let binary = binary.ok_or_else(|| anyhow::anyhow!("no binary found"))?; + + #[cfg(unix)] + { + use std::os::unix::fs::PermissionsExt; + std::fs::set_permissions(&binary, std::fs::Permissions::from_mode(0o755))?; + } + + Ok(binary) +} diff --git a/ci/svd2rust-regress/src/main.rs b/ci/svd2rust-regress/src/main.rs index 3ee39955..a8c1d246 100644 --- a/ci/svd2rust-regress/src/main.rs +++ b/ci/svd2rust-regress/src/main.rs @@ -1,12 +1,15 @@ -#[macro_use] -extern crate error_chain; - -mod errors; +pub mod ci; +pub mod command; +pub mod diff; +pub mod github; mod svd_test; mod tests; +use anyhow::Context; +use ci::Ci; +use diff::Diffing; + use clap::Parser; -use error_chain::ChainedError; use rayon::prelude::*; use std::fs::File; use std::io::Read; @@ -14,100 +17,303 @@ use std::path::PathBuf; use std::process::{exit, Command}; use std::sync::atomic::{AtomicBool, Ordering}; use std::time::Instant; +use wildmatch::WildMatch; -#[derive(Parser, Debug)] -#[command(name = "svd2rust-regress")] -struct Opt { - /// Run a long test (it's very long) - #[clap(short = 'l', long)] - long_test: bool, +#[derive(Debug, serde::Deserialize)] +pub struct CargoMetadata { + workspace_root: PathBuf, + target_directory: PathBuf, +} - /// Path to an `svd2rust` binary, relative or absolute. - /// Defaults to `target/release/svd2rust[.exe]` of this repository - /// (which must be already built) - #[clap(short = 'p', long = "svd2rust-path")] - bin_path: Option, +static RUSTFMT: std::sync::OnceLock = std::sync::OnceLock::new(); +static FORM: std::sync::OnceLock = std::sync::OnceLock::new(); + +/// Returns the cargo metadata +pub fn get_cargo_metadata() -> &'static CargoMetadata { + static WORKSPACE: std::sync::OnceLock = std::sync::OnceLock::new(); + WORKSPACE.get_or_init(|| { + std::process::Command::new("cargo") + .args(["metadata", "--format-version", "1"]) + .output() + .map(|v| String::from_utf8(v.stdout)) + .unwrap() + .map_err(anyhow::Error::from) + .and_then(|s: String| serde_json::from_str::(&s).map_err(Into::into)) + .unwrap() + }) +} - // TODO: Consider using the same strategy cargo uses for passing args to rustc via `--` - /// Run svd2rust with `--atomics` - #[clap(long)] - atomics: bool, +/// Returns the cargo workspace for the manifest +#[must_use] +pub fn get_cargo_workspace() -> &'static std::path::Path { + &get_cargo_metadata().workspace_root +} + +#[derive(clap::Parser, Debug)] +pub struct TestOpts { + /// Run a long test (it's very long) + #[clap(short = 'l', long)] + pub long_test: bool, /// Filter by chip name, case sensitive, may be combined with other filters - #[clap(short = 'c', long, value_parser = validate_chips)] - chip: Vec, + #[clap(short = 'c', long)] + pub chip: Vec, /// Filter by manufacturer, case sensitive, may be combined with other filters #[clap( - short = 'm', - long = "manufacturer", - value_parser = validate_manufacturer, - )] - mfgr: Option, + short = 'm', + long = "manufacturer", + ignore_case = true, + value_parser = manufacturers(), +)] + pub mfgr: Option, /// Filter by architecture, case sensitive, may be combined with other filters - /// Options are: "CortexM", "RiscV", "Msp430", "Mips" and "XtensaLX" #[clap( - short = 'a', - long = "architecture", - value_parser = validate_architecture, - )] - arch: Option, + short = 'a', + long = "architecture", + ignore_case = true, + value_parser = architectures(), +)] + pub arch: Option, /// Include tests expected to fail (will cause a non-zero return code) #[clap(short = 'b', long)] - bad_tests: bool, + pub bad_tests: bool, /// Enable formatting with `rustfmt` #[clap(short = 'f', long)] - format: bool, + pub format: bool, + + #[clap(long)] + /// Enable splitting `lib.rs` with `form` + pub form_lib: bool, /// Print all available test using the specified filters #[clap(long)] - list: bool, + pub list: bool, + + /// Path to an `svd2rust` binary, relative or absolute. + /// Defaults to `target/release/svd2rust[.exe]` of this repository + /// (which must be already built) + #[clap(short = 'p', long = "svd2rust-path", default_value = default_svd2rust())] + pub current_bin_path: PathBuf, + #[clap(last = true)] + pub command: Option, + // TODO: Specify smaller subset of tests? Maybe with tags? + // TODO: Compile svd2rust? +} + +impl TestOpts { + fn run(&self, opt: &Opts) -> Result<(), anyhow::Error> { + let tests = tests::tests(Some(&opt.test_cases))? + .iter() + // Short test? + .filter(|t| t.should_run(!self.long_test)) + // selected architecture? + .filter(|t| { + if let Some(ref arch) = self.arch { + arch.to_ascii_lowercase() + .eq_ignore_ascii_case(&t.arch.to_string()) + } else { + true + } + }) + // selected manufacturer? + .filter(|t| { + if let Some(ref mfgr) = self.mfgr { + mfgr.to_ascii_lowercase() + .eq_ignore_ascii_case(&t.mfgr.to_string().to_ascii_lowercase()) + } else { + true + } + }) + // Specify chip - note: may match multiple + .filter(|t| { + if self.chip.is_empty() { + // Don't run failable tests unless wanted + self.bad_tests || t.should_pass + } else { + self.chip.iter().any(|c| WildMatch::new(c).matches(&t.chip)) + } + }) + .collect::>(); + if self.list { + // FIXME: Prettier output + println!("{:?}", tests.iter().map(|t| t.name()).collect::>()); + exit(0); + } + if tests.is_empty() { + tracing::error!( + "No tests run, you might want to use `--bad-tests` and/or `--long-test`" + ); + } + let any_fails = AtomicBool::new(false); + tests.par_iter().for_each(|t| { + let start = Instant::now(); + + match t.test(opt, self) { + Ok(s) => { + if let Some(stderrs) = s { + let mut buf = String::new(); + for stderr in stderrs { + read_file(&stderr, &mut buf); + } + tracing::info!( + "Passed: {} - {} seconds\n{}", + t.name(), + start.elapsed().as_secs(), + buf + ); + } else { + tracing::info!( + "Passed: {} - {} seconds", + t.name(), + start.elapsed().as_secs() + ); + } + } + Err(e) => { + any_fails.store(true, Ordering::Release); + let additional_info = if opt.verbose > 0 { + match &e { + svd_test::TestError::Process(svd_test::ProcessFailed { + stderr: Some(ref stderr), + previous_processes_stderr, + .. + }) => { + let mut buf = String::new(); + if opt.verbose > 1 { + for stderr in previous_processes_stderr { + read_file(stderr, &mut buf); + } + } + read_file(stderr, &mut buf); + buf + } + _ => String::new(), + } + } else { + String::new() + }; + tracing::error!( + "Failed: {} - {} seconds. {:?}{}", + t.name(), + start.elapsed().as_secs(), + anyhow::Error::new(e), + additional_info, + ); + } + } + }); + if any_fails.load(Ordering::Acquire) { + exit(1); + } else { + exit(0); + } + } +} + +#[derive(clap::Subcommand, Debug)] +pub enum Subcommand { + Diff(Diffing), + Tests(TestOpts), + Ci(Ci), +} + +#[derive(Parser, Debug)] +#[command(name = "svd2rust-regress")] +pub struct Opts { + /// Use verbose output + #[clap(global = true, long, short = 'v', action = clap::ArgAction::Count)] + pub verbose: u8, /// Path to an `rustfmt` binary, relative or absolute. /// Defaults to `$(rustup which rustfmt)` - #[clap(long)] - rustfmt_bin_path: Option, + #[clap(global = true, long)] + pub rustfmt_bin_path: Option, + + /// Path to a `form` binary, relative or absolute. + /// Defaults to `form` + #[clap(global = true, long)] + pub form_bin_path: Option, /// Specify what rustup toolchain to use when compiling chip(s) - #[clap(long = "toolchain")] // , env = "RUSTUP_TOOLCHAIN" - rustup_toolchain: Option, + #[clap(global = true, long = "toolchain")] // , env = "RUSTUP_TOOLCHAIN" + pub rustup_toolchain: Option, - /// Use verbose output - #[clap(long, short = 'v', action = clap::ArgAction::Count)] - verbose: u8, - // TODO: Specify smaller subset of tests? Maybe with tags? - // TODO: Compile svd2rust? + /// Test cases to run + #[clap(global = true, long, default_value = default_test_cases())] + pub test_cases: std::path::PathBuf, + + #[clap(global = true, long, short, default_value = "output")] + pub output_dir: std::path::PathBuf, + + #[clap(subcommand)] + subcommand: Subcommand, } -fn validate_chips(s: &str) -> Result<(), String> { - if tests::TESTS.iter().any(|t| t.chip == s) { - Ok(()) - } else { - Err(format!("Chip `{}` is not a valid value", s)) +impl Opts { + const fn use_rustfmt(&self) -> bool { + match self.subcommand { + Subcommand::Tests(TestOpts { format, .. }) + | Subcommand::Diff(Diffing { format, .. }) + | Subcommand::Ci(Ci { format, .. }) => format, + } } -} -fn validate_architecture(s: &str) -> Result<(), String> { - if tests::TESTS.iter().any(|t| format!("{:?}", t.arch) == s) { - Ok(()) - } else { - Err(format!("Architecture `{s}` is not a valid value")) + const fn use_form(&self) -> bool { + match self.subcommand { + Subcommand::Tests(TestOpts { form_lib, .. }) + | Subcommand::Diff(Diffing { + form_split: form_lib, + .. + }) + | Subcommand::Ci(Ci { form_lib, .. }) => form_lib, + } } } -fn validate_manufacturer(s: &str) -> Result<(), String> { - if tests::TESTS.iter().any(|t| format!("{:?}", t.mfgr) == s) { - Ok(()) - } else { - Err(format!("Manufacturer `{s}` is not a valid value")) - } +/// Hack to use ci/tests.yml as default value when running as `cargo run` +fn default_test_cases() -> std::ffi::OsString { + std::env::var_os("CARGO_MANIFEST_DIR").map_or_else( + || std::ffi::OsString::from("tests.yml".to_owned()), + |mut e| { + e.extend([std::ffi::OsStr::new("/tests.yml")]); + std::path::PathBuf::from(e) + .strip_prefix(std::env::current_dir().unwrap()) + .unwrap() + .to_owned() + .into_os_string() + }, + ) +} + +fn default_svd2rust() -> std::ffi::OsString { + get_cargo_workspace() + .join(format!( + "target/release/svd2rust{}", + std::env::consts::EXE_SUFFIX, + )) + .into_os_string() +} + +fn architectures() -> Vec { + svd2rust::Target::all() + .iter() + .map(|arch| clap::builder::PossibleValue::new(arch.to_string())) + .collect() +} + +fn manufacturers() -> Vec { + tests::Manufacturer::all() + .iter() + .map(|mfgr| clap::builder::PossibleValue::new(mfgr.to_string())) + .collect() } /// Validate any assumptions made by this program -fn validate_tests(tests: &[&tests::TestCase]) { +fn validate_tests(tests: &[tests::TestCase]) { use std::collections::HashSet; let mut fail = false; @@ -118,13 +324,11 @@ fn validate_tests(tests: &[&tests::TestCase]) { let name = t.name(); if !uniq.insert(name.clone()) { fail = true; - eprintln!("{} is not unique!", name); + tracing::info!("{} is not unique!", name); } } - if fail { - panic!("Tests failed validation"); - } + assert!(!fail, "Tests failed validation"); } fn read_file(path: &PathBuf, buf: &mut String) { @@ -139,166 +343,113 @@ fn read_file(path: &PathBuf, buf: &mut String) { .expect("Couldn't read file to string"); } -fn main() { - let opt = Opt::parse(); +fn main() -> Result<(), anyhow::Error> { + let opt = Opts::parse(); + tracing_subscriber::fmt() + .pretty() + .with_target(false) + .with_writer(std::io::stderr) + .with_env_filter( + tracing_subscriber::EnvFilter::builder() + .with_default_directive(tracing::level_filters::LevelFilter::INFO.into()) + .from_env_lossy(), + ) + .init(); // Validate all test pre-conditions - validate_tests(tests::TESTS); - - // Determine default svd2rust path - let default_svd2rust_iter = ["..", "..", "..", "..", "target", "release"]; - - let default_svd2rust = if cfg!(windows) { - default_svd2rust_iter.iter().chain(["svd2rust.exe"].iter()) - } else { - default_svd2rust_iter.iter().chain(["svd2rust"].iter()) - } - .collect(); - - let bin_path = match opt.bin_path { - Some(ref bp) => bp, - None => &default_svd2rust, - }; + validate_tests(tests::tests(Some(&opt.test_cases))?); let default_rustfmt: Option = if let Some((v, true)) = Command::new("rustup") - .args(&["which", "rustfmt"]) + .args(["which", "rustfmt"]) .output() .ok() .map(|o| (o.stdout, o.status.success())) { Some(String::from_utf8_lossy(&v).into_owned().trim().into()) } else { - if opt.format && opt.rustfmt_bin_path.is_none() { - panic!("rustfmt binary not found, is rustup and rustfmt-preview installed?"); - } None }; - let rustfmt_bin_path = match (&opt.rustfmt_bin_path, opt.format) { - (_, false) => None, - (&Some(ref path), true) => Some(path), + match (&opt.rustfmt_bin_path, opt.use_rustfmt()) { + (_, false) => {} + (Some(path), true) => { + RUSTFMT.get_or_init(|| path.clone()); + } (&None, true) => { // FIXME: Use Option::filter instead when stable, rust-lang/rust#45860 - if default_rustfmt.iter().find(|p| p.is_file()).is_none() { - panic!("No rustfmt found"); + assert!( + default_rustfmt.iter().any(|p| p.is_file()), + "No rustfmt found" + ); + if let Some(default_rustfmt) = default_rustfmt { + RUSTFMT.get_or_init(|| default_rustfmt); } - default_rustfmt.as_ref() } }; + match (&opt.form_bin_path, opt.use_form()) { + (_, false) => {} + (Some(path), true) => { + FORM.get_or_init(|| path.clone()); + } + (&None, true) => { + if let Ok(form) = which::which("form") { + FORM.get_or_init(|| form); + } + } + } // Set RUSTUP_TOOLCHAIN if needed if let Some(toolchain) = &opt.rustup_toolchain { std::env::set_var("RUSTUP_TOOLCHAIN", toolchain); } - // collect enabled tests - let tests = tests::TESTS - .iter() - // Short test? - .filter(|t| t.should_run(!opt.long_test)) - // selected architecture? - .filter(|t| { - if let Some(ref arch) = opt.arch { - arch == &format!("{:?}", t.arch) - } else { - true - } - }) - // selected manufacturer? - .filter(|t| { - if let Some(ref mfgr) = opt.mfgr { - mfgr == &format!("{:?}", t.mfgr) - } else { - true - } - }) - // Specify chip - note: may match multiple - .filter(|t| { - if !opt.chip.is_empty() { - opt.chip.iter().any(|c| c == t.chip) - } else { - true - } - }) - // Run failable tests? - .filter(|t| opt.bad_tests || t.should_pass) - .collect::>(); - - if opt.list { - // FIXME: Prettier output - eprintln!("{:?}", tests.iter().map(|t| t.name()).collect::>()); - exit(0); - } - if tests.is_empty() { - eprintln!("No tests run, you might want to use `--bad-tests` and/or `--long-test`"); + match &opt.subcommand { + Subcommand::Tests(test_opts) => { + anyhow::ensure!( + test_opts.current_bin_path.exists(), + "svd2rust binary does not exist" + ); + + test_opts.run(&opt).with_context(|| "failed to run tests") + } + Subcommand::Diff(diff) => diff.run(&opt).with_context(|| "failed to run diff"), + Subcommand::Ci(ci) => ci.run(&opt).with_context(|| "failed to run ci"), } +} - let any_fails = AtomicBool::new(false); +macro_rules! gha_output { + ($fmt:literal$(, $args:expr)* $(,)?) => { + #[cfg(not(test))] + println!($fmt $(, $args)*); + #[cfg(test)] + eprintln!($fmt $(,$args)*); + }; +} - // TODO: It would be more efficient to reuse directories, so we don't - // have to rebuild all the deps crates - tests.par_iter().for_each(|t| { - let start = Instant::now(); +pub fn gha_print(content: &str) { + gha_output!("{}", content); +} - match svd_test::test(t, &bin_path, rustfmt_bin_path, opt.atomics, opt.verbose) { - Ok(s) => { - if let Some(stderrs) = s { - let mut buf = String::new(); - for stderr in stderrs { - read_file(&stderr, &mut buf); - } - eprintln!( - "Passed: {} - {} seconds\n{}", - t.name(), - start.elapsed().as_secs(), - buf - ); - } else { - eprintln!( - "Passed: {} - {} seconds", - t.name(), - start.elapsed().as_secs() - ); - } - } - Err(e) => { - any_fails.store(true, Ordering::Release); - let additional_info = if opt.verbose > 0 { - match *e.kind() { - errors::ErrorKind::ProcessFailed( - _, - _, - Some(ref stderr), - ref previous_processes_stderr, - ) => { - let mut buf = String::new(); - if opt.verbose > 1 { - for stderr in previous_processes_stderr { - read_file(&stderr, &mut buf); - } - } - read_file(&stderr, &mut buf); - buf - } - _ => "".into(), - } - } else { - "".into() - }; - eprintln!( - "Failed: {} - {} seconds. {}{}", - t.name(), - start.elapsed().as_secs(), - e.display_chain().to_string().trim_end(), - additional_info, - ); - } - } - }); +pub fn gha_error(content: &str) { + gha_output!("::error {}", content); +} - if any_fails.load(Ordering::Acquire) { - exit(1); - } else { - exit(0); +#[track_caller] +pub fn gha_output(tag: &str, content: &str) -> anyhow::Result<()> { + if content.contains('\n') { + // https://github.com/actions/toolkit/issues/403 + anyhow::bail!("output `{tag}` contains newlines, consider serializing with json and deserializing in gha with fromJSON()"); } + write_to_gha_env_file("GITHUB_OUTPUT", &format!("{tag}={content}"))?; + Ok(()) +} + +// https://docs.github.com/en/actions/using-workflows/workflow-commands-for-github-actions#environment-files +pub fn write_to_gha_env_file(env_name: &str, contents: &str) -> anyhow::Result<()> { + use std::io::Write; + let path = std::env::var(env_name)?; + let path = std::path::Path::new(&path); + let mut file = std::fs::OpenOptions::new().append(true).open(path)?; + writeln!(file, "{}", contents)?; + Ok(()) } diff --git a/ci/svd2rust-regress/src/svd_test.rs b/ci/svd2rust-regress/src/svd_test.rs index a1404660..bdb595c6 100644 --- a/ci/svd2rust-regress/src/svd_test.rs +++ b/ci/svd2rust-regress/src/svd_test.rs @@ -1,9 +1,15 @@ -use crate::errors::*; -use crate::tests::TestCase; -use std::fs::{self, File, OpenOptions}; +use anyhow::{anyhow, Context, Result}; +use svd2rust::{util::ToSanitizedCase, Target}; + +use crate::{command::CommandExt, tests::TestCase, Opts, TestOpts}; use std::io::prelude::*; use std::path::PathBuf; use std::process::{Command, Output}; +use std::{ + fmt::Write as _, + fs::{self, File, OpenOptions}, + path::Path, +}; const CRATES_ALL: &[&str] = &["critical-section = \"1.0\"", "vcell = \"0.1.2\""]; const CRATES_MSP430: &[&str] = &["msp430 = \"0.4.0\"", "msp430-rt = \"0.4.0\""]; @@ -17,63 +23,108 @@ const PROFILE_ALL: &[&str] = &["[profile.dev]", "incremental = false"]; const FEATURES_ALL: &[&str] = &["[features]"]; const FEATURES_XTENSALX: &[&str] = &["default = [\"xtensa-lx/esp32\", \"xtensa-lx-rt/esp32\"]"]; -fn path_helper(input: &[&str]) -> PathBuf { - input.iter().collect() -} - -fn path_helper_base(base: &PathBuf, input: &[&str]) -> PathBuf { - let mut path = base.clone(); - input.iter().for_each(|p| path.push(p)); - path +fn path_helper_base(base: &Path, input: &[&str]) -> PathBuf { + input + .iter() + .fold(base.to_owned(), |b: PathBuf, p| b.join(p)) } /// Create and write to file -fn file_helper(payload: &str, path: &PathBuf) -> Result<()> { - let mut f = File::create(path).chain_err(|| format!("Failed to create {path:?}"))?; +fn file_helper(payload: &str, path: &Path) -> Result<()> { + let mut f = OpenOptions::new() + .create(true) + .append(true) + .open(path) + .with_context(|| format!("Failed to create {path:?}"))?; f.write_all(payload.as_bytes()) - .chain_err(|| format!("Failed to write to {path:?}"))?; + .with_context(|| format!("Failed to write to {path:?}"))?; Ok(()) } +#[derive(thiserror::Error)] +#[error("Process failed - {command}")] +pub struct ProcessFailed { + pub command: String, + pub stderr: Option, + pub stdout: Option, + pub previous_processes_stderr: Vec, +} + +#[derive(Debug, thiserror::Error)] +pub enum TestError { + #[error("test case failed")] + Process(#[from] ProcessFailed), + #[error("Failed to run test")] + Other(#[from] anyhow::Error), +} + +impl std::fmt::Debug for ProcessFailed { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.write_str("Process failed") + } +} + trait CommandHelper { fn capture_outputs( - &self, + &mut self, cant_fail: bool, name: &str, stdout: Option<&PathBuf>, stderr: Option<&PathBuf>, previous_processes_stderr: &[PathBuf], - ) -> Result<()>; + ) -> Result<(), TestError>; } -impl CommandHelper for Output { +impl CommandHelper for Command { + #[tracing::instrument(skip_all, fields(stdout = tracing::field::Empty, stderr = tracing::field::Empty))] fn capture_outputs( - &self, + &mut self, cant_fail: bool, name: &str, stdout: Option<&PathBuf>, stderr: Option<&PathBuf>, previous_processes_stderr: &[PathBuf], - ) -> Result<()> { + ) -> Result<(), TestError> { + let output = self.get_output(true)?; + let out_payload = String::from_utf8_lossy(&output.stdout); if let Some(out) = stdout { - let out_payload = String::from_utf8_lossy(&self.stdout); file_helper(&out_payload, out)?; }; + let err_payload = String::from_utf8_lossy(&output.stderr); if let Some(err) = stderr { - let err_payload = String::from_utf8_lossy(&self.stderr); file_helper(&err_payload, err)?; }; - - if cant_fail && !self.status.success() { - return Err(ErrorKind::ProcessFailed( - name.into(), - stdout.cloned(), - stderr.cloned(), - previous_processes_stderr.to_vec(), - ) + if cant_fail && !output.status.success() { + let span = tracing::Span::current(); + let mut message = format!("Process failed: {}", self.display()); + if !out_payload.trim().is_empty() { + span.record( + "stdout", + tracing::field::display( + stdout.map(|p| p.display().to_string()).unwrap_or_default(), + ), + ); + write!(message, "\nstdout: \n{}", out_payload).unwrap(); + } + if !err_payload.trim().is_empty() { + span.record( + "stderr", + tracing::field::display( + stderr.map(|p| p.display().to_string()).unwrap_or_default(), + ), + ); + write!(message, "\nstderr: \n{}", err_payload).unwrap(); + } + tracing::error!(message=%message); + return Err(ProcessFailed { + command: name.into(), + stdout: stdout.cloned(), + stderr: stderr.cloned(), + previous_processes_stderr: previous_processes_stderr.to_vec(), + } .into()); } @@ -81,171 +132,245 @@ impl CommandHelper for Output { } } -pub fn test( - t: &TestCase, - bin_path: &PathBuf, - rustfmt_bin_path: Option<&PathBuf>, - atomics: bool, - verbosity: u8, -) -> Result>> { - let user = match std::env::var("USER") { - Ok(val) => val, - Err(_) => "rusttester".into(), - }; - - // Remove the existing chip directory, if it exists - let chip_dir = path_helper(&["output", &t.name()]); - if let Err(err) = fs::remove_dir_all(&chip_dir) { - match err.kind() { - std::io::ErrorKind::NotFound => (), - _ => Err(err).chain_err(|| "While removing chip directory")?, - } +impl TestCase { + #[tracing::instrument(skip(self, opts, test_opts), fields(name = %self.name()))] + pub fn test( + &self, + opts: &Opts, + test_opts: &TestOpts, + ) -> Result>, TestError> { + let (chip_dir, mut process_stderr_paths) = self + .setup_case( + &opts.output_dir, + &test_opts.current_bin_path, + test_opts.command.as_deref(), + ) + .with_context(|| anyhow!("when setting up case for {}", self.name()))?; + // Run `cargo check`, capturing stderr to a log file + let cargo_check_err_file = path_helper_base(&chip_dir, &["cargo-check.err.log"]); + Command::new("cargo") + .arg("check") + .current_dir(&chip_dir) + .capture_outputs( + true, + "cargo check", + None, + Some(&cargo_check_err_file), + &process_stderr_paths, + ) + .with_context(|| "failed to check")?; + process_stderr_paths.push(cargo_check_err_file); + Ok(if opts.verbose > 1 { + Some(process_stderr_paths) + } else { + None + }) } - // Used to build the output from stderr for -v and -vv* - let mut process_stderr_paths: Vec = vec![]; - - // Create a new cargo project. It is necesary to set the user, otherwise - // cargo init will not work (when running in a container with no user set) - Command::new("cargo") - .env("USER", user) - .arg("init") - .arg("--name") - .arg(&t.name()) - .arg("--vcs") - .arg("none") - .arg(&chip_dir) - .output() - .chain_err(|| "Failed to cargo init")? - .capture_outputs(true, "cargo init", None, None, &[])?; - - // Add some crates to the Cargo.toml of our new project - let svd_toml = path_helper_base(&chip_dir, &["Cargo.toml"]); - let mut file = OpenOptions::new() - .write(true) - .append(true) - .open(svd_toml) - .chain_err(|| "Failed to open Cargo.toml for appending")?; + #[tracing::instrument(skip(self, output_dir, command), fields(name = %self.name(), chip_dir = tracing::field::Empty))] - use crate::tests::Target; - let crates = CRATES_ALL - .iter() - .chain(match &t.arch { - Target::CortexM => CRATES_CORTEX_M.iter(), - Target::RISCV => CRATES_RISCV.iter(), - Target::Mips => CRATES_MIPS.iter(), - Target::Msp430 => CRATES_MSP430.iter(), - Target::XtensaLX => CRATES_XTENSALX.iter(), + pub fn setup_case( + &self, + output_dir: &Path, + svd2rust_bin_path: &Path, + command: Option<&str>, + ) -> Result<(PathBuf, Vec), TestError> { + let user = match std::env::var("USER") { + Ok(val) => val, + Err(_) => "rusttester".into(), + }; + let chip_dir = output_dir.join(self.name().to_sanitized_snake_case().as_ref()); + tracing::span::Span::current() + .record("chip_dir", tracing::field::display(chip_dir.display())); + if let Err(err) = fs::remove_dir_all(&chip_dir) { + match err.kind() { + std::io::ErrorKind::NotFound => (), + _ => Err(err).with_context(|| "While removing chip directory")?, + } + } + let mut process_stderr_paths: Vec = vec![]; + tracing::info!( + "Initializing cargo package for `{}` in {}", + self.name(), + chip_dir.display() + ); + Command::new("cargo") + .env("USER", user) + .arg("init") + .arg("--name") + .arg(self.name().to_sanitized_snake_case().as_ref()) + .arg("--vcs") + .arg("none") + .arg(&chip_dir) + .capture_outputs(true, "cargo init", None, None, &[]) + .with_context(|| "Failed to cargo init")?; + let svd_toml = path_helper_base(&chip_dir, &["Cargo.toml"]); + let mut file = OpenOptions::new() + .write(true) + .append(true) + .open(svd_toml) + .with_context(|| "Failed to open Cargo.toml for appending")?; + let crates = CRATES_ALL + .iter() + .chain(match &self.arch { + Target::CortexM => CRATES_CORTEX_M.iter(), + Target::RISCV => CRATES_RISCV.iter(), + Target::Mips => CRATES_MIPS.iter(), + Target::Msp430 => CRATES_MSP430.iter(), + Target::XtensaLX => CRATES_XTENSALX.iter(), + Target::None => unreachable!(), + }) + .chain(if command.unwrap_or_default().contains("--atomics") { + CRATES_ATOMICS.iter() + } else { + [].iter() + }) + .chain(PROFILE_ALL.iter()) + .chain(FEATURES_ALL.iter()) + .chain(match &self.arch { + Target::XtensaLX => FEATURES_XTENSALX.iter(), + _ => [].iter(), + }); + for c in crates { + writeln!(file, "{}", c).with_context(|| "Failed to append to file!")?; + } + tracing::info!("Downloading SVD"); + // FIXME: Avoid downloading multiple times, especially if we're using the diff command + let svd_url = &self.svd_url(); + let svd = reqwest::blocking::get(svd_url) + .with_context(|| format!("Failed to get svd URL: {svd_url}"))? + .error_for_status() + .with_context(|| anyhow!("Response is not ok for svd url"))? + .text() + .with_context(|| "SVD is bad text")?; + + let chip_svd = format!("{}.svd", &self.chip); + let svd_file = path_helper_base(&chip_dir, &[&chip_svd]); + file_helper(&svd, &svd_file)?; + let lib_rs_file = path_helper_base(&chip_dir, &["src", "lib.rs"]); + let src_dir = path_helper_base(&chip_dir, &["src"]); + let svd2rust_err_file = path_helper_base(&chip_dir, &["svd2rust.err.log"]); + let target = match self.arch { + Target::CortexM => "cortex-m", + Target::Msp430 => "msp430", + Target::Mips => "mips", + Target::RISCV => "riscv", + Target::XtensaLX => "xtensa-lx", Target::None => unreachable!(), - }) - .chain(if atomics { - CRATES_ATOMICS.iter() - } else { - [].iter() - }) - .chain(PROFILE_ALL.iter()) - .chain(FEATURES_ALL.iter()) - .chain(match &t.arch { - Target::XtensaLX => FEATURES_XTENSALX.iter(), - _ => [].iter(), - }); - - for c in crates { - writeln!(file, "{}", c).chain_err(|| "Failed to append to file!")?; - } + }; + tracing::info!("Running svd2rust"); + let mut svd2rust_bin = Command::new(svd2rust_bin_path); + if let Some(command) = command { + if !command.is_empty() { + svd2rust_bin.arg(command); + } + } + svd2rust_bin + .args(["-i", &chip_svd]) + .args(["--target", target]) + .current_dir(&chip_dir) + .capture_outputs( + true, + "svd2rust", + Some(&lib_rs_file).filter(|_| { + !matches!( + self.arch, + Target::CortexM | Target::Msp430 | Target::XtensaLX + ) + }), + Some(&svd2rust_err_file), + &[], + )?; + process_stderr_paths.push(svd2rust_err_file); + match self.arch { + Target::CortexM | Target::Mips | Target::Msp430 | Target::XtensaLX => { + // TODO: Give error the path to stderr + fs::rename(path_helper_base(&chip_dir, &["lib.rs"]), &lib_rs_file) + .with_context(|| "While moving lib.rs file")?; + } + _ => {} + } + let lib_rs = + fs::read_to_string(&lib_rs_file).with_context(|| "Failed to read lib.rs file")?; + let file = syn::parse_file(&lib_rs) + .with_context(|| format!("couldn't parse {}", lib_rs_file.display()))?; + File::options() + .write(true) + .open(&lib_rs_file) + .with_context(|| format!("couldn't open {}", lib_rs_file.display()))? + .write(prettyplease::unparse(&file).as_bytes()) + .with_context(|| format!("couldn't write {}", lib_rs_file.display()))?; + let rustfmt_err_file = path_helper_base(&chip_dir, &["rustfmt.err.log"]); + let form_err_file = path_helper_base(&chip_dir, &["form.err.log"]); + if let Some(form_bin_path) = crate::FORM.get() { + tracing::info!("Running form"); - // Download the SVD as specified in the URL - // TODO: Check for existing svd files? `--no-cache` flag? - let svd = reqwest::blocking::get(&t.svd_url()) - .chain_err(|| "Failed to get svd URL")? - .text() - .chain_err(|| "SVD is bad text")?; - - // Write SVD contents to file - let chip_svd = format!("{}.svd", &t.chip); - let svd_file = path_helper_base(&chip_dir, &[&chip_svd]); - file_helper(&svd, &svd_file)?; - - // Generate the lib.rs from the SVD file using the specified `svd2rust` binary - // If the architecture is cortex-m or msp430 we move the generated lib.rs file to src/ - let lib_rs_file = path_helper_base(&chip_dir, &["src", "lib.rs"]); - let svd2rust_err_file = path_helper_base(&chip_dir, &["svd2rust.err.log"]); - let target = match t.arch { - Target::CortexM => "cortex-m", - Target::Msp430 => "msp430", - Target::Mips => "mips", - Target::RISCV => "riscv", - Target::XtensaLX => "xtensa-lx", - Target::None => unreachable!(), - }; - let mut svd2rust_bin = Command::new(bin_path); - if atomics { - svd2rust_bin.arg("--atomics"); - } + // move the lib.rs file to src, then split with form. + let new_lib_rs_file = path_helper_base(&chip_dir, &["lib.rs"]); + std::fs::rename(lib_rs_file, &new_lib_rs_file) + .with_context(|| "While moving lib.rs file")?; + Command::new(form_bin_path) + .arg("--input") + .arg(&new_lib_rs_file) + .arg("--outdir") + .arg(&src_dir) + .capture_outputs( + true, + "form", + None, + Some(&form_err_file), + &process_stderr_paths, + ) + .with_context(|| "failed to form")?; + std::fs::remove_file(&new_lib_rs_file) + .with_context(|| "While removing lib.rs file after form")?; + } + if let Some(rustfmt_bin_path) = crate::RUSTFMT.get() { + tracing::info!("Running rustfmt"); + // Run `rusfmt`, capturing stderr to a log file - let output = svd2rust_bin - .args(&["-i", &chip_svd]) - .args(&["--target", &target]) - .current_dir(&chip_dir) - .output() - .chain_err(|| "failed to execute process")?; - output.capture_outputs( - true, - "svd2rust", - Some(&lib_rs_file).filter(|_| { - (t.arch != Target::CortexM) - && (t.arch != Target::Msp430) - && (t.arch != Target::XtensaLX) - }), - Some(&svd2rust_err_file), - &[], - )?; - process_stderr_paths.push(svd2rust_err_file); - - match t.arch { - Target::CortexM | Target::Mips | Target::Msp430 | Target::XtensaLX => { - // TODO: Give error the path to stderr - fs::rename(path_helper_base(&chip_dir, &["lib.rs"]), &lib_rs_file) - .chain_err(|| "While moving lib.rs file")? + // find all .rs files in src_dir and it's subdirectories + let mut src_files = vec![]; + visit_dirs(&src_dir, &mut |e: &fs::DirEntry| { + if e.path().extension().unwrap_or_default() == "rs" { + src_files.push(e.path()); + } + }) + .context("couldn't visit")?; + src_files.sort(); + + for entry in src_files { + let output = Command::new(rustfmt_bin_path) + .arg(entry) + .args(["--edition", "2021"]) + .capture_outputs( + false, + "rustfmt", + None, + Some(&rustfmt_err_file), + &process_stderr_paths, + ) + .with_context(|| "failed to format")?; + } + + process_stderr_paths.push(rustfmt_err_file); } - _ => {} + tracing::info!("Done processing"); + Ok((chip_dir, process_stderr_paths)) } +} - let rustfmt_err_file = path_helper_base(&chip_dir, &["rustfmt.err.log"]); - if let Some(rustfmt_bin_path) = rustfmt_bin_path { - // Run `cargo fmt`, capturing stderr to a log file - - let output = Command::new(rustfmt_bin_path) - .arg(lib_rs_file) - .output() - .chain_err(|| "failed to format")?; - output.capture_outputs( - false, - "rustfmt", - None, - Some(&rustfmt_err_file), - &process_stderr_paths, - )?; - process_stderr_paths.push(rustfmt_err_file); +fn visit_dirs(dir: &Path, cb: &mut dyn FnMut(&fs::DirEntry)) -> std::io::Result<()> { + if dir.is_dir() { + for entry in fs::read_dir(dir)? { + let entry = entry?; + let path = entry.path(); + if path.is_dir() { + visit_dirs(&path, cb)?; + } else { + cb(&entry); + } + } } - // Run `cargo check`, capturing stderr to a log file - let cargo_check_err_file = path_helper_base(&chip_dir, &["cargo-check.err.log"]); - let output = Command::new("cargo") - .arg("check") - .current_dir(&chip_dir) - .output() - .chain_err(|| "failed to check")?; - output.capture_outputs( - true, - "cargo check", - None, - Some(&cargo_check_err_file), - &process_stderr_paths, - )?; - process_stderr_paths.push(cargo_check_err_file); - Ok(if verbosity > 1 { - Some(process_stderr_paths) - } else { - None - }) + Ok(()) } diff --git a/ci/svd2rust-regress/src/tests.rs b/ci/svd2rust-regress/src/tests.rs index 9020924f..7cd31024 100644 --- a/ci/svd2rust-regress/src/tests.rs +++ b/ci/svd2rust-regress/src/tests.rs @@ -1,7 +1,12 @@ -pub use svd2rust::util::Target; -use svd2rust::util::ToSanitizedCase; +use self::RunWhen::*; +use anyhow::Context; +use serde::Serialize as _; +pub use svd2rust::Target; -#[derive(Debug)] +#[allow(clippy::upper_case_acronyms)] +#[derive( + Debug, serde::Serialize, serde::Deserialize, PartialOrd, Ord, PartialEq, Eq, Clone, Copy, +)] pub enum Manufacturer { Atmel, Freescale, @@ -20,8 +25,39 @@ pub enum Manufacturer { Espressif, } -#[derive(Debug)] +impl Manufacturer { + pub const fn all() -> &'static [Self] { + use self::Manufacturer::*; + &[ + Atmel, + Freescale, + Fujitsu, + Holtek, + Microchip, + Nordic, + Nuvoton, + NXP, + SiliconLabs, + Spansion, + STMicro, + Toshiba, + SiFive, + TexasInstruments, + Espressif, + ] + } +} + +impl std::fmt::Display for Manufacturer { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + self.serialize(f) + } +} + +#[derive(Debug, serde::Serialize, serde::Deserialize, Default)] +#[serde(rename_all = "kebab-case")] pub enum RunWhen { + #[default] Always, NotShort, @@ -29,27 +65,35 @@ pub enum RunWhen { Never, } +#[derive(serde::Serialize, serde::Deserialize)] pub struct TestCase { pub arch: Target, pub mfgr: Manufacturer, - pub chip: &'static str, - svd_url: Option<&'static str>, + pub chip: String, + #[serde(default, skip_serializing_if = "Option::is_none")] + svd_url: Option, + #[serde(default = "true_")] pub should_pass: bool, + #[serde(default)] run_when: RunWhen, } +fn true_() -> bool { + true +} + impl TestCase { pub fn svd_url(&self) -> String { - match self.svd_url { + match &self.svd_url { Some(u) => u.to_owned(), - None => format!("https://raw.githubusercontent.com/posborne/cmsis-svd/master/data/{vendor:?}/{chip}.svd", + None => format!("https://raw.githubusercontent.com/cmsis-svd/cmsis-svd-data/main/data/{vendor:?}/{chip}.svd", vendor = self.mfgr, chip = self.chip ) } } - pub fn should_run(&self, short_test: bool) -> bool { + pub const fn should_run(&self, short_test: bool) -> bool { match (&self.run_when, short_test) { (&Always, _) => true, (&NotShort, true) => false, @@ -58,4145 +102,34 @@ impl TestCase { } pub fn name(&self) -> String { - format!("{:?}-{}", self.mfgr, self.chip.replace(".", "_")) - .to_sanitized_snake_case() - .into() + format!("{:?}-{}", self.mfgr, self.chip.replace('.', "_")) } } -use self::Manufacturer::*; -use self::RunWhen::*; -use self::Target::{CortexM, Mips, Msp430, XtensaLX, RISCV}; +pub fn tests(test_cases: Option<&std::path::Path>) -> Result<&'static [TestCase], anyhow::Error> { + pub static TESTS: std::sync::OnceLock> = std::sync::OnceLock::new(); -// NOTE: All chip names must be unique! -pub const TESTS: &[&TestCase] = &[ - // BAD-SVD missing resetValue - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9CN11", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9CN12", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9G10", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9G15", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9G20", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9G25", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9G35", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9M10", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9M11", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9N12", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9X25", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "AT91SAM9X35", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3A4C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3A8C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N00A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N00B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N0A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N0B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N0C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N1A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N1B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N1C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N2A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N2B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N2C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N4A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N4B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3N4C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S1A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S1B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S1C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S2A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S2B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S2C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S4A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S4B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S4C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S8B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3S8C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3SD8B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3SD8C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3U1C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3U1E", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3U2C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3U2E", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3U4C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3U4E", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3X4C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3X4E", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3X8C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM3X8E", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM4S16B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM4S16C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM4S8B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM4S8C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM4SD32B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAM4SD32C", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMA5D31", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMA5D33", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMA5D34", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMA5D35", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // FIXME(#107) "failed to resolve. Use of undeclared type or module `sercom0`" - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21E15A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21E16A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21E17A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21E18A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21G16A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21G17A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21G18A", - svd_url: Some( - "https://raw.githubusercontent.com/wez/atsamd21-rs/master/svd/ATSAMD21G18A.svd", - ), - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21J16A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21J17A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMD21J18A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMR21E16A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMR21E17A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMR21E18A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMR21G16A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMR21G17A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Atmel, - chip: "ATSAMR21G18A", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // BAD-SVD bad enumeratedValue value - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV56F20", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV56F22", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV56F24", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV58F20", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV58F22", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV58F24", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // BAD-SVD field names are equivalent when case is ignored - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK61F15", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK61F15WS", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK70F12", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK70F15", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK70F15WS", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // Test 1/3 of these to save time - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK02F12810", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK10D10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK10D5", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK10D7", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK10DZ10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK10F12", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK11D5", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK11D5WS", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK11DA5", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK12D5", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK20D10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK20D5", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK20D7", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK20DZ10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK20F12", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK21D5", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK21D5WS", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK21DA5", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK21F12", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK21FA12", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK22D5", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK22F12", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK22F12810", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK22F25612", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK22F51212", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK22FA12", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK24F12", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK24F25612", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK26F18", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK30D10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK30D7", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK30DZ10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK40D10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK40D7", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK40DZ10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK50D10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK50D7", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK50DZ10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK51D10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK51D7", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK51DZ10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK52D10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK52DZ10", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK53D10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK53DZ10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK60D10", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK60DZ10", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK60F15", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK63F12", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK64F12", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK65F18", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK66F18", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK80F25615", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK81F25615", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MK82F25615", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE14F16", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE14Z7", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE15Z7", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE16F16", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE18F16", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL28T7_CORE0", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL28T7_CORE1", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL28Z7", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL81Z7", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL82Z7", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKS22F12", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV10Z1287", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV10Z7", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV11Z7", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV30F12810", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV31F12810", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV31F25612", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV31F51212", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV40F15", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV42F16", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV43F15", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV44F15", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV44F16", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV45F15", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV46F15", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKV46F16", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW20Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW21D5", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW21Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW22D5", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW24D5", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW30Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW31Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW40Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW41Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE02Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE04Z1284", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE04Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE06Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE14D7", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKE15D7", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL02Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL03Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL04Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL05Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL13Z644", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL14Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL15Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL16Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL17Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL17Z644", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL24Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL25Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL26Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL27Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL27Z644", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL33Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL33Z644", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL34Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL36Z4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL43Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKL46Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKM14ZA5", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKM33ZA5", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKM34Z7", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKM34ZA5", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "MKW01Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "SKEAZ1284", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "SKEAZN642", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Freescale, - chip: "SKEAZN84", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF10xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF10xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF11xK", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF11xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF11xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF11xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF12xK", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF12xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF13xK", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF13xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF13xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF13xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF14xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF14xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF14xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF15xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF15xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF15xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF1AxL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF1AxM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF1AxN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF31xK", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF31xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF31xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF31xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF34xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF34xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF34xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF42xK", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AF42xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFA3xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFA3xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFA3xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFA4xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFA4xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFA4xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFAAxL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFAAxM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFAAxN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFB4xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFB4xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9AFB4xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9B160L", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9B160R", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9B360L", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9B360R", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9B460L", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9B460R", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9B560L", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9B560R", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF10xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF10xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF11xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF11xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF11xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF11xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF12xJ", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF12xK", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF12xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF12xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF12xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF12xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF21xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF21xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF30xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF30xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF31xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF31xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF31xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF31xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF32xK", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF32xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF32xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF32xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF32xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF40xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF40xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF41xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF41xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF41xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF41xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF42xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF42xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF50xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF50xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF51xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF51xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF51xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF51xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF52xK", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF52xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF52xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF52xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF52xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF61xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BF61xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BFD1xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "MB9BFD1xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "S6E1A1", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Fujitsu, - chip: "S6E2CC", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Holtek, - chip: "ht32f125x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Holtek, - chip: "ht32f175x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Holtek, - chip: "ht32f275x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Nordic, - chip: "nrf51", - svd_url: None, - should_pass: true, - run_when: Always, - }, - // BAD-SVD two enumeratedValues have the same value - &TestCase { - arch: CortexM, - mfgr: Nordic, - chip: "nrf52", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Nuvoton, - chip: "M051_Series", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Nuvoton, - chip: "NUC100_Series", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // BAD-SVD two enumeratedValues have the same name - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC11Exx_v5", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC11Uxx_v7", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC11xx_v6a", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC11xx_v6", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC13Uxx_v1", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC15xx_v0.7", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC800_v0.3", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC11E6x_v0.8", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC176x5x_v0.2", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC11Cxx_v9", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // BAD-SVD missing resetValue - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC178x_7x", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC178x_7x_v0.8", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC408x_7x_v0.7", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC11Axxv0.6", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // BAD-SVD bad identifier: contains a '.' - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC11D14_svd_v4", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC13xx_svd_v1", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // BAD-SVD bad identifier: contains a '/' - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC18xx_svd_v18", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC43xx_43Sxx", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // BAD-SVD uses the identifier '_' to name a reserved bitfield value - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC1102_4_v4", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // FIXME(???) "duplicate definitions for `write`" - // #99 regression test - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "LPC5410x_v0.4", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "MK22F25612", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "MK22F51212", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: NXP, - chip: "MKW41Z4", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3C1x4_SVD", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3C1x6_SVD", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3C1x7_SVD", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3L1x4_SVD", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3L1x6_SVD", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3L1x7_SVD", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3U1x4_SVD", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3U1x6_SVD", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3U1x7_SVD", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - // FIXME(???) panicked at "c.text.clone()" - &TestCase { - arch: CortexM, - mfgr: SiliconLabs, - chip: "SIM3L1x8_SVD", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF12xK", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF12xL", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF42xK", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF42xL", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF12xJ", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF12xS", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF12xT", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF16xx", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF32xS", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF32xT", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF36xx", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF42xS", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF42xT", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF46xx", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF52xS", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF52xT", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF56xx", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - // Test half of these for the sake of time - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF10xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF10xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF11xK", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF11xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF11xM", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF11xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF13xK", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF13xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF13xM", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF13xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF14xL", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF14xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF14xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF15xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF15xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF15xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF31xK", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF31xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF31xM", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF31xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF34xL", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF34xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AF34xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AFA3xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AFA3xM", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AFA3xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AFA4xL", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AFA4xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AFA4xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AFB4xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AFB4xM", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9AFB4xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF10xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF10xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF11xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF11xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF11xS", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF11xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF12xK", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF12xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF12xM", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF21xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF21xT", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF30xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF30xR", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF31xN", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF31xR", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF31xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF31xT", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF32xK", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF32xL", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF32xM", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF40xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF40xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF41xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF41xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF41xS", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF41xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF50xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF50xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF51xN", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF51xR", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF51xS", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF51xT", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF52xK", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF52xL", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF52xM", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF61xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BF61xT", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BFD1xS", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: Spansion, - chip: "MB9BFD1xT", - svd_url: None, - should_pass: true, - run_when: NotShort, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F030", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F031x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F042x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F072x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F091x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F0xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F100xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F101xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F102xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F103xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F105xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F107xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F20x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F21x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F301", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F302", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F303", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F3x4", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F373", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F401", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F405", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F407", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F410", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F411", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F412", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F413", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F427", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F429", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F446", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F469", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F7x", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F7x2", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F7x3", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F7x5", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F7x6", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F7x7", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32F7x9", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32G07x", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32G431xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32G441xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32G471xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32G474xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32G483xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32G484xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L100", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L15xC", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L15xxE", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L15xxxA", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L1xx", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L4x6", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32W108", - svd_url: None, - should_pass: true, - run_when: Always, - }, - // FIXME(#91) "field is never used: `register`" - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L051x", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L052x", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L053x", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L062x", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: STMicro, - chip: "STM32L063x", - svd_url: None, - should_pass: false, - run_when: Never, - }, - // BAD-SVD resetValue is bigger than the register size - &TestCase { - arch: CortexM, - mfgr: Toshiba, - chip: "M365", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Toshiba, - chip: "M367", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Toshiba, - chip: "M368", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Toshiba, - chip: "M369", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Toshiba, - chip: "M36B", - svd_url: None, - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: CortexM, - mfgr: Toshiba, - chip: "M061", - svd_url: None, - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: RISCV, - mfgr: SiFive, - chip: "E310x", - svd_url: Some("https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x.svd"), - should_pass: false, - run_when: Never, - }, - &TestCase { - arch: Msp430, - mfgr: TexasInstruments, - chip: "msp430g2553", - svd_url: Some("https://github.com/pftbest/msp430g2553/raw/v0.1.3-svd/msp430g2553.svd"), - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: Msp430, - mfgr: TexasInstruments, - chip: "msp430fr2355", - svd_url: Some( - "https://raw.githubusercontent.com/YuhanLiin/msp430fr2355/master/msp430fr2355.svd", - ), - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: XtensaLX, - mfgr: Espressif, - chip: "esp32", - svd_url: Some( - "https://raw.githubusercontent.com/espressif/svd/main/svd/esp32.svd", - ), - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: XtensaLX, - mfgr: Espressif, - chip: "esp32s2", - svd_url: Some( - "https://raw.githubusercontent.com/espressif/svd/main/svd/esp32s2.svd", - ), - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: XtensaLX, - mfgr: Espressif, - chip: "esp32s3", - svd_url: Some( - "https://raw.githubusercontent.com/espressif/svd/main/svd/esp32s3.svd", - ), - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: RISCV, - mfgr: Espressif, - chip: "esp32c3", - svd_url: Some( - "https://raw.githubusercontent.com/espressif/svd/main/svd/esp32c3.svd", - ), - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: Mips, - mfgr: Microchip, - chip: "pic32mx170f256b", - svd_url: Some( - "https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx1xxfxxxb/PIC32MX170F256B.svd.patched", - ), - should_pass: true, - run_when: Always, - }, - &TestCase { - arch: Mips, - mfgr: Microchip, - chip: "pic32mx270f256b", - svd_url: Some( - "https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx2xxfxxxb/PIC32MX270F256B.svd.patched", - ), - should_pass: true, - run_when: Always, - }, -]; + if let Some(cases) = TESTS.get() { + Ok(cases) + } else { + let path = test_cases.ok_or_else(|| anyhow::format_err!("no test cases specified"))?; + let cases: Vec = if path.extension() != Some(std::ffi::OsStr::new("yml")) { + serde_json::from_reader( + std::fs::OpenOptions::new() + .read(true) + .open(path) + .with_context(|| format!("couldn't open file {}", path.display()))?, + )? + } else if path.extension() != Some(std::ffi::OsStr::new("json")) { + serde_yaml::from_reader( + std::fs::OpenOptions::new() + .read(true) + .open(path) + .with_context(|| format!("couldn't open file {}", path.display()))?, + )? + } else { + anyhow::bail!("unknown file extension for {}", path.display()); + }; + Ok(TESTS.get_or_init(|| cases)) + } +} diff --git a/ci/svd2rust-regress/tests.yml b/ci/svd2rust-regress/tests.yml new file mode 100644 index 00000000..a1dadb4a --- /dev/null +++ b/ci/svd2rust-regress/tests.yml @@ -0,0 +1,2139 @@ +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9CN11 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9CN12 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G09 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G15 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G20 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G25 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9G35 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9M10 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9M11 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9N12 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9X25 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: AT91SAM9X35 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3A4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3A8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N00A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N00B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N0A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N0B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N0C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N1A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N1B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N1C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N2A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N2B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N2C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N4A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N4B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3N4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S1A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S1B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S1C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S2A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S2B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S2C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S4A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S4B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S8B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3S8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3SD8B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3SD8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U1C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U1E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U2C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U2E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3U4E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3X4C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3X4E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3X8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM3X8E + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4S16B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4S16C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4S8B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4S8C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4SD32B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAM4SD32C + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMA5D31 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMA5D33 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMA5D34 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMA5D35 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21E15A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21E16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21E17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21E18A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21G16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21G17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21G18A + svd_url: https://raw.githubusercontent.com/wez/atsamd21-rs/master/svd/ATSAMD21G18A.svd + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21J16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21J17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMD21J18A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21E16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21E17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21E18A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21G16A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21G17A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Atmel + chip: ATSAMR21G18A + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV56F20 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV56F22 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV56F24 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV58F20 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV58F22 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MKV58F24 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK61F15 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK61F15WS + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK70F12 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK70F15 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK70F15WS + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Freescale + chip: MK02F12810 +- arch: cortex-m + mfgr: Freescale + chip: MK10D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK10D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK10D7 +- arch: cortex-m + mfgr: Freescale + chip: MK10DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK10F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK11D5 +- arch: cortex-m + mfgr: Freescale + chip: MK11D5WS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK11DA5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK12D5 +- arch: cortex-m + mfgr: Freescale + chip: MK20D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK20D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK20D7 +- arch: cortex-m + mfgr: Freescale + chip: MK20DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK20F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK21D5 +- arch: cortex-m + mfgr: Freescale + chip: MK21D5WS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK21DA5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK21F12 +- arch: cortex-m + mfgr: Freescale + chip: MK21FA12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK22D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK22F12 +- arch: cortex-m + mfgr: Freescale + chip: MK22F12810 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK22F25612 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK22F51212 +- arch: cortex-m + mfgr: Freescale + chip: MK22FA12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK24F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK24F25612 +- arch: cortex-m + mfgr: Freescale + chip: MK26F18 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK30D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK30D7 +- arch: cortex-m + mfgr: Freescale + chip: MK30DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK40D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK40D7 +- arch: cortex-m + mfgr: Freescale + chip: MK40DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK50D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK50D7 +- arch: cortex-m + mfgr: Freescale + chip: MK50DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK51D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK51D7 +- arch: cortex-m + mfgr: Freescale + chip: MK51DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK52D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK52DZ10 +- arch: cortex-m + mfgr: Freescale + chip: MK53D10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK53DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK60D10 +- arch: cortex-m + mfgr: Freescale + chip: MK60DZ10 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK60F15 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK63F12 +- arch: cortex-m + mfgr: Freescale + chip: MK64F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK65F18 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK66F18 +- arch: cortex-m + mfgr: Freescale + chip: MK80F25615 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK81F25615 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MK82F25615 +- arch: cortex-m + mfgr: Freescale + chip: MKE14F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE14Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE15Z7 +- arch: cortex-m + mfgr: Freescale + chip: MKE16F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE18F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL28T7_CORE0 +- arch: cortex-m + mfgr: Freescale + chip: MKL28T7_CORE1 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL28Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL81Z7 +- arch: cortex-m + mfgr: Freescale + chip: MKL82Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKS22F12 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV10Z1287 +- arch: cortex-m + mfgr: Freescale + chip: MKV10Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV11Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV30F12810 +- arch: cortex-m + mfgr: Freescale + chip: MKV31F12810 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV31F25612 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV31F51212 +- arch: cortex-m + mfgr: Freescale + chip: MKV40F15 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV42F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV43F15 +- arch: cortex-m + mfgr: Freescale + chip: MKV44F15 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV44F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV45F15 +- arch: cortex-m + mfgr: Freescale + chip: MKV46F15 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKV46F16 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW20Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKW21D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW21Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW22D5 +- arch: cortex-m + mfgr: Freescale + chip: MKW24D5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW30Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW31Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKW40Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKW41Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE02Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKE04Z1284 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE04Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE06Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKE14D7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKE15D7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL02Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL03Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL04Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL05Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL13Z644 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL14Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL15Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL16Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL17Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL17Z644 +- arch: cortex-m + mfgr: Freescale + chip: MKL24Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL25Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL26Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL27Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL27Z644 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL33Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL33Z644 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL34Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL36Z4 +- arch: cortex-m + mfgr: Freescale + chip: MKL43Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKL46Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKM14ZA5 +- arch: cortex-m + mfgr: Freescale + chip: MKM33ZA5 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKM34Z7 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: MKM34ZA5 +- arch: cortex-m + mfgr: Freescale + chip: MKW01Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: SKEAZ1284 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Freescale + chip: SKEAZN642 +- arch: cortex-m + mfgr: Freescale + chip: SKEAZN84 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF10xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF10xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF11xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF11xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF11xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF11xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF12xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF12xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF13xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF13xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF13xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF13xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF14xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF14xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF14xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF15xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF15xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF15xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF1AxL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF1AxM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF1AxN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF31xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF31xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF31xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF31xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF34xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF34xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF34xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF42xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AF42xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA3xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA3xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA3xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA4xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA4xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFA4xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFAAxL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFAAxM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFAAxN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFB4xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFB4xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9AFB4xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B160L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B160R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B360L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B360R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B460L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B460R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B560L +- arch: cortex-m + mfgr: Fujitsu + chip: MB9B560R +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF10xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF10xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF11xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF11xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF11xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF11xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xJ +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF12xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF21xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF21xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF30xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF30xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF31xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF31xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF31xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF31xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF32xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF40xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF40xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF41xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF41xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF41xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF41xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF42xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF42xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF50xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF50xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF51xN +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF51xR +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF51xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF51xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xK +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xL +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xM +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF52xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF61xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BF61xT +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BFD1xS +- arch: cortex-m + mfgr: Fujitsu + chip: MB9BFD1xT +- arch: cortex-m + mfgr: Fujitsu + chip: S6E1A1 +- arch: cortex-m + mfgr: Fujitsu + chip: S6E2CC +- arch: cortex-m + mfgr: Holtek + chip: ht32f125x +- arch: cortex-m + mfgr: Holtek + chip: ht32f175x +- arch: cortex-m + mfgr: Holtek + chip: ht32f275x +- arch: cortex-m + mfgr: Nordic + chip: nrf51 +- arch: cortex-m + mfgr: Nordic + chip: nrf52 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Nuvoton + chip: M051_Series + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Nuvoton + chip: NUC100_Series + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11Exx_v5 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11Uxx_v7 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11xx_v6a + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11xx_v6 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC13Uxx_v1 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC15xx_v0.7 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC800_v0.3 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11E6x_v0.8 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC176x5x_v0.2 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11Cxx_v9 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC178x_7x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC178x_7x_v0.8 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC408x_7x_v0.7 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11Axxv0.6 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC11D14_svd_v4 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC13xx_svd_v1 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC18xx_svd_v18 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC43xx_43Sxx + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC1102_4_v4 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: LPC5410x_v0.4 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: NXP + chip: MK22F25612 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: NXP + chip: MK22F51212 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: NXP + chip: MKW41Z4 + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3C1x4_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3C1x6_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3C1x7_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3L1x4_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3L1x6_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3L1x7_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3U1x4_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3U1x6_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3U1x7_SVD + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: SiliconLabs + chip: SIM3L1x8_SVD + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Spansion + chip: MB9AF12xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF12xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF42xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF42xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xJ + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF16xx + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF36xx + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF42xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF42xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF46xx + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF56xx + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF10xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF10xR +- arch: cortex-m + mfgr: Spansion + chip: MB9AF11xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF11xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AF11xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF11xN +- arch: cortex-m + mfgr: Spansion + chip: MB9AF13xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF13xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AF13xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF13xN +- arch: cortex-m + mfgr: Spansion + chip: MB9AF14xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF14xM +- arch: cortex-m + mfgr: Spansion + chip: MB9AF14xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF15xM +- arch: cortex-m + mfgr: Spansion + chip: MB9AF15xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF15xR +- arch: cortex-m + mfgr: Spansion + chip: MB9AF31xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF31xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AF31xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF31xN +- arch: cortex-m + mfgr: Spansion + chip: MB9AF34xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AF34xM +- arch: cortex-m + mfgr: Spansion + chip: MB9AF34xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA3xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA3xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA3xN +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA4xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA4xM +- arch: cortex-m + mfgr: Spansion + chip: MB9AFA4xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFB4xL +- arch: cortex-m + mfgr: Spansion + chip: MB9AFB4xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9AFB4xN +- arch: cortex-m + mfgr: Spansion + chip: MB9BF10xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF10xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF11xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF11xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF11xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF11xT +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xL +- arch: cortex-m + mfgr: Spansion + chip: MB9BF12xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF21xS +- arch: cortex-m + mfgr: Spansion + chip: MB9BF21xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF30xN +- arch: cortex-m + mfgr: Spansion + chip: MB9BF30xR + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF31xN +- arch: cortex-m + mfgr: Spansion + chip: MB9BF31xR + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF31xS +- arch: cortex-m + mfgr: Spansion + chip: MB9BF31xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xK +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xL + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF32xM +- arch: cortex-m + mfgr: Spansion + chip: MB9BF40xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF40xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF41xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF41xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF41xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF41xT +- arch: cortex-m + mfgr: Spansion + chip: MB9BF50xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF50xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF51xN + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF51xR +- arch: cortex-m + mfgr: Spansion + chip: MB9BF51xS + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF51xT +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xK + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xL +- arch: cortex-m + mfgr: Spansion + chip: MB9BF52xM + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BF61xS +- arch: cortex-m + mfgr: Spansion + chip: MB9BF61xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: Spansion + chip: MB9BFD1xS +- arch: cortex-m + mfgr: Spansion + chip: MB9BFD1xT + should_pass: true + run_when: not-short +- arch: cortex-m + mfgr: STMicro + chip: STM32F030 +- arch: cortex-m + mfgr: STMicro + chip: STM32F0x2 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f0x2.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F103 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f103.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F411 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f411.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F469 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f469.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x3 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32f7x3.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32G070 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32g070.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32G473 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32g473.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32H753 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32h753.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32L0x3 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l0x3.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32L162 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l162.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32L4x6 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l4x6.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32L562 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32l562.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32MP157 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32mp157.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32WB55 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32wb55.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32WLE5 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32wle5.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32C011 + svd_url: https://stm32-rs.github.io/stm32-rs/stm32c011.svd.patched +- arch: cortex-m + mfgr: STMicro + chip: STM32F031x +- arch: cortex-m + mfgr: STMicro + chip: STM32F042x +- arch: cortex-m + mfgr: STMicro + chip: STM32F072x +- arch: cortex-m + mfgr: STMicro + chip: STM32F091x +- arch: cortex-m + mfgr: STMicro + chip: STM32F0xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F100xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F101xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F102xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F105xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F107xx +- arch: cortex-m + mfgr: STMicro + chip: STM32F20x +- arch: cortex-m + mfgr: STMicro + chip: STM32F21x +- arch: cortex-m + mfgr: STMicro + chip: STM32F301 +- arch: cortex-m + mfgr: STMicro + chip: STM32F302 +- arch: cortex-m + mfgr: STMicro + chip: STM32F303 +- arch: cortex-m + mfgr: STMicro + chip: STM32F3x4 +- arch: cortex-m + mfgr: STMicro + chip: STM32F373 +- arch: cortex-m + mfgr: STMicro + chip: STM32F401 +- arch: cortex-m + mfgr: STMicro + chip: STM32F405 +- arch: cortex-m + mfgr: STMicro + chip: STM32F407 +- arch: cortex-m + mfgr: STMicro + chip: STM32F410 +- arch: cortex-m + mfgr: STMicro + chip: STM32F412 +- arch: cortex-m + mfgr: STMicro + chip: STM32F413 +- arch: cortex-m + mfgr: STMicro + chip: STM32F427 +- arch: cortex-m + mfgr: STMicro + chip: STM32F429 +- arch: cortex-m + mfgr: STMicro + chip: STM32F446 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x2 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x5 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x6 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x7 +- arch: cortex-m + mfgr: STMicro + chip: STM32F7x9 +- arch: cortex-m + mfgr: STMicro + chip: STM32G07x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32G431xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G441xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G471xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G474xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G483xx +- arch: cortex-m + mfgr: STMicro + chip: STM32G484xx +- arch: cortex-m + mfgr: STMicro + chip: STM32L100 +- arch: cortex-m + mfgr: STMicro + chip: STM32L15xC +- arch: cortex-m + mfgr: STMicro + chip: STM32L15xxE +- arch: cortex-m + mfgr: STMicro + chip: STM32L15xxxA +- arch: cortex-m + mfgr: STMicro + chip: STM32L1xx +- arch: cortex-m + mfgr: STMicro + chip: STM32W108 +- arch: cortex-m + mfgr: STMicro + chip: STM32L051x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32L052x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32L053x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32L062x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: STMicro + chip: STM32L063x + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M365 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M367 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M368 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M369 + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M36B + should_pass: false + run_when: never +- arch: cortex-m + mfgr: Toshiba + chip: M061 +- arch: riscv + mfgr: SiFive + chip: E310x + svd_url: https://raw.githubusercontent.com/riscv-rust/e310x/master/e310x.svd + should_pass: false + run_when: never +- arch: msp430 + mfgr: TexasInstruments + chip: msp430g2553 + svd_url: https://github.com/pftbest/msp430g2553/raw/v0.1.3-svd/msp430g2553.svd +- arch: msp430 + mfgr: TexasInstruments + chip: msp430fr2355 + svd_url: https://raw.githubusercontent.com/YuhanLiin/msp430fr2355/master/msp430fr2355.svd +- arch: xtensa-lx + mfgr: Espressif + chip: esp32 + svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32.svd +- arch: xtensa-lx + mfgr: Espressif + chip: esp32s2 + svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32s2.svd +- arch: xtensa-lx + mfgr: Espressif + chip: esp32s3 + svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32s3.svd +- arch: riscv + mfgr: Espressif + chip: esp32c3 + svd_url: https://raw.githubusercontent.com/espressif/svd/main/svd/esp32c3.svd +- arch: mips + mfgr: Microchip + chip: pic32mx170f256b + svd_url: https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx1xxfxxxb/PIC32MX170F256B.svd.patched +- arch: mips + mfgr: Microchip + chip: pic32mx270f256b + svd_url: https://raw.githubusercontent.com/kiffie/pic32-pac/master/pic32mx2xxfxxxb/PIC32MX270F256B.svd.patched diff --git a/src/config.rs b/src/config.rs index c80dc561..7656bf43 100644 --- a/src/config.rs +++ b/src/config.rs @@ -32,7 +32,7 @@ pub struct Config { #[allow(clippy::upper_case_acronyms)] #[allow(non_camel_case_types)] -#[cfg_attr(feature = "serde", derive(serde::Deserialize))] +#[cfg_attr(feature = "serde", derive(serde::Deserialize, serde::Serialize))] #[derive(Clone, Copy, PartialEq, Eq, Debug, Default)] pub enum Target { #[cfg_attr(feature = "serde", serde(rename = "cortex-m"))] @@ -50,6 +50,19 @@ pub enum Target { None, } +impl std::fmt::Display for Target { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + f.write_str(match self { + Target::CortexM => "cortex-m", + Target::Msp430 => "msp430", + Target::RISCV => "riscv", + Target::XtensaLX => "xtensa-lx", + Target::Mips => "mips", + Target::None => "none", + }) + } +} + impl Target { pub fn parse(s: &str) -> Result { Ok(match s { @@ -62,6 +75,11 @@ impl Target { _ => bail!("unknown target {}", s), }) } + + pub const fn all() -> &'static [Target] { + use self::Target::*; + &[CortexM, Msp430, RISCV, XtensaLX, Mips] + } } #[cfg_attr( diff --git a/src/util.rs b/src/util.rs index 722a24cb..547d879a 100644 --- a/src/util.rs +++ b/src/util.rs @@ -144,7 +144,7 @@ pub fn respace(s: &str) -> String { pub fn escape_brackets(s: &str) -> String { s.split('[') - .fold("".to_string(), |acc, x| { + .fold(String::new(), |acc, x| { if acc.is_empty() { x.to_string() } else if acc.ends_with('\\') { @@ -154,7 +154,7 @@ pub fn escape_brackets(s: &str) -> String { } }) .split(']') - .fold("".to_string(), |acc, x| { + .fold(String::new(), |acc, x| { if acc.is_empty() { x.to_string() } else if acc.ends_with('\\') { @@ -445,11 +445,13 @@ pub fn peripheral_names(d: &Device) -> Vec { for p in &d.peripherals { match p { Peripheral::Single(info) => { - v.push(replace_suffix(&info.name.to_sanitized_snake_case(), "")) + v.push(replace_suffix(&info.name.to_sanitized_snake_case(), "")); + } + Peripheral::Array(info, dim) => { + v.extend( + svd_rs::array::names(info, dim).map(|n| n.to_sanitized_snake_case().into()), + ); } - Peripheral::Array(info, dim) => v.extend( - svd_rs::array::names(info, dim).map(|n| n.to_sanitized_snake_case().into()), - ), } } v.sort();