From 0321498a85a597894fadaded78c430280c897b5d Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@gmail.com>
Date: Wed, 3 Jul 2019 02:13:11 +0000
Subject: [PATCH] [ELF][RISCV] Support RISC-V in getBitcodeMachineKind

Add Triple::riscv64 and Triple::riscv32 to getBitcodeMachineKind for get right
e_machine during LTO.

Reviewed By: ruiu, MaskRay

Differential Revision: https://reviews.llvm.org/D52165

llvm-svn: 364996
---
 lld/ELF/InputFiles.cpp      |  3 +++
 lld/test/ELF/lto/riscv32.ll | 10 ++++++++++
 lld/test/ELF/lto/riscv64.ll | 10 ++++++++++
 3 files changed, 23 insertions(+)
 create mode 100644 lld/test/ELF/lto/riscv32.ll
 create mode 100644 lld/test/ELF/lto/riscv64.ll

diff --git a/lld/ELF/InputFiles.cpp b/lld/ELF/InputFiles.cpp
index bc7e61072e642..4b5aa2c106f29 100644
--- a/lld/ELF/InputFiles.cpp
+++ b/lld/ELF/InputFiles.cpp
@@ -1086,6 +1086,9 @@ static uint8_t getBitcodeMachineKind(StringRef Path, const Triple &T) {
   case Triple::ppc64:
   case Triple::ppc64le:
     return EM_PPC64;
+  case Triple::riscv32:
+  case Triple::riscv64:
+    return EM_RISCV;
   case Triple::x86:
     return T.isOSIAMCU() ? EM_IAMCU : EM_386;
   case Triple::x86_64:
diff --git a/lld/test/ELF/lto/riscv32.ll b/lld/test/ELF/lto/riscv32.ll
new file mode 100644
index 0000000000000..1fe5547748fc3
--- /dev/null
+++ b/lld/test/ELF/lto/riscv32.ll
@@ -0,0 +1,10 @@
+; REQUIRES: riscv
+
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
+target triple = "riscv32-unknown-elf"
+
+define void @f() {
+  ret void
+}
diff --git a/lld/test/ELF/lto/riscv64.ll b/lld/test/ELF/lto/riscv64.ll
new file mode 100644
index 0000000000000..59de1de4a8d91
--- /dev/null
+++ b/lld/test/ELF/lto/riscv64.ll
@@ -0,0 +1,10 @@
+; REQUIRES: riscv
+
+; RUN: llvm-as %s -o %t.o
+; RUN: ld.lld %t.o -o %t
+target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
+target triple = "riscv64-unknown-elf"
+
+define void @f() {
+  ret void
+}