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[RISCV] Add fixed-length vector instrinsics for segment load
Inspired by reviews.llvm.org/D107790. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D119834
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‎llvm/include/llvm/IR/IntrinsicsRISCV.td

+10
Original file line numberDiff line numberDiff line change
@@ -1499,6 +1499,16 @@ let TargetPrefix = "riscv" in {
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[llvm_anyvector_ty, llvm_anyptr_ty,
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llvm_anyint_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
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[NoCapture<ArgIndex<1>>, IntrWriteMem]>;
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// Segment loads for fixed vectors.
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foreach nf = [2, 3, 4, 5, 6, 7, 8] in {
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def int_riscv_seg # nf # _load
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: Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
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!add(nf, -1))),
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[llvm_anyptr_ty, llvm_anyint_ty],
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[NoCapture<ArgIndex<0>>, IntrReadMem]>;
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}
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} // TargetPrefix = "riscv"
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+54
Original file line numberDiff line numberDiff line change
@@ -1126,6 +1126,24 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
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Info.size = MemoryLocation::UnknownSize;
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Info.flags |= MachineMemOperand::MOStore;
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return true;
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case Intrinsic::riscv_seg2_load:
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case Intrinsic::riscv_seg3_load:
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case Intrinsic::riscv_seg4_load:
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case Intrinsic::riscv_seg5_load:
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case Intrinsic::riscv_seg6_load:
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case Intrinsic::riscv_seg7_load:
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case Intrinsic::riscv_seg8_load:
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Info.opc = ISD::INTRINSIC_W_CHAIN;
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Info.ptrVal = I.getArgOperand(0);
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Info.memVT =
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getValueType(DL, I.getType()->getStructElementType(0)->getScalarType());
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Info.align =
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Align(DL.getTypeSizeInBits(
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I.getType()->getStructElementType(0)->getScalarType()) /
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8);
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Info.size = MemoryLocation::UnknownSize;
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Info.flags |= MachineMemOperand::MOLoad;
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return true;
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}
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}
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@@ -4878,6 +4896,42 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
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Result = convertFromScalableVector(VT, Result, DAG, Subtarget);
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return DAG.getMergeValues({Result, Chain}, DL);
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}
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case Intrinsic::riscv_seg2_load:
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case Intrinsic::riscv_seg3_load:
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case Intrinsic::riscv_seg4_load:
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case Intrinsic::riscv_seg5_load:
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case Intrinsic::riscv_seg6_load:
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case Intrinsic::riscv_seg7_load:
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case Intrinsic::riscv_seg8_load: {
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SDLoc DL(Op);
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static const Intrinsic::ID VlsegInts[7] = {
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Intrinsic::riscv_vlseg2, Intrinsic::riscv_vlseg3,
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Intrinsic::riscv_vlseg4, Intrinsic::riscv_vlseg5,
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Intrinsic::riscv_vlseg6, Intrinsic::riscv_vlseg7,
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Intrinsic::riscv_vlseg8};
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unsigned NF = Op->getNumValues() - 1;
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assert(NF >= 2 && NF <= 8 && "Unexpected seg number");
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MVT XLenVT = Subtarget.getXLenVT();
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MVT VT = Op->getSimpleValueType(0);
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MVT ContainerVT = getContainerForFixedLengthVector(VT);
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SDValue VL = DAG.getConstant(VT.getVectorNumElements(), DL, XLenVT);
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SDValue IntID = DAG.getTargetConstant(VlsegInts[NF - 2], DL, XLenVT);
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auto *Load = cast<MemIntrinsicSDNode>(Op);
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SmallVector<EVT, 9> ContainerVTs(NF, ContainerVT);
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ContainerVTs.push_back(MVT::Other);
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SDVTList VTs = DAG.getVTList(ContainerVTs);
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SDValue Result =
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DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs,
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{Load->getChain(), IntID, Op.getOperand(2), VL},
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Load->getMemoryVT(), Load->getMemOperand());
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SmallVector<SDValue, 9> Results;
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for (unsigned int RetIdx = 0; RetIdx < NF; RetIdx++)
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Results.push_back(convertFromScalableVector(VT, Result.getValue(RetIdx),
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DAG, Subtarget));
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Results.push_back(Result.getValue(NF));
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return DAG.getMergeValues(Results, DL);
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}
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}
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48834937
return lowerVectorIntrinsicScalars(Op, DAG, Subtarget);

‎llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll

+129
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,129 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple riscv64 -mattr=+zve64x -riscv-v-vector-bits-min=128 < %s \
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; RUN: | FileCheck %s
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define <8 x i8> @load_factor2(<16 x i8>* %ptr) {
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; CHECK-LABEL: load_factor2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vlseg2e8.v v7, (a0)
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; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
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; CHECK-NEXT: ret
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%1 = bitcast <16 x i8>* %ptr to i8*
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%2 = call { <8 x i8>, <8 x i8> } @llvm.riscv.seg2.load.v8i8.p0i8.i64(i8* %1, i64 8)
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%3 = extractvalue { <8 x i8>, <8 x i8> } %2, 0
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%4 = extractvalue { <8 x i8>, <8 x i8> } %2, 1
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ret <8 x i8> %4
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}
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define <8 x i8> @load_factor3(<24 x i8>* %ptr) {
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; CHECK-LABEL: load_factor3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vlseg3e8.v v6, (a0)
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; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v6_v7_v8
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; CHECK-NEXT: ret
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%1 = bitcast <24 x i8>* %ptr to i8*
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%2 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg3.load.v8i8.p0i8.i64(i8* %1, i64 8)
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%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
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%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
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%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
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ret <8 x i8> %5
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}
33+
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define <8 x i8> @load_factor4(<32 x i8>* %ptr) {
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; CHECK-LABEL: load_factor4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vlseg4e8.v v5, (a0)
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; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v5_v6_v7_v8
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; CHECK-NEXT: ret
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%1 = bitcast <32 x i8>* %ptr to i8*
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%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg4.load.v8i8.p0i8.i64(i8* %1, i64 8)
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%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
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%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
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%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
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%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
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ret <8 x i8> %6
48+
}
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define <8 x i8> @load_factor5(<40 x i8>* %ptr) {
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; CHECK-LABEL: load_factor5:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vlseg5e8.v v4, (a0)
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; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v4_v5_v6_v7_v8
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; CHECK-NEXT: ret
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%1 = bitcast <40 x i8>* %ptr to i8*
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%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg5.load.v8i8.p0i8.i64(i8* %1, i64 8)
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%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
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%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
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%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
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%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
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%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4
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ret <8 x i8> %7
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}
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define <8 x i8> @load_factor6(<48 x i8>* %ptr) {
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; CHECK-LABEL: load_factor6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vlseg6e8.v v3, (a0)
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; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v3_v4_v5_v6_v7_v8
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; CHECK-NEXT: ret
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%1 = bitcast <48 x i8>* %ptr to i8*
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%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg6.load.v8i8.p0i8.i64(i8* %1, i64 8)
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%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
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%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
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%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
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%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
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%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4
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%8 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 5
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ret <8 x i8> %8
83+
}
84+
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define <8 x i8> @load_factor7(<56 x i8>* %ptr) {
86+
; CHECK-LABEL: load_factor7:
87+
; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vlseg7e8.v v2, (a0)
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; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v2_v3_v4_v5_v6_v7_v8
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; CHECK-NEXT: ret
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%1 = bitcast <56 x i8>* %ptr to i8*
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%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg7.load.v8i8.p0i8.i64(i8* %1, i64 8)
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%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
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%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
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%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
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%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
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%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4
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%8 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 5
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%9 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 6
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ret <8 x i8> %9
102+
}
103+
104+
define <8 x i8> @load_factor8(<64 x i8>* %ptr) {
105+
; CHECK-LABEL: load_factor8:
106+
; CHECK: # %bb.0:
107+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
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; CHECK-NEXT: vlseg8e8.v v1, (a0)
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; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v1_v2_v3_v4_v5_v6_v7_v8
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; CHECK-NEXT: ret
111+
%1 = bitcast <64 x i8>* %ptr to i8*
112+
%2 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg8.load.v8i8.p0i8.i64(i8* %1, i64 8)
113+
%3 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 0
114+
%4 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 1
115+
%5 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 2
116+
%6 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 3
117+
%7 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 4
118+
%8 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 5
119+
%9 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 6
120+
%10 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } %2, 7
121+
ret <8 x i8> %10
122+
}
123+
declare { <8 x i8>, <8 x i8> } @llvm.riscv.seg2.load.v8i8.p0i8.i64(i8*, i64)
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declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg3.load.v8i8.p0i8.i64(i8*, i64)
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declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg4.load.v8i8.p0i8.i64(i8*, i64)
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declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg5.load.v8i8.p0i8.i64(i8*, i64)
127+
declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg6.load.v8i8.p0i8.i64(i8*, i64)
128+
declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg7.load.v8i8.p0i8.i64(i8*, i64)
129+
declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.riscv.seg8.load.v8i8.p0i8.i64(i8*, i64)

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