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1 parent aef5ca5 commit 9802c4cCopy full SHA for 9802c4c
src/libcore/ops.rs
@@ -1645,7 +1645,7 @@ rem_assign_impl! { usize u8 u16 u32 u64 isize i8 i16 i32 i64 f32 f64 }
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#[lang = "bitand_assign"]
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#[stable(feature = "op_assign_traits", since = "1.8.0")]
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pub trait BitAndAssign<Rhs=Self> {
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- /// The method for the `&` operator
+ /// The method for the `&=` operator
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fn bitand_assign(&mut self, Rhs);
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}
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