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couchandcouchand
committedDec 6, 2021
Implement inline asm! for AVR platform
1 parent 09d8a50 commit c6e8ae1

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8 files changed

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‎compiler/rustc_codegen_gcc/src/asm.rs

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -577,6 +577,7 @@ fn reg_to_gcc(reg: InlineAsmRegOrRegClass) -> ConstraintOrRegister {
577577
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => unimplemented!(),
578578
InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
579579
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => unimplemented!(),
580+
InlineAsmRegClass::Avr(_) => unimplemented!(),
580581
InlineAsmRegClass::Bpf(_) => unimplemented!(),
581582
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => unimplemented!(),
582583
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => unimplemented!(),
@@ -639,6 +640,7 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
639640
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
640641
unimplemented!()
641642
}
643+
InlineAsmRegClass::Avr(_) => unimplemented!(),
642644
InlineAsmRegClass::Bpf(_) => unimplemented!(),
643645
InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
644646
InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
@@ -747,6 +749,7 @@ fn modifier_to_gcc(arch: InlineAsmArch, reg: InlineAsmRegClass, modifier: Option
747749
| InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg_low4) => {
748750
unimplemented!()
749751
}
752+
InlineAsmRegClass::Avr(_) => unimplemented!(),
750753
InlineAsmRegClass::Bpf(_) => unimplemented!(),
751754
InlineAsmRegClass::Hexagon(_) => unimplemented!(),
752755
InlineAsmRegClass::Mips(_) => unimplemented!(),

‎compiler/rustc_codegen_llvm/src/asm.rs

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -319,6 +319,9 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
319319
"~{vxrm}".to_string(),
320320
]);
321321
}
322+
InlineAsmArch::Avr => {
323+
constraints.push("~{sreg}".to_string());
324+
}
322325
InlineAsmArch::Nvptx64 => {}
323326
InlineAsmArch::PowerPC | InlineAsmArch::PowerPC64 => {}
324327
InlineAsmArch::Hexagon => {}
@@ -669,6 +672,11 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
669672
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => "r",
670673
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => "r",
671674
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => "w",
675+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => "r",
676+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper) => "d",
677+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) => "r",
678+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) => "w",
679+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => "e",
672680
InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => "r",
673681
InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => "f",
674682
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
@@ -749,6 +757,14 @@ fn modifier_to_llvm(
749757
}
750758
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => None,
751759
InlineAsmRegClass::Bpf(_) => None,
760+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair)
761+
| InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw)
762+
| InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => match modifier {
763+
Some('h') => Some('B'),
764+
Some('l') => Some('A'),
765+
_ => None,
766+
},
767+
InlineAsmRegClass::Avr(_) => None,
752768
InlineAsmRegClass::S390x(_) => None,
753769
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
754770
bug!("LLVM backend does not support SPIR-V")
@@ -812,6 +828,11 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
812828
InlineAsmRegClass::Wasm(WasmInlineAsmRegClass::local) => cx.type_i32(),
813829
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::reg) => cx.type_i64(),
814830
InlineAsmRegClass::Bpf(BpfInlineAsmRegClass::wreg) => cx.type_i32(),
831+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg) => cx.type_i8(),
832+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_upper) => cx.type_i8(),
833+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_pair) => cx.type_i16(),
834+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_iw) => cx.type_i16(),
835+
InlineAsmRegClass::Avr(AvrInlineAsmRegClass::reg_ptr) => cx.type_i16(),
815836
InlineAsmRegClass::S390x(S390xInlineAsmRegClass::reg) => cx.type_i32(),
816837
InlineAsmRegClass::S390x(S390xInlineAsmRegClass::freg) => cx.type_f64(),
817838
InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {

‎compiler/rustc_span/src/symbol.rs

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1052,8 +1052,12 @@ symbols! {
10521052
reg64,
10531053
reg_abcd,
10541054
reg_byte,
1055+
reg_iw,
10551056
reg_nonzero,
1057+
reg_pair,
1058+
reg_ptr,
10561059
reg_thumb,
1060+
reg_upper,
10571061
register_attr,
10581062
register_tool,
10591063
relaxed_adts,

‎compiler/rustc_target/src/asm/avr.rs

Lines changed: 196 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,196 @@
1+
use super::{InlineAsmArch, InlineAsmType};
2+
use rustc_macros::HashStable_Generic;
3+
use std::fmt;
4+
5+
def_reg_class! {
6+
Avr AvrInlineAsmRegClass {
7+
reg,
8+
reg_upper,
9+
reg_pair,
10+
reg_iw,
11+
reg_ptr,
12+
}
13+
}
14+
15+
impl AvrInlineAsmRegClass {
16+
pub fn valid_modifiers(self, _arch: InlineAsmArch) -> &'static [char] {
17+
match self {
18+
Self::reg_pair | Self::reg_iw | Self::reg_ptr => &['h', 'l'],
19+
_ => &[],
20+
}
21+
}
22+
23+
pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
24+
None
25+
}
26+
27+
pub fn suggest_modifier(
28+
self,
29+
_arch: InlineAsmArch,
30+
_ty: InlineAsmType,
31+
) -> Option<(char, &'static str)> {
32+
None
33+
}
34+
35+
pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
36+
None
37+
}
38+
39+
pub fn supported_types(
40+
self,
41+
_arch: InlineAsmArch,
42+
) -> &'static [(InlineAsmType, Option<&'static str>)] {
43+
match self {
44+
Self::reg => types! { _: I8; },
45+
Self::reg_upper => types! { _: I8; },
46+
Self::reg_pair => types! { _: I16; },
47+
Self::reg_iw => types! { _: I16; },
48+
Self::reg_ptr => types! { _: I16; },
49+
}
50+
}
51+
}
52+
53+
def_regs! {
54+
Avr AvrInlineAsmReg AvrInlineAsmRegClass {
55+
r2: reg = ["r2"],
56+
r3: reg = ["r3"],
57+
r4: reg = ["r4"],
58+
r5: reg = ["r5"],
59+
r6: reg = ["r6"],
60+
r7: reg = ["r7"],
61+
r8: reg = ["r8"],
62+
r9: reg = ["r9"],
63+
r10: reg = ["r10"],
64+
r11: reg = ["r11"],
65+
r12: reg = ["r12"],
66+
r13: reg = ["r13"],
67+
r14: reg = ["r14"],
68+
r15: reg = ["r15"],
69+
r16: reg, reg_upper = ["r16"],
70+
r17: reg, reg_upper = ["r17"],
71+
r18: reg, reg_upper = ["r18"],
72+
r19: reg, reg_upper = ["r19"],
73+
r20: reg, reg_upper = ["r20"],
74+
r21: reg, reg_upper = ["r21"],
75+
r22: reg, reg_upper = ["r22"],
76+
r23: reg, reg_upper = ["r23"],
77+
r24: reg, reg_upper = ["r24"],
78+
r25: reg, reg_upper = ["r25"],
79+
r26: reg, reg_upper = ["r26", "XL"],
80+
r27: reg, reg_upper = ["r27", "XH"],
81+
r30: reg, reg_upper = ["r30", "ZL"],
82+
r31: reg, reg_upper = ["r31", "ZH"],
83+
84+
r3r2: reg_pair = ["r3r2"],
85+
r5r4: reg_pair = ["r5r4"],
86+
r7r6: reg_pair = ["r7r6"],
87+
r9r8: reg_pair = ["r9r8"],
88+
r11r10: reg_pair = ["r11r10"],
89+
r13r12: reg_pair = ["r13r12"],
90+
r15r14: reg_pair = ["r15r14"],
91+
r17r16: reg_pair = ["r17r16"],
92+
r19r18: reg_pair = ["r19r18"],
93+
r21r20: reg_pair = ["r21r20"],
94+
r23r22: reg_pair = ["r23r22"],
95+
96+
r25r24: reg_iw, reg_pair = ["r25r24"],
97+
98+
X: reg_ptr, reg_iw, reg_pair = ["r27r26", "X"],
99+
Z: reg_ptr, reg_iw, reg_pair = ["r31r30", "Z"],
100+
101+
#error = ["Y", "YL", "YH"] =>
102+
"the frame pointer cannot be used as an operand for inline asm",
103+
#error = ["SP", "SPL", "SPH"] =>
104+
"the stack pointer cannot be used as an operand for inline asm",
105+
#error = ["r0", "r1", "r1r0"] =>
106+
"r0 and r1 are not available due to an issue in LLVM",
107+
}
108+
}
109+
110+
macro_rules! emit_pairs {
111+
(
112+
$self:ident $modifier:ident,
113+
$($pair:ident $name:literal $hi:literal $lo:literal,)*
114+
) => {
115+
match ($self, $modifier) {
116+
$(
117+
(AvrInlineAsmReg::$pair, Some('h')) => $hi,
118+
(AvrInlineAsmReg::$pair, Some('l')) => $lo,
119+
(AvrInlineAsmReg::$pair, _) => $name,
120+
)*
121+
_ => $self.name(),
122+
}
123+
};
124+
}
125+
126+
impl AvrInlineAsmReg {
127+
pub fn emit(
128+
self,
129+
out: &mut dyn fmt::Write,
130+
_arch: InlineAsmArch,
131+
modifier: Option<char>,
132+
) -> fmt::Result {
133+
let name = emit_pairs! {
134+
self modifier,
135+
Z "Z" "ZH" "ZL",
136+
X "X" "XH" "XL",
137+
r25r24 "r25:r24" "r25" "r24",
138+
r23r22 "r23:r22" "r23" "r22",
139+
r21r20 "r21:r20" "r21" "r20",
140+
r19r18 "r19:r18" "r19" "r18",
141+
r17r16 "r17:r16" "r17" "r16",
142+
r15r14 "r15:r14" "r15" "r14",
143+
r13r12 "r13:r12" "r13" "r12",
144+
r11r10 "r11:r10" "r11" "r10",
145+
r9r8 "r9:r8" "r9" "r8",
146+
r7r6 "r7:r6" "r7" "r6",
147+
r5r4 "r5:r4" "r5" "r4",
148+
r3r2 "r3:r2" "r3" "r2",
149+
};
150+
out.write_str(name)
151+
}
152+
153+
pub fn overlapping_regs(self, mut cb: impl FnMut(AvrInlineAsmReg)) {
154+
cb(self);
155+
156+
macro_rules! reg_conflicts {
157+
(
158+
$(
159+
$pair:ident : $hi:ident $lo:ident,
160+
)*
161+
) => {
162+
match self {
163+
$(
164+
Self::$pair => {
165+
cb(Self::$hi);
166+
cb(Self::$lo);
167+
}
168+
Self::$hi => {
169+
cb(Self::$pair);
170+
}
171+
Self::$lo => {
172+
cb(Self::$pair);
173+
}
174+
)*
175+
}
176+
};
177+
}
178+
179+
reg_conflicts! {
180+
Z : r31 r30,
181+
X : r27 r26,
182+
r25r24 : r25 r24,
183+
r23r22 : r23 r22,
184+
r21r20 : r21 r20,
185+
r19r18 : r19 r18,
186+
r17r16 : r17 r16,
187+
r15r14 : r15 r14,
188+
r13r12 : r13 r12,
189+
r11r10 : r11 r10,
190+
r9r8 : r9 r8,
191+
r7r6 : r7 r6,
192+
r5r4 : r5 r4,
193+
r3r2 : r3 r2,
194+
}
195+
}
196+
}

‎compiler/rustc_target/src/asm/mod.rs

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -148,6 +148,7 @@ macro_rules! types {
148148

149149
mod aarch64;
150150
mod arm;
151+
mod avr;
151152
mod bpf;
152153
mod hexagon;
153154
mod mips;
@@ -161,6 +162,7 @@ mod x86;
161162

162163
pub use aarch64::{AArch64InlineAsmReg, AArch64InlineAsmRegClass};
163164
pub use arm::{ArmInlineAsmReg, ArmInlineAsmRegClass};
165+
pub use avr::{AvrInlineAsmReg, AvrInlineAsmRegClass};
164166
pub use bpf::{BpfInlineAsmReg, BpfInlineAsmRegClass};
165167
pub use hexagon::{HexagonInlineAsmReg, HexagonInlineAsmRegClass};
166168
pub use mips::{MipsInlineAsmReg, MipsInlineAsmRegClass};
@@ -191,6 +193,7 @@ pub enum InlineAsmArch {
191193
Wasm32,
192194
Wasm64,
193195
Bpf,
196+
Avr,
194197
}
195198

196199
impl FromStr for InlineAsmArch {
@@ -215,6 +218,7 @@ impl FromStr for InlineAsmArch {
215218
"wasm32" => Ok(Self::Wasm32),
216219
"wasm64" => Ok(Self::Wasm64),
217220
"bpf" => Ok(Self::Bpf),
221+
"avr" => Ok(Self::Avr),
218222
_ => Err(()),
219223
}
220224
}
@@ -245,6 +249,7 @@ pub enum InlineAsmReg {
245249
SpirV(SpirVInlineAsmReg),
246250
Wasm(WasmInlineAsmReg),
247251
Bpf(BpfInlineAsmReg),
252+
Avr(AvrInlineAsmReg),
248253
// Placeholder for invalid register constraints for the current target
249254
Err,
250255
}
@@ -261,6 +266,7 @@ impl InlineAsmReg {
261266
Self::Mips(r) => r.name(),
262267
Self::S390x(r) => r.name(),
263268
Self::Bpf(r) => r.name(),
269+
Self::Avr(r) => r.name(),
264270
Self::Err => "<reg>",
265271
}
266272
}
@@ -276,6 +282,7 @@ impl InlineAsmReg {
276282
Self::Mips(r) => InlineAsmRegClass::Mips(r.reg_class()),
277283
Self::S390x(r) => InlineAsmRegClass::S390x(r.reg_class()),
278284
Self::Bpf(r) => InlineAsmRegClass::Bpf(r.reg_class()),
285+
Self::Avr(r) => InlineAsmRegClass::Avr(r.reg_class()),
279286
Self::Err => InlineAsmRegClass::Err,
280287
}
281288
}
@@ -326,6 +333,9 @@ impl InlineAsmReg {
326333
InlineAsmArch::Bpf => {
327334
Self::Bpf(BpfInlineAsmReg::parse(arch, has_feature, target, &name)?)
328335
}
336+
InlineAsmArch::Avr => {
337+
Self::Avr(AvrInlineAsmReg::parse(arch, has_feature, target, &name)?)
338+
}
329339
})
330340
}
331341

@@ -347,6 +357,7 @@ impl InlineAsmReg {
347357
Self::Mips(r) => r.emit(out, arch, modifier),
348358
Self::S390x(r) => r.emit(out, arch, modifier),
349359
Self::Bpf(r) => r.emit(out, arch, modifier),
360+
Self::Avr(r) => r.emit(out, arch, modifier),
350361
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
351362
}
352363
}
@@ -362,6 +373,7 @@ impl InlineAsmReg {
362373
Self::Mips(_) => cb(self),
363374
Self::S390x(_) => cb(self),
364375
Self::Bpf(r) => r.overlapping_regs(|r| cb(Self::Bpf(r))),
376+
Self::Avr(r) => r.overlapping_regs(|r| cb(Self::Avr(r))),
365377
Self::Err => unreachable!("Use of InlineAsmReg::Err"),
366378
}
367379
}
@@ -392,6 +404,7 @@ pub enum InlineAsmRegClass {
392404
SpirV(SpirVInlineAsmRegClass),
393405
Wasm(WasmInlineAsmRegClass),
394406
Bpf(BpfInlineAsmRegClass),
407+
Avr(AvrInlineAsmRegClass),
395408
// Placeholder for invalid register constraints for the current target
396409
Err,
397410
}
@@ -411,6 +424,7 @@ impl InlineAsmRegClass {
411424
Self::SpirV(r) => r.name(),
412425
Self::Wasm(r) => r.name(),
413426
Self::Bpf(r) => r.name(),
427+
Self::Avr(r) => r.name(),
414428
Self::Err => rustc_span::symbol::sym::reg,
415429
}
416430
}
@@ -432,6 +446,7 @@ impl InlineAsmRegClass {
432446
Self::SpirV(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::SpirV),
433447
Self::Wasm(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Wasm),
434448
Self::Bpf(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Bpf),
449+
Self::Avr(r) => r.suggest_class(arch, ty).map(InlineAsmRegClass::Avr),
435450
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
436451
}
437452
}
@@ -460,6 +475,7 @@ impl InlineAsmRegClass {
460475
Self::SpirV(r) => r.suggest_modifier(arch, ty),
461476
Self::Wasm(r) => r.suggest_modifier(arch, ty),
462477
Self::Bpf(r) => r.suggest_modifier(arch, ty),
478+
Self::Avr(r) => r.suggest_modifier(arch, ty),
463479
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
464480
}
465481
}
@@ -484,6 +500,7 @@ impl InlineAsmRegClass {
484500
Self::SpirV(r) => r.default_modifier(arch),
485501
Self::Wasm(r) => r.default_modifier(arch),
486502
Self::Bpf(r) => r.default_modifier(arch),
503+
Self::Avr(r) => r.default_modifier(arch),
487504
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
488505
}
489506
}
@@ -507,6 +524,7 @@ impl InlineAsmRegClass {
507524
Self::SpirV(r) => r.supported_types(arch),
508525
Self::Wasm(r) => r.supported_types(arch),
509526
Self::Bpf(r) => r.supported_types(arch),
527+
Self::Avr(r) => r.supported_types(arch),
510528
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
511529
}
512530
}
@@ -535,6 +553,7 @@ impl InlineAsmRegClass {
535553
Self::Wasm(WasmInlineAsmRegClass::parse(arch, name)?)
536554
}
537555
InlineAsmArch::Bpf => Self::Bpf(BpfInlineAsmRegClass::parse(arch, name)?),
556+
InlineAsmArch::Avr => Self::Avr(AvrInlineAsmRegClass::parse(arch, name)?),
538557
})
539558
}
540559

@@ -554,6 +573,7 @@ impl InlineAsmRegClass {
554573
Self::SpirV(r) => r.valid_modifiers(arch),
555574
Self::Wasm(r) => r.valid_modifiers(arch),
556575
Self::Bpf(r) => r.valid_modifiers(arch),
576+
Self::Avr(r) => r.valid_modifiers(arch),
557577
Self::Err => unreachable!("Use of InlineAsmRegClass::Err"),
558578
}
559579
}
@@ -739,6 +759,11 @@ pub fn allocatable_registers(
739759
bpf::fill_reg_map(arch, has_feature, target, &mut map);
740760
map
741761
}
762+
InlineAsmArch::Avr => {
763+
let mut map = avr::regclass_map();
764+
avr::fill_reg_map(arch, has_feature, target, &mut map);
765+
map
766+
}
742767
}
743768
}
744769

‎src/doc/unstable-book/src/library-features/asm.md

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@@ -32,6 +32,7 @@ Inline assembly is currently supported on the following architectures:
3232
- wasm32
3333
- BPF
3434
- SPIR-V
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- AVR
3536

3637
## Basic usage
3738

@@ -471,6 +472,7 @@ Inline assembly is currently supported on the following architectures:
471472
- wasm32
472473
- BPF
473474
- SPIR-V
475+
- AVR
474476

475477
Support for more targets may be added in the future. The compiler will emit an error if `asm!` is used on an unsupported target.
476478

@@ -593,6 +595,11 @@ Here is the list of currently supported register classes:
593595
| wasm32 | `local` | None\* | `r` |
594596
| BPF | `reg` | `r[0-10]` | `r` |
595597
| BPF | `wreg` | `w[0-10]` | `w` |
598+
| AVR | `reg` | `r[2-25]`, `XH`, `XL`, `ZH`, `ZL` | `r` |
599+
| AVR | `reg_upper` | `r[16-25]`, `XH`, `XL`, `ZH`, `ZL` | `d` |
600+
| AVR | `reg_pair` | `r3r2` .. `r25r24`, `X`, `Z` | `r` |
601+
| AVR | `reg_iw` | `r25r24`, `X`, `Z` | `w` |
602+
| AVR | `reg_ptr` | `X`, `Z` | `e` |
596603

597604
> **Note**: On x86 we treat `reg_byte` differently from `reg` because the compiler can allocate `al` and `ah` separately whereas `reg` reserves the whole register.
598605
>
@@ -648,6 +655,8 @@ Each register class has constraints on which value types they can be used with.
648655
| wasm32 | `local` | None | `i8` `i16` `i32` `i64` `f32` `f64` |
649656
| BPF | `reg` | None | `i8` `i16` `i32` `i64` |
650657
| BPF | `wreg` | `alu32` | `i8` `i16` `i32` |
658+
| AVR | `reg`, `reg_upper` | None | `i8` |
659+
| AVR | `reg_pair`, `reg_iw`, `reg_ptr` | None | `i16` |
651660

652661
> **Note**: For the purposes of the above table pointers, function pointers and `isize`/`usize` are treated as the equivalent integer type (`i16`/`i32`/`i64` depending on the target).
653662
@@ -708,13 +717,17 @@ Some registers have multiple names. These are all treated by the compiler as ide
708717
| Hexagon | `r30` | `fr` |
709718
| Hexagon | `r31` | `lr` |
710719
| BPF | `r[0-10]` | `w[0-10]` |
720+
| AVR | `XH` | `r27` |
721+
| AVR | `XL` | `r26` |
722+
| AVR | `ZH` | `r31` |
723+
| AVR | `ZL` | `r30` |
711724

712725
Some registers cannot be used for input or output operands:
713726

714727
| Architecture | Unsupported register | Reason |
715728
| ------------ | -------------------- | ------ |
716729
| All | `sp` | The stack pointer must be restored to its original value at the end of an asm code block. |
717-
| All | `bp` (x86), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon), `$fp` (MIPS) | The frame pointer cannot be used as an input or output. |
730+
| All | `bp` (x86), `x29` (AArch64), `x8` (RISC-V), `fr` (Hexagon), `$fp` (MIPS), `Y` (AVR) | The frame pointer cannot be used as an input or output. |
718731
| ARM | `r7` or `r11` | On ARM the frame pointer can be either `r7` or `r11` depending on the target. The frame pointer cannot be used as an input or output. |
719732
| All | `si` (x86-32), `bx` (x86-64), `r6` (ARM), `x19` (AArch64), `r19` (Hexagon), `x9` (RISC-V) | This is used internally by LLVM as a "base pointer" for functions with complex stack frames. |
720733
| x86 | `k0` | This is a constant zero register which can't be modified. |
@@ -732,11 +745,13 @@ Some registers cannot be used for input or output operands:
732745
| RISC-V | `x0` | This is a constant zero register which can't be modified. |
733746
| RISC-V | `gp`, `tp` | These registers are reserved and cannot be used as inputs or outputs. |
734747
| Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
748+
| AVR | `r0`, `r1`, `r1r0` | Due to an issue in LLVM, the `r0` and `r1` registers cannot be used as inputs or outputs. If modified, they must be restored to their original values before the end of the block. |
735749

736750
In some cases LLVM will allocate a "reserved register" for `reg` operands even though this register cannot be explicitly specified. Assembly code making use of reserved registers should be careful since `reg` operands may alias with those registers. Reserved registers are the frame pointer and base pointer
737751
- The frame pointer and LLVM base pointer on all architectures.
738752
- `r9` on ARM.
739753
- `x18` on AArch64.
754+
- `r0` and `r1` on AVR.
740755

741756
## Template modifiers
742757

@@ -882,6 +897,8 @@ The compiler performs some additional checks on options:
882897
- RISC-V
883898
- Floating-point exception flags in `fcsr` (`fflags`).
884899
- Vector extension state (`vtype`, `vl`, `vcsr`).
900+
- AVR
901+
- The status register `SREG`.
885902
- On x86, the direction flag (DF in `EFLAGS`) is clear on entry to an asm block and must be clear on exit.
886903
- Behavior is undefined if the direction flag is set on exiting an asm block.
887904
- The requirement of restoring the stack pointer and non-output registers to their original value only applies when exiting an `asm!` block.

‎src/test/assembly/asm/avr-modifiers.rs

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@@ -0,0 +1,60 @@
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// min-llvm-version: 13.0
2+
// assembly-output: emit-asm
3+
// compile-flags: --target avr-unknown-gnu-atmega328
4+
// needs-llvm-components: avr
5+
6+
#![feature(no_core, lang_items, rustc_attrs, asm_experimental_arch)]
7+
#![crate_type = "rlib"]
8+
#![no_core]
9+
#![allow(non_camel_case_types)]
10+
11+
#[rustc_builtin_macro]
12+
macro_rules! asm {
13+
() => {};
14+
}
15+
#[rustc_builtin_macro]
16+
macro_rules! concat {
17+
() => {};
18+
}
19+
20+
#[lang = "sized"]
21+
trait Sized {}
22+
#[lang = "copy"]
23+
trait Copy {}
24+
25+
type ptr = *const u64;
26+
27+
impl Copy for i8 {}
28+
impl Copy for i16 {}
29+
impl Copy for i32 {}
30+
impl Copy for i64 {}
31+
impl Copy for ptr {}
32+
33+
macro_rules! check {
34+
($func:ident $hi:literal $lo:literal $reg:tt) => {
35+
#[no_mangle]
36+
unsafe fn $func() -> i16 {
37+
let y;
38+
asm!(concat!("mov {0:", $hi, "}, {0:", $lo, "}"), out($reg) y);
39+
y
40+
}
41+
};
42+
}
43+
44+
// CHECK-LABEL: reg_pair_modifiers:
45+
// CHECK: ;APP
46+
// CHECK: mov r{{[1-9]?[13579]}}, r{{[1-9]?[24680]}}
47+
// CHECK: ;NO_APP
48+
check!(reg_pair_modifiers "h" "l" reg_pair);
49+
50+
// CHECK-LABEL: reg_iw_modifiers:
51+
// CHECK: ;APP
52+
// CHECK: mov r{{[1-9]?[13579]}}, r{{[1-9]?[24680]}}
53+
// CHECK: ;NO_APP
54+
check!(reg_iw_modifiers "h" "l" reg_iw);
55+
56+
// CHECK-LABEL: reg_ptr_modifiers:
57+
// CHECK: ;APP
58+
// CHECK: mov r{{[1-9]?[13579]}}, r{{[1-9]?[24680]}}
59+
// CHECK: ;NO_APP
60+
check!(reg_ptr_modifiers "h" "l" reg_ptr);

‎src/test/assembly/asm/avr-types.rs

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@@ -0,0 +1,222 @@
1+
// min-llvm-version: 13.0
2+
// assembly-output: emit-asm
3+
// compile-flags: --target avr-unknown-gnu-atmega328
4+
// needs-llvm-components: avr
5+
6+
#![feature(no_core, lang_items, rustc_attrs, asm_sym, asm_experimental_arch)]
7+
#![crate_type = "rlib"]
8+
#![no_core]
9+
#![allow(non_camel_case_types)]
10+
11+
#[rustc_builtin_macro]
12+
macro_rules! asm {
13+
() => {};
14+
}
15+
#[rustc_builtin_macro]
16+
macro_rules! concat {
17+
() => {};
18+
}
19+
20+
#[lang = "sized"]
21+
trait Sized {}
22+
#[lang = "copy"]
23+
trait Copy {}
24+
25+
type ptr = *const u64;
26+
27+
impl Copy for i8 {}
28+
impl Copy for i16 {}
29+
impl Copy for i32 {}
30+
impl Copy for i64 {}
31+
impl Copy for ptr {}
32+
33+
macro_rules! check {
34+
($func:ident $ty:ident $class:ident) => {
35+
#[no_mangle]
36+
pub unsafe fn $func(x: $ty) -> $ty {
37+
let y;
38+
asm!("mov {}, {}", lateout($class) y, in($class) x);
39+
y
40+
}
41+
};
42+
}
43+
44+
macro_rules! checkw {
45+
($func:ident $ty:ident $class:ident) => {
46+
#[no_mangle]
47+
pub unsafe fn $func(x: $ty) -> $ty {
48+
let y;
49+
asm!("movw {}, {}", lateout($class) y, in($class) x);
50+
y
51+
}
52+
};
53+
}
54+
55+
macro_rules! check_reg {
56+
($func:ident $ty:ident $reg:tt) => {
57+
#[no_mangle]
58+
pub unsafe fn $func(x: $ty) -> $ty {
59+
let y;
60+
asm!(concat!("mov ", $reg, ", ", $reg), lateout($reg) y, in($reg) x);
61+
y
62+
}
63+
};
64+
}
65+
66+
macro_rules! check_regw {
67+
($func:ident $ty:ident $reg:tt $reg_lit:tt) => {
68+
#[no_mangle]
69+
pub unsafe fn $func(x: $ty) -> $ty {
70+
let y;
71+
asm!(concat!("movw ", $reg_lit, ", ", $reg_lit), lateout($reg) y, in($reg) x);
72+
y
73+
}
74+
};
75+
}
76+
77+
extern "C" {
78+
fn extern_func();
79+
static extern_static: i8;
80+
}
81+
82+
// CHECK-LABEL: sym_fn
83+
// CHECK: ;APP
84+
// CHECK: call extern_func
85+
// CHECK: ;NO_APP
86+
#[no_mangle]
87+
pub unsafe fn sym_fn() {
88+
asm!("call {}", sym extern_func);
89+
}
90+
91+
// CHECK-LABEL: sym_static
92+
// CHECK: ;APP
93+
// CHECK: lds r{{[0-9]+}}, extern_static
94+
// CHECK: ;NO_APP
95+
#[no_mangle]
96+
pub unsafe fn sym_static() -> i8 {
97+
let y;
98+
asm!("lds {}, {}", lateout(reg) y, sym extern_static);
99+
y
100+
}
101+
102+
// CHECK-LABEL: ld_z:
103+
// CHECK: ;APP
104+
// CHECK: ld r{{[0-9]+}}, Z
105+
// CHECK: ;NO_APP
106+
#[no_mangle]
107+
pub unsafe fn ld_z(x: i16) -> i8 {
108+
let y;
109+
asm!("ld {}, Z", out(reg) y, in("Z") x);
110+
y
111+
}
112+
113+
// CHECK-LABEL: ldd_z:
114+
// CHECK: ;APP
115+
// CHECK: ldd r{{[0-9]+}}, Z+4
116+
// CHECK: ;NO_APP
117+
#[no_mangle]
118+
pub unsafe fn ldd_z(x: i16) -> i8 {
119+
let y;
120+
asm!("ldd {}, Z+4", out(reg) y, in("Z") x);
121+
y
122+
}
123+
124+
// CHECK-LABEL: ld_predecrement:
125+
// CHECK: ;APP
126+
// CHECK: ld r{{[0-9]+}}, -Z
127+
// CHECK: ;NO_APP
128+
#[no_mangle]
129+
pub unsafe fn ld_predecrement(x: i16) -> i8 {
130+
let y;
131+
asm!("ld {}, -Z", out(reg) y, in("Z") x);
132+
y
133+
}
134+
135+
// CHECK-LABEL: ld_postincrement:
136+
// CHECK: ;APP
137+
// CHECK: ld r{{[0-9]+}}, Z+
138+
// CHECK: ;NO_APP
139+
#[no_mangle]
140+
pub unsafe fn ld_postincrement(x: i16) -> i8 {
141+
let y;
142+
asm!("ld {}, Z+", out(reg) y, in("Z") x);
143+
y
144+
}
145+
146+
// CHECK-LABEL: muls_clobber:
147+
// CHECK: ;APP
148+
// CHECK: muls r{{[0-9]+}}, r{{[0-9]+}}
149+
// CHECK: movw r{{[0-9]+}}, r0
150+
// CHECK: ;NO_APP
151+
#[no_mangle]
152+
pub unsafe fn muls_clobber(x: i8, y: i8) -> i16 {
153+
let z;
154+
asm!(
155+
"muls {}, {}",
156+
"movw {}, r1:r0",
157+
out(reg_iw) z,
158+
in(reg) x,
159+
in(reg) y,
160+
);
161+
z
162+
}
163+
164+
// CHECK-LABEL: reg_i8:
165+
// CHECK: ;APP
166+
// CHECK: mov r{{[0-9]+}}, r{{[0-9]+}}
167+
// CHECK: ;NO_APP
168+
check!(reg_i8 i8 reg);
169+
170+
// CHECK-LABEL: reg_upper_i8:
171+
// CHECK: ;APP
172+
// CHECK: mov r{{[1-3][0-9]}}, r{{[1-3][0-9]}}
173+
// CHECK: ;NO_APP
174+
check!(reg_upper_i8 i8 reg_upper);
175+
176+
// CHECK-LABEL: reg_pair_i16:
177+
// CHECK: ;APP
178+
// CHECK: movw r{{[0-9]+}}, r{{[0-9]+}}
179+
// CHECK: ;NO_APP
180+
checkw!(reg_pair_i16 i16 reg_pair);
181+
182+
// CHECK-LABEL: reg_iw_i16:
183+
// CHECK: ;APP
184+
// CHECK: movw r{{[0-9]+}}, r{{[0-9]+}}
185+
// CHECK: ;NO_APP
186+
checkw!(reg_iw_i16 i16 reg_iw);
187+
188+
// CHECK-LABEL: reg_ptr_i16:
189+
// CHECK: ;APP
190+
// CHECK: movw r{{[0-9]+}}, r{{[0-9]+}}
191+
// CHECK: ;NO_APP
192+
checkw!(reg_ptr_i16 i16 reg_ptr);
193+
194+
// CHECK-LABEL: r2_i8:
195+
// CHECK: ;APP
196+
// CHECK: mov r2, r2
197+
// CHECK: ;NO_APP
198+
check_reg!(r2_i8 i8 "r2");
199+
200+
// CHECK-LABEL: xl_i8:
201+
// CHECK: ;APP
202+
// CHECK: mov r26, r26
203+
// CHECK: ;NO_APP
204+
check_reg!(xl_i8 i8 "XL");
205+
206+
// CHECK-LABEL: xh_i8:
207+
// CHECK: ;APP
208+
// CHECK: mov r27, r27
209+
// CHECK: ;NO_APP
210+
check_reg!(xh_i8 i8 "XH");
211+
212+
// CHECK-LABEL: x_i16:
213+
// CHECK: ;APP
214+
// CHECK: movw r26, r26
215+
// CHECK: ;NO_APP
216+
check_regw!(x_i16 i16 "X" "X");
217+
218+
// CHECK-LABEL: r25r24_i16:
219+
// CHECK: ;APP
220+
// CHECK: movw r24, r24
221+
// CHECK: ;NO_APP
222+
check_regw!(r25r24_i16 i16 "r25r24" "r24");

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