diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index a408654b6..2c75adf9a 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -50,16 +50,6 @@ jobs:
         rustc -Vv
         cargo -Vv
 
-    - name: Cache binaries
-      id: cache-bin
-      uses: actions/cache@v1
-      with:
-        path: binaries
-        key: ${{ runner.OS }}-binaries
-    - name: Add binaries/bin to PATH
-      run: echo "$GITHUB_WORKSPACE/binaries/bin" >> $GITHUB_PATH
-      shell: bash
-
     - name: "Run cargo build"
       uses: actions-rs/cargo@v1
       with:
@@ -131,6 +121,35 @@ jobs:
         cargo build --target i686-unknown-linux-gnu --no-default-features --features nightly
         cargo build --target thumbv7em-none-eabihf --no-default-features --features nightly
 
+  bootloader-test:
+    name: "Bootloader Integration Test"
+
+    strategy:
+      fail-fast: false
+      matrix:
+        platform: [
+          ubuntu-latest,
+          macos-latest,
+          windows-latest
+        ]
+
+    runs-on: ${{ matrix.platform }}
+    timeout-minutes: 15
+
+    steps:
+    - name: "Checkout Repository"
+      uses: actions/checkout@v1
+
+    - name: Cache binaries
+      id: cache-bin
+      uses: actions/cache@v1
+      with:
+        path: binaries
+        key: ${{ runner.OS }}-binaries
+    - name: Add binaries/bin to PATH
+      run: echo "$GITHUB_WORKSPACE/binaries/bin" >> $GITHUB_PATH
+      shell: bash
+
     - name: "Install Rustup Components"
       run: rustup component add rust-src llvm-tools-preview
     - name: "Install cargo-xbuild"
diff --git a/src/instructions/interrupts.rs b/src/instructions/interrupts.rs
index eee606ee9..d850cf0f3 100644
--- a/src/instructions/interrupts.rs
+++ b/src/instructions/interrupts.rs
@@ -1,5 +1,8 @@
 //! Enabling and disabling interrupts
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
+
 /// Returns whether interrupts are enabled.
 #[inline]
 pub fn are_enabled() -> bool {
diff --git a/src/instructions/mod.rs b/src/instructions/mod.rs
index 27c42f17a..bd35f2a82 100644
--- a/src/instructions/mod.rs
+++ b/src/instructions/mod.rs
@@ -9,6 +9,9 @@ pub mod segmentation;
 pub mod tables;
 pub mod tlb;
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
+
 /// Halts the CPU until the next interrupt arrives.
 #[inline]
 pub fn hlt() {
diff --git a/src/instructions/port.rs b/src/instructions/port.rs
index aa3c40137..fd2362b2f 100644
--- a/src/instructions/port.rs
+++ b/src/instructions/port.rs
@@ -1,5 +1,7 @@
 //! Access to I/O ports
 
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 use core::fmt;
 use core::marker::PhantomData;
 
diff --git a/src/instructions/segmentation.rs b/src/instructions/segmentation.rs
index bf16abe5a..555552c2f 100644
--- a/src/instructions/segmentation.rs
+++ b/src/instructions/segmentation.rs
@@ -6,6 +6,8 @@ use crate::{
     structures::gdt::SegmentSelector,
     VirtAddr,
 };
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 
 macro_rules! get_reg_impl {
     ($name:literal, $asm_get:ident) => {
diff --git a/src/instructions/tables.rs b/src/instructions/tables.rs
index 667fb9b46..0549cce20 100644
--- a/src/instructions/tables.rs
+++ b/src/instructions/tables.rs
@@ -2,6 +2,8 @@
 
 use crate::structures::gdt::SegmentSelector;
 use crate::VirtAddr;
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 
 pub use crate::structures::DescriptorTablePointer;
 
diff --git a/src/instructions/tlb.rs b/src/instructions/tlb.rs
index 008dfadff..4f8565b85 100644
--- a/src/instructions/tlb.rs
+++ b/src/instructions/tlb.rs
@@ -1,6 +1,8 @@
 //! Functions to flush the translation lookaside buffer (TLB).
 
 use crate::VirtAddr;
+#[cfg(feature = "inline_asm")]
+use core::arch::asm;
 
 /// Invalidate the given address in the TLB using the `invlpg` instruction.
 #[inline]
diff --git a/src/registers/control.rs b/src/registers/control.rs
index 8d55d7147..bfa1e50bd 100644
--- a/src/registers/control.rs
+++ b/src/registers/control.rs
@@ -161,6 +161,8 @@ bitflags! {
 mod x86_64 {
     use super::*;
     use crate::{instructions::tlb::Pcid, structures::paging::PhysFrame, PhysAddr, VirtAddr};
+    #[cfg(feature = "inline_asm")]
+    use core::arch::asm;
 
     impl Cr0 {
         /// Read the current set of CR0 flags.
diff --git a/src/registers/model_specific.rs b/src/registers/model_specific.rs
index aa1aa9b64..9c48e6b94 100644
--- a/src/registers/model_specific.rs
+++ b/src/registers/model_specific.rs
@@ -127,6 +127,8 @@ mod x86_64 {
         control::Cr4Flags,
         segmentation::{Segment, Segment64, CS, SS},
     };
+    #[cfg(feature = "inline_asm")]
+    use core::arch::asm;
 
     impl Msr {
         /// Read 64 bits msr register.
diff --git a/src/registers/rflags.rs b/src/registers/rflags.rs
index cb133bf3b..3d5179441 100644
--- a/src/registers/rflags.rs
+++ b/src/registers/rflags.rs
@@ -65,6 +65,8 @@ bitflags! {
 #[cfg(feature = "instructions")]
 mod x86_64 {
     use super::*;
+    #[cfg(feature = "inline_asm")]
+    use core::arch::asm;
 
     /// Returns the current value of the RFLAGS register.
     ///
diff --git a/src/registers/xcontrol.rs b/src/registers/xcontrol.rs
index cc94858c9..36ceea120 100644
--- a/src/registers/xcontrol.rs
+++ b/src/registers/xcontrol.rs
@@ -54,6 +54,9 @@ bitflags! {
 #[cfg(feature = "instructions")]
 mod x86_64 {
     use super::*;
+    #[cfg(feature = "inline_asm")]
+    use core::arch::asm;
+
     impl XCr0 {
         /// Read the current set of XCR0 flags.
         #[inline]