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[RISCV] Add coverage for abdu and abds (absolute difference)
Test copied from aarch64 with minimal adaption. We likely need addition coverage, but this is a reasonable starting point.
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‎llvm/test/CodeGen/RISCV/rvv/abd.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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;
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; SABD
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;
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define <vscale x 16 x i8> @sabd_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: sabd_b:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vwsub.vv v12, v8, v10
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v12, 0
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; CHECK-NEXT: vmax.vv v12, v12, v8
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v12, 0
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; CHECK-NEXT: ret
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%a.sext = sext <vscale x 16 x i8> %a to <vscale x 16 x i16>
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%b.sext = sext <vscale x 16 x i8> %b to <vscale x 16 x i16>
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%sub = sub <vscale x 16 x i16> %a.sext, %b.sext
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%abs = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> %sub, i1 true)
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%trunc = trunc <vscale x 16 x i16> %abs to <vscale x 16 x i8>
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ret <vscale x 16 x i8> %trunc
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}
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define <vscale x 16 x i8> @sabd_b_promoted_ops(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: sabd_b_promoted_ops:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmerge.vim v12, v10, -1, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vmerge.vim v8, v10, -1, v0
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; CHECK-NEXT: vsub.vv v8, v12, v8
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; CHECK-NEXT: vrsub.vi v10, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v10
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; CHECK-NEXT: ret
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%a.sext = sext <vscale x 16 x i1> %a to <vscale x 16 x i8>
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%b.sext = sext <vscale x 16 x i1> %b to <vscale x 16 x i8>
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%sub = sub <vscale x 16 x i8> %a.sext, %b.sext
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%abs = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %sub, i1 true)
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ret <vscale x 16 x i8> %abs
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}
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define <vscale x 8 x i16> @sabd_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: sabd_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vwsub.vv v12, v8, v10
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v12, 0
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; CHECK-NEXT: vmax.vv v12, v12, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v12, 0
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; CHECK-NEXT: ret
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%a.sext = sext <vscale x 8 x i16> %a to <vscale x 8 x i32>
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%b.sext = sext <vscale x 8 x i16> %b to <vscale x 8 x i32>
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%sub = sub <vscale x 8 x i32> %a.sext, %b.sext
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%abs = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> %sub, i1 true)
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%trunc = trunc <vscale x 8 x i32> %abs to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %trunc
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}
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define <vscale x 8 x i16> @sabd_h_promoted_ops(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: sabd_h_promoted_ops:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vwsub.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a.sext = sext <vscale x 8 x i8> %a to <vscale x 8 x i16>
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%b.sext = sext <vscale x 8 x i8> %b to <vscale x 8 x i16>
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%sub = sub <vscale x 8 x i16> %a.sext, %b.sext
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%abs = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %sub, i1 true)
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ret <vscale x 8 x i16> %abs
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}
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define <vscale x 4 x i32> @sabd_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: sabd_s:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vwsub.vv v12, v8, v10
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v12, 0
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; CHECK-NEXT: vmax.vv v12, v12, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v12, 0
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; CHECK-NEXT: ret
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%a.sext = sext <vscale x 4 x i32> %a to <vscale x 4 x i64>
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%b.sext = sext <vscale x 4 x i32> %b to <vscale x 4 x i64>
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%sub = sub <vscale x 4 x i64> %a.sext, %b.sext
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%abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)
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%trunc = trunc <vscale x 4 x i64> %abs to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %trunc
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}
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define <vscale x 4 x i32> @sabd_s_promoted_ops(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
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; CHECK-LABEL: sabd_s_promoted_ops:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vwsub.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a.sext = sext <vscale x 4 x i16> %a to <vscale x 4 x i32>
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%b.sext = sext <vscale x 4 x i16> %b to <vscale x 4 x i32>
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%sub = sub <vscale x 4 x i32> %a.sext, %b.sext
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%abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)
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ret <vscale x 4 x i32> %abs
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}
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; FIXME: Crashes legalization if enabled
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;; define <vscale x 2 x i64> @sabd_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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;; %a.sext = sext <vscale x 2 x i64> %a to <vscale x 2 x i128>
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;; %b.sext = sext <vscale x 2 x i64> %b to <vscale x 2 x i128>
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;; %sub = sub <vscale x 2 x i128> %a.sext, %b.sext
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;; %abs = call <vscale x 2 x i128> @llvm.abs.nxv2i128(<vscale x 2 x i128> %sub, i1 true)
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;; %trunc = trunc <vscale x 2 x i128> %abs to <vscale x 2 x i64>
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;; ret <vscale x 2 x i64> %trunc
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;; }
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define <vscale x 2 x i64> @sabd_d_promoted_ops(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: sabd_d_promoted_ops:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vwsub.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a.sext = sext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%b.sext = sext <vscale x 2 x i32> %b to <vscale x 2 x i64>
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%sub = sub <vscale x 2 x i64> %a.sext, %b.sext
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%abs = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %sub, i1 true)
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ret <vscale x 2 x i64> %abs
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}
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;
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; UABD
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;
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define <vscale x 16 x i8> @uabd_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: uabd_b:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vwsubu.vv v12, v8, v10
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; CHECK-NEXT: vsetvli zero, zero, e16, m4, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v12, 0
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; CHECK-NEXT: vmax.vv v12, v12, v8
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; CHECK-NEXT: vsetvli zero, zero, e8, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v12, 0
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 16 x i8> %a to <vscale x 16 x i16>
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%b.zext = zext <vscale x 16 x i8> %b to <vscale x 16 x i16>
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%sub = sub <vscale x 16 x i16> %a.zext, %b.zext
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%abs = call <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16> %sub, i1 true)
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%trunc = trunc <vscale x 16 x i16> %abs to <vscale x 16 x i8>
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ret <vscale x 16 x i8> %trunc
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}
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define <vscale x 16 x i8> @uabd_b_promoted_ops(<vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
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; CHECK-LABEL: uabd_b_promoted_ops:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
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; CHECK-NEXT: vsub.vv v8, v12, v8
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; CHECK-NEXT: vrsub.vi v10, v8, 0
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; CHECK-NEXT: vmax.vv v8, v8, v10
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 16 x i1> %a to <vscale x 16 x i8>
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%b.zext = zext <vscale x 16 x i1> %b to <vscale x 16 x i8>
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%sub = sub <vscale x 16 x i8> %a.zext, %b.zext
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%abs = call <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8> %sub, i1 true)
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ret <vscale x 16 x i8> %abs
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}
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define <vscale x 8 x i16> @uabd_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: uabd_h:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
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; CHECK-NEXT: vwsubu.vv v12, v8, v10
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v12, 0
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; CHECK-NEXT: vmax.vv v12, v12, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v12, 0
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i16> %a to <vscale x 8 x i32>
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%b.zext = zext <vscale x 8 x i16> %b to <vscale x 8 x i32>
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%sub = sub <vscale x 8 x i32> %a.zext, %b.zext
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%abs = call <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32> %sub, i1 true)
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%trunc = trunc <vscale x 8 x i32> %abs to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %trunc
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}
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define <vscale x 8 x i16> @uabd_h_promoted_ops(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
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; CHECK-LABEL: uabd_h_promoted_ops:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
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; CHECK-NEXT: vwsubu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
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%b.zext = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
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%sub = sub <vscale x 8 x i16> %a.zext, %b.zext
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%abs = call <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16> %sub, i1 true)
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ret <vscale x 8 x i16> %abs
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}
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define <vscale x 4 x i32> @uabd_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: uabd_s:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vwsubu.vv v12, v8, v10
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v12, 0
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; CHECK-NEXT: vmax.vv v12, v12, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v12, 0
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 4 x i32> %a to <vscale x 4 x i64>
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%b.zext = zext <vscale x 4 x i32> %b to <vscale x 4 x i64>
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%sub = sub <vscale x 4 x i64> %a.zext, %b.zext
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%abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)
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%trunc = trunc <vscale x 4 x i64> %abs to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %trunc
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}
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define <vscale x 4 x i32> @uabd_s_promoted_ops(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
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; CHECK-LABEL: uabd_s_promoted_ops:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vwsubu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
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%b.zext = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
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%sub = sub <vscale x 4 x i32> %a.zext, %b.zext
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%abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)
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ret <vscale x 4 x i32> %abs
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}
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; FIXME: Crashes legalization if enabled
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;; define <vscale x 2 x i64> @uabd_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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;; %a.zext = zext <vscale x 2 x i64> %a to <vscale x 2 x i128>
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;; %b.zext = zext <vscale x 2 x i64> %b to <vscale x 2 x i128>
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;; %sub = sub <vscale x 2 x i128> %a.zext, %b.zext
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;; %abs = call <vscale x 2 x i128> @llvm.abs.nxv2i128(<vscale x 2 x i128> %sub, i1 true)
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;; %trunc = trunc <vscale x 2 x i128> %abs to <vscale x 2 x i64>
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;; ret <vscale x 2 x i64> %trunc
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;; }
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define <vscale x 2 x i64> @uabd_d_promoted_ops(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
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; CHECK-LABEL: uabd_d_promoted_ops:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vwsubu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 2 x i32> %a to <vscale x 2 x i64>
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%b.zext = zext <vscale x 2 x i32> %b to <vscale x 2 x i64>
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%sub = sub <vscale x 2 x i64> %a.zext, %b.zext
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%abs = call <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64> %sub, i1 true)
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ret <vscale x 2 x i64> %abs
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}
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; Test the situation where isLegal(ISD::ABD, typeof(%a)) returns true but %a and
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; %b have differing types.
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define <vscale x 4 x i32> @uabd_non_matching_extension(<vscale x 4 x i32> %a, <vscale x 4 x i8> %b) {
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; CHECK-LABEL: uabd_non_matching_extension:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vzext.vf4 v12, v10
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; CHECK-NEXT: vwsubu.vv v16, v8, v12
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v16, 0
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; CHECK-NEXT: vmax.vv v12, v16, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vnsrl.wi v8, v12, 0
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 4 x i32> %a to <vscale x 4 x i64>
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%b.zext = zext <vscale x 4 x i8> %b to <vscale x 4 x i64>
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%sub = sub <vscale x 4 x i64> %a.zext, %b.zext
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%abs = call <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64> %sub, i1 true)
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%trunc = trunc <vscale x 4 x i64> %abs to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %trunc
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}
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; Test the situation where isLegal(ISD::ABD, typeof(%a.zext)) returns true but
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; %a and %b have differing types.
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define <vscale x 4 x i32> @uabd_non_matching_promoted_ops(<vscale x 4 x i8> %a, <vscale x 4 x i16> %b) {
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; CHECK-LABEL: uabd_non_matching_promoted_ops:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vzext.vf2 v10, v8
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; CHECK-NEXT: vwsubu.vv v12, v10, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v12, 0
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; CHECK-NEXT: vmax.vv v8, v12, v8
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 4 x i8> %a to <vscale x 4 x i32>
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%b.zext = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
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%sub = sub <vscale x 4 x i32> %a.zext, %b.zext
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%abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)
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ret <vscale x 4 x i32> %abs
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}
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; Test the situation where isLegal(ISD::ABD, typeof(%a)) returns true but %a and
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; %b are promoted differently.
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define <vscale x 4 x i32> @uabd_non_matching_promotion(<vscale x 4 x i8> %a, <vscale x 4 x i8> %b) {
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; CHECK-LABEL: uabd_non_matching_promotion:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vzext.vf4 v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; CHECK-NEXT: vsext.vf2 v8, v9
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; CHECK-NEXT: vwsub.wv v10, v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: ret
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%a.zext = zext <vscale x 4 x i8> %a to <vscale x 4 x i32>
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%b.zext = sext <vscale x 4 x i8> %b to <vscale x 4 x i32>
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%sub = sub <vscale x 4 x i32> %a.zext, %b.zext
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%abs = call <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32> %sub, i1 true)
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ret <vscale x 4 x i32> %abs
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}
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declare <vscale x 16 x i8> @llvm.abs.nxv16i8(<vscale x 16 x i8>, i1)
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declare <vscale x 8 x i16> @llvm.abs.nxv8i16(<vscale x 8 x i16>, i1)
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declare <vscale x 16 x i16> @llvm.abs.nxv16i16(<vscale x 16 x i16>, i1)
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declare <vscale x 4 x i32> @llvm.abs.nxv4i32(<vscale x 4 x i32>, i1)
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declare <vscale x 8 x i32> @llvm.abs.nxv8i32(<vscale x 8 x i32>, i1)
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declare <vscale x 2 x i64> @llvm.abs.nxv2i64(<vscale x 2 x i64>, i1)
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declare <vscale x 4 x i64> @llvm.abs.nxv4i64(<vscale x 4 x i64>, i1)
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declare <vscale x 2 x i128> @llvm.abs.nxv2i128(<vscale x 2 x i128>, i1)
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; RV32: {{.*}}
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; RV64: {{.*}}

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