Skip to content

Commit 5c4bc7e

Browse files
author
git apple-llvm automerger
committed
Merge commit '4c0251da149c' from llvm.org/master into apple/master
2 parents 1a014a0 + 4c0251d commit 5c4bc7e

File tree

3 files changed

+59
-14
lines changed

3 files changed

+59
-14
lines changed

llvm/lib/Target/AMDGPU/SIFoldOperands.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -668,7 +668,6 @@ void SIFoldOperands::foldOperand(
668668
} else {
669669
if (UseMI->isCopy() && OpToFold.isReg() &&
670670
UseMI->getOperand(0).getReg().isVirtual() &&
671-
TRI->isVectorRegister(*MRI, UseMI->getOperand(0).getReg()) &&
672671
!UseMI->getOperand(1).getSubReg()) {
673672
LLVM_DEBUG(dbgs() << "Folding " << OpToFold
674673
<< "\n into " << *UseMI << '\n');

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3921,20 +3921,18 @@ bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
39213921
? MRI.getRegClass(Reg)
39223922
: RI.getPhysRegClass(Reg);
39233923

3924-
const SIRegisterInfo *TRI =
3925-
static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
3926-
RC = TRI->getSubRegClass(RC, MO.getSubReg());
3927-
3928-
// In order to be legal, the common sub-class must be equal to the
3929-
// class of the current operand. For example:
3930-
//
3931-
// v_mov_b32 s0 ; Operand defined as vsrc_b32
3932-
// ; RI.getCommonSubClass(s0,vsrc_b32) = sgpr ; LEGAL
3933-
//
3934-
// s_sendmsg 0, s0 ; Operand defined as m0reg
3935-
// ; RI.getCommonSubClass(s0,m0reg) = m0reg ; NOT LEGAL
3924+
const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
3925+
if (MO.getSubReg()) {
3926+
const MachineFunction *MF = MO.getParent()->getParent()->getParent();
3927+
const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF);
3928+
if (!SuperRC)
3929+
return false;
39363930

3937-
return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
3931+
DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg());
3932+
if (!DRC)
3933+
return false;
3934+
}
3935+
return RC->hasSuperClassEq(DRC);
39383936
}
39393937

39403938
bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,
Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-fold-operands,dead-mi-elimination -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
2+
3+
---
4+
5+
# GCN-LABEL: name: fold_sgpr_to_sgpr_copy_full
6+
# GCN: %0:sgpr_32 = IMPLICIT_DEF
7+
# GCN-NEXT: S_STORE_DWORD_IMM %0, undef $sgpr10_sgpr11, 0, 0, 0
8+
9+
name: fold_sgpr_to_sgpr_copy_full
10+
body: |
11+
bb.0:
12+
13+
%0:sgpr_32 = IMPLICIT_DEF
14+
%1:sgpr_32 = COPY %0
15+
%2:sgpr_32 = COPY %1
16+
S_STORE_DWORD_IMM %2, undef $sgpr10_sgpr11, 0, 0, 0
17+
...
18+
19+
# GCN-LABEL: name: fold_sgpr_to_sgpr_copy_subreg
20+
# GCN: %0:sreg_64 = IMPLICIT_DEF
21+
# GCN-NEXT: %2:sgpr_32 = COPY %0.sub0
22+
# GCN-NEXT: S_STORE_DWORD_IMM %2, undef $sgpr10_sgpr11, 0, 0, 0
23+
24+
name: fold_sgpr_to_sgpr_copy_subreg
25+
body: |
26+
bb.0:
27+
28+
%0:sreg_64 = IMPLICIT_DEF
29+
%1:sgpr_32 = COPY %0.sub0
30+
%2:sgpr_32 = COPY %1
31+
S_STORE_DWORD_IMM %2, undef $sgpr10_sgpr11, 0, 0, 0
32+
...
33+
34+
# GCN-LABEL: name: fold_sgpr_to_sgpr_copy_subreg2
35+
# GCN: %0:sreg_64 = IMPLICIT_DEF
36+
# GCN-NEXT: %3:sreg_32_xm0_xexec = COPY %0.sub0
37+
# GCN-NEXT: S_STORE_DWORD_IMM %3, undef $sgpr10_sgpr11, 0, 0, 0
38+
39+
name: fold_sgpr_to_sgpr_copy_subreg2
40+
body: |
41+
bb.0:
42+
43+
%0:sreg_64 = IMPLICIT_DEF
44+
%1:sgpr_32 = COPY %0.sub0
45+
%2:sgpr_32 = COPY %1
46+
%3:sreg_32_xm0_xexec = COPY %2
47+
S_STORE_DWORD_IMM %3, undef $sgpr10_sgpr11, 0, 0, 0
48+
...

0 commit comments

Comments
 (0)