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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sad.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v | FileCheck %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
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define signext i16 @sad_4x8_as_i16(<4 x i8> %a, <4 x i8> %b) {
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; CHECK-LABEL: sad_4x8_as_i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vwsubu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: vmv.s.x v9, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v9
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%1 = zext <4 x i8> %a to <4 x i16>
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%3 = zext <4 x i8> %b to <4 x i16>
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%4 = sub nsw <4 x i16> %1, %3
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%5 = tail call <4 x i16> @llvm.abs.v4i16(<4 x i16> %4, i1 true)
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%6 = tail call i16 @llvm.vector.reduce.add.v4i16(<4 x i16> %5)
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ret i16 %6
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}
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define signext i32 @sad_4x8_as_i32(<4 x i8> %a, <4 x i8> %b) {
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; CHECK-LABEL: sad_4x8_as_i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vwsubu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv.s.x v9, zero
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vwredsumu.vs v8, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%1 = zext <4 x i8> %a to <4 x i32>
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%3 = zext <4 x i8> %b to <4 x i32>
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%4 = sub nsw <4 x i32> %1, %3
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%5 = tail call <4 x i32> @llvm.abs.v4i32(<4 x i32> %4, i1 true)
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%6 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %5)
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ret i32 %6
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}
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define signext i16 @sad_16x8_as_i16(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: sad_16x8_as_i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vwsubu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: vmv.s.x v10, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v10
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%1 = zext <16 x i8> %a to <16 x i16>
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%3 = zext <16 x i8> %b to <16 x i16>
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%4 = sub nsw <16 x i16> %1, %3
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%5 = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %4, i1 true)
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%6 = tail call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %5)
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ret i16 %6
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}
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define signext i32 @sad_16x8_as_i32(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: sad_16x8_as_i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vwsubu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: vmax.vv v8, v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v10, zero
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vwredsumu.vs v8, v8, v10
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%1 = zext <16 x i8> %a to <16 x i32>
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%3 = zext <16 x i8> %b to <16 x i32>
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%4 = sub nsw <16 x i32> %1, %3
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%5 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %4, i1 true)
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%6 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %5)
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ret i32 %6
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}
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define signext i32 @sad_2block_16xi8_as_i32(ptr %a, ptr %b, i32 signext %stridea, i32 signext %strideb) {
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; CHECK-LABEL: sad_2block_16xi8_as_i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vle8.v v9, (a1)
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; CHECK-NEXT: vwsubu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: add a0, a0, a2
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; CHECK-NEXT: add a1, a1, a3
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; CHECK-NEXT: vle8.v v8, (a0)
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; CHECK-NEXT: vle8.v v9, (a1)
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; CHECK-NEXT: vrsub.vi v12, v10, 0
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; CHECK-NEXT: vmax.vv v12, v10, v12
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; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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; CHECK-NEXT: vwsubu.vv v10, v8, v9
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v8, v10, 0
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; CHECK-NEXT: add a0, a0, a2
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; CHECK-NEXT: add a1, a1, a3
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; CHECK-NEXT: vle8.v v14, (a0)
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; CHECK-NEXT: vle8.v v15, (a1)
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; CHECK-NEXT: vmax.vv v16, v10, v8
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; CHECK-NEXT: vwaddu.vv v8, v16, v12
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; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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; CHECK-NEXT: vwsubu.vv v12, v14, v15
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v14, v12, 0
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; CHECK-NEXT: add a0, a0, a2
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; CHECK-NEXT: add a1, a1, a3
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; CHECK-NEXT: vle8.v v16, (a0)
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; CHECK-NEXT: vle8.v v17, (a1)
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; CHECK-NEXT: vmax.vv v12, v12, v14
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; CHECK-NEXT: vwaddu.wv v8, v8, v12
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; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
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; CHECK-NEXT: vwsubu.vv v12, v16, v17
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; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
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; CHECK-NEXT: vrsub.vi v14, v12, 0
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; CHECK-NEXT: vmax.vv v12, v12, v14
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; CHECK-NEXT: vwaddu.wv v8, v8, v12
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; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
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; CHECK-NEXT: vmv.s.x v12, zero
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; CHECK-NEXT: vredsum.vs v8, v8, v12
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; CHECK-NEXT: vmv.x.s a0, v8
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; CHECK-NEXT: ret
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entry:
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%idx.ext8 = sext i32 %strideb to i64
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%idx.ext = sext i32 %stridea to i64
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%0 = load <16 x i8>, ptr %a, align 1
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%1 = zext <16 x i8> %0 to <16 x i32>
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%2 = load <16 x i8>, ptr %b, align 1
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%3 = zext <16 x i8> %2 to <16 x i32>
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%4 = sub nsw <16 x i32> %1, %3
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%5 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %4, i1 true)
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%6 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %5)
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%add.ptr = getelementptr inbounds i8, ptr %a, i64 %idx.ext
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%add.ptr9 = getelementptr inbounds i8, ptr %b, i64 %idx.ext8
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%7 = load <16 x i8>, ptr %add.ptr, align 1
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%8 = zext <16 x i8> %7 to <16 x i32>
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%9 = load <16 x i8>, ptr %add.ptr9, align 1
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%10 = zext <16 x i8> %9 to <16 x i32>
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%11 = sub nsw <16 x i32> %8, %10
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%12 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %11, i1 true)
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%13 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %12)
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%op.rdx.1 = add i32 %13, %6
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%add.ptr.1 = getelementptr inbounds i8, ptr %add.ptr, i64 %idx.ext
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%add.ptr9.1 = getelementptr inbounds i8, ptr %add.ptr9, i64 %idx.ext8
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%14 = load <16 x i8>, ptr %add.ptr.1, align 1
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%15 = zext <16 x i8> %14 to <16 x i32>
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%16 = load <16 x i8>, ptr %add.ptr9.1, align 1
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%17 = zext <16 x i8> %16 to <16 x i32>
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%18 = sub nsw <16 x i32> %15, %17
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%19 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %18, i1 true)
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%20 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %19)
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%op.rdx.2 = add i32 %20, %op.rdx.1
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%add.ptr.2 = getelementptr inbounds i8, ptr %add.ptr.1, i64 %idx.ext
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%add.ptr9.2 = getelementptr inbounds i8, ptr %add.ptr9.1, i64 %idx.ext8
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%21 = load <16 x i8>, ptr %add.ptr.2, align 1
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%22 = zext <16 x i8> %21 to <16 x i32>
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%23 = load <16 x i8>, ptr %add.ptr9.2, align 1
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%24 = zext <16 x i8> %23 to <16 x i32>
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%25 = sub nsw <16 x i32> %22, %24
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%26 = tail call <16 x i32> @llvm.abs.v16i32(<16 x i32> %25, i1 true)
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%27 = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %26)
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%op.rdx.3 = add i32 %27, %op.rdx.2
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ret i32 %op.rdx.3
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}
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declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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declare <4 x i16> @llvm.abs.v4i16(<4 x i16>, i1)
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declare i16 @llvm.vector.reduce.add.v4i16(<4 x i16>)
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declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1)
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declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
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declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1)
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declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>)

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