|
| 1 | +/* CMSIS-DAP Interface Firmware |
| 2 | + * Copyright (c) 2009-2013 ARM Limited |
| 3 | + * |
| 4 | + * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | + * you may not use this file except in compliance with the License. |
| 6 | + * You may obtain a copy of the License at |
| 7 | + * |
| 8 | + * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | + * |
| 10 | + * Unless required by applicable law or agreed to in writing, software |
| 11 | + * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | + * See the License for the specific language governing permissions and |
| 14 | + * limitations under the License. |
| 15 | + */ |
| 16 | + |
| 17 | +#ifndef __DAP_H__ |
| 18 | +#define __DAP_H__ |
| 19 | + |
| 20 | + |
| 21 | +// DAP Command IDs |
| 22 | +#define ID_DAP_Info 0x00 |
| 23 | +#define ID_DAP_HostStatus 0x01 |
| 24 | +#define ID_DAP_Connect 0x02 |
| 25 | +#define ID_DAP_Disconnect 0x03 |
| 26 | +#define ID_DAP_TransferConfigure 0x04 |
| 27 | +#define ID_DAP_Transfer 0x05 |
| 28 | +#define ID_DAP_TransferBlock 0x06 |
| 29 | +#define ID_DAP_TransferAbort 0x07 |
| 30 | +#define ID_DAP_WriteABORT 0x08 |
| 31 | +#define ID_DAP_Delay 0x09 |
| 32 | +#define ID_DAP_ResetTarget 0x0A |
| 33 | +#define ID_DAP_SWJ_Pins 0x10 |
| 34 | +#define ID_DAP_SWJ_Clock 0x11 |
| 35 | +#define ID_DAP_SWJ_Sequence 0x12 |
| 36 | +#define ID_DAP_SWD_Configure 0x13 |
| 37 | +#define ID_DAP_JTAG_Sequence 0x14 |
| 38 | +#define ID_DAP_JTAG_Configure 0x15 |
| 39 | +#define ID_DAP_JTAG_IDCODE 0x16 |
| 40 | + |
| 41 | +// DAP Vendor Command IDs |
| 42 | +#define ID_DAP_Vendor0 0x80 |
| 43 | +#define ID_DAP_Vendor1 0x81 |
| 44 | +#define ID_DAP_Vendor2 0x82 |
| 45 | +#define ID_DAP_Vendor3 0x83 |
| 46 | +#define ID_DAP_Vendor4 0x84 |
| 47 | +#define ID_DAP_Vendor5 0x85 |
| 48 | +#define ID_DAP_Vendor6 0x86 |
| 49 | +#define ID_DAP_Vendor7 0x87 |
| 50 | +#define ID_DAP_Vendor8 0x88 |
| 51 | +#define ID_DAP_Vendor9 0x89 |
| 52 | +#define ID_DAP_Vendor10 0x8A |
| 53 | +#define ID_DAP_Vendor11 0x8B |
| 54 | +#define ID_DAP_Vendor12 0x8C |
| 55 | +#define ID_DAP_Vendor13 0x8D |
| 56 | +#define ID_DAP_Vendor14 0x8E |
| 57 | +#define ID_DAP_Vendor15 0x8F |
| 58 | +#define ID_DAP_Vendor16 0x90 |
| 59 | +#define ID_DAP_Vendor17 0x91 |
| 60 | +#define ID_DAP_Vendor18 0x92 |
| 61 | +#define ID_DAP_Vendor19 0x93 |
| 62 | +#define ID_DAP_Vendor20 0x94 |
| 63 | +#define ID_DAP_Vendor21 0x95 |
| 64 | +#define ID_DAP_Vendor22 0x96 |
| 65 | +#define ID_DAP_Vendor23 0x97 |
| 66 | +#define ID_DAP_Vendor24 0x98 |
| 67 | +#define ID_DAP_Vendor25 0x99 |
| 68 | +#define ID_DAP_Vendor26 0x9A |
| 69 | +#define ID_DAP_Vendor27 0x9B |
| 70 | +#define ID_DAP_Vendor28 0x9C |
| 71 | +#define ID_DAP_Vendor29 0x9D |
| 72 | +#define ID_DAP_Vendor30 0x9E |
| 73 | +#define ID_DAP_Vendor31 0x9F |
| 74 | + |
| 75 | +#define ID_DAP_Invalid 0xFF |
| 76 | + |
| 77 | +// DAP Status Code |
| 78 | +#define DAP_OK 0 |
| 79 | +#define DAP_ERROR 0xFF |
| 80 | + |
| 81 | +// DAP ID |
| 82 | +#define DAP_ID_VENDOR 1 |
| 83 | +#define DAP_ID_PRODUCT 2 |
| 84 | +#define DAP_ID_SER_NUM 3 |
| 85 | +#define DAP_ID_FW_VER 4 |
| 86 | +#define DAP_ID_DEVICE_VENDOR 5 |
| 87 | +#define DAP_ID_DEVICE_NAME 6 |
| 88 | +#define DAP_ID_CAPABILITIES 0xF0 |
| 89 | +#define DAP_ID_PACKET_COUNT 0xFE |
| 90 | +#define DAP_ID_PACKET_SIZE 0xFF |
| 91 | + |
| 92 | +// DAP Host Status |
| 93 | +#define DAP_DEBUGGER_CONNECTED 0 |
| 94 | +#define DAP_TARGET_RUNNING 1 |
| 95 | + |
| 96 | +// DAP Port |
| 97 | +#define DAP_PORT_AUTODETECT 0 // Autodetect Port |
| 98 | +#define DAP_PORT_DISABLED 0 // Port Disabled (I/O pins in High-Z) |
| 99 | +#define DAP_PORT_SWD 1 // SWD Port (SWCLK, SWDIO) + nRESET |
| 100 | +#define DAP_PORT_JTAG 2 // JTAG Port (TCK, TMS, TDI, TDO, nTRST) + nRESET |
| 101 | + |
| 102 | +// DAP SWJ Pins |
| 103 | +#define DAP_SWJ_SWCLK_TCK 0 // SWCLK/TCK |
| 104 | +#define DAP_SWJ_SWDIO_TMS 1 // SWDIO/TMS |
| 105 | +#define DAP_SWJ_TDI 2 // TDI |
| 106 | +#define DAP_SWJ_TDO 3 // TDO |
| 107 | +#define DAP_SWJ_nTRST 5 // nTRST |
| 108 | +#define DAP_SWJ_nRESET 7 // nRESET |
| 109 | + |
| 110 | +// DAP Transfer Request |
| 111 | +#define DAP_TRANSFER_APnDP (1<<0) |
| 112 | +#define DAP_TRANSFER_RnW (1<<1) |
| 113 | +#define DAP_TRANSFER_A2 (1<<2) |
| 114 | +#define DAP_TRANSFER_A3 (1<<3) |
| 115 | +#define DAP_TRANSFER_MATCH_VALUE (1<<4) |
| 116 | +#define DAP_TRANSFER_MATCH_MASK (1<<5) |
| 117 | + |
| 118 | +// DAP Transfer Response |
| 119 | +#define DAP_TRANSFER_OK (1<<0) |
| 120 | +#define DAP_TRANSFER_WAIT (1<<1) |
| 121 | +#define DAP_TRANSFER_FAULT (1<<2) |
| 122 | +#define DAP_TRANSFER_ERROR (1<<3) |
| 123 | +#define DAP_TRANSFER_MISMATCH (1<<4) |
| 124 | + |
| 125 | + |
| 126 | +// Debug Port Register Addresses |
| 127 | +#define DP_IDCODE 0x00 // IDCODE Register (SW Read only) |
| 128 | +#define DP_ABORT 0x00 // Abort Register (SW Write only) |
| 129 | +#define DP_CTRL_STAT 0x04 // Control & Status |
| 130 | +#define DP_WCR 0x04 // Wire Control Register (SW Only) |
| 131 | +#define DP_SELECT 0x08 // Select Register (JTAG R/W & SW W) |
| 132 | +#define DP_RESEND 0x08 // Resend (SW Read Only) |
| 133 | +#define DP_RDBUFF 0x0C // Read Buffer (Read Only) |
| 134 | + |
| 135 | +// JTAG IR Codes |
| 136 | +#define JTAG_ABORT 0x08 |
| 137 | +#define JTAG_DPACC 0x0A |
| 138 | +#define JTAG_APACC 0x0B |
| 139 | +#define JTAG_IDCODE 0x0E |
| 140 | +#define JTAG_BYPASS 0x0F |
| 141 | + |
| 142 | +// JTAG Sequence Info |
| 143 | +#define JTAG_SEQUENCE_TCK 0x3F // TCK count |
| 144 | +#define JTAG_SEQUENCE_TMS 0x40 // TMS value |
| 145 | +#define JTAG_SEQUENCE_TDO 0x80 // TDO capture |
| 146 | + |
| 147 | + |
| 148 | +#include <stddef.h> |
| 149 | +#include <stdint.h> |
| 150 | + |
| 151 | +// DAP Data structure |
| 152 | +typedef struct { |
| 153 | + uint8_t debug_port; // Debug Port |
| 154 | + uint8_t fast_clock; // Fast Clock Flag |
| 155 | + uint32_t clock_delay; // Clock Delay |
| 156 | + struct { // Transfer Configuration |
| 157 | + uint8_t idle_cycles; // Idle cycles after transfer |
| 158 | + uint16_t retry_count; // Number of retries after WAIT response |
| 159 | + uint16_t match_retry; // Number of retries if read value does not match |
| 160 | + uint32_t match_mask; // Match Mask |
| 161 | + } transfer; |
| 162 | +#if (DAP_SWD != 0) |
| 163 | + struct { // SWD Configuration |
| 164 | + uint8_t turnaround; // Turnaround period |
| 165 | + uint8_t data_phase; // Always generate Data Phase |
| 166 | + } swd_conf; |
| 167 | +#endif |
| 168 | +#if (DAP_JTAG != 0) |
| 169 | + struct { // JTAG Device Chain |
| 170 | + uint8_t count; // Number of devices |
| 171 | + uint8_t index; // Device index (device at TDO has index 0) |
| 172 | +#if (DAP_JTAG_DEV_CNT != 0) |
| 173 | + uint8_t ir_length[DAP_JTAG_DEV_CNT]; // IR Length in bits |
| 174 | + uint16_t ir_before[DAP_JTAG_DEV_CNT]; // Bits before IR |
| 175 | + uint16_t ir_after [DAP_JTAG_DEV_CNT]; // Bits after IR |
| 176 | +#endif |
| 177 | + } jtag_dev; |
| 178 | +#endif |
| 179 | +} DAP_Data_t; |
| 180 | + |
| 181 | +extern DAP_Data_t DAP_Data; // DAP Data |
| 182 | +extern volatile uint8_t DAP_TransferAbort; // Transfer Abort Flag |
| 183 | + |
| 184 | + |
| 185 | +// Functions |
| 186 | +extern void SWJ_Sequence (uint32_t count, uint8_t *data); |
| 187 | +extern void JTAG_Sequence (uint32_t info, uint8_t *tdi, uint8_t *tdo); |
| 188 | +extern void JTAG_IR (uint32_t ir); |
| 189 | +extern uint32_t JTAG_ReadIDCode (void); |
| 190 | +extern void JTAG_WriteAbort (uint32_t data); |
| 191 | +extern uint8_t JTAG_Transfer (uint32_t request, uint32_t *data); |
| 192 | +extern uint8_t SWD_Transfer (uint32_t request, uint32_t *data); |
| 193 | + |
| 194 | +extern void Delayms (uint32_t delay); |
| 195 | + |
| 196 | +extern uint32_t DAP_ProcessVendorCommand (uint8_t *request, uint8_t *response); |
| 197 | + |
| 198 | +extern uint32_t DAP_ProcessCommand (uint8_t *request, uint8_t *response); |
| 199 | +extern void DAP_Setup (void); |
| 200 | + |
| 201 | +// Configurable delay for clock generation |
| 202 | +#ifndef DELAY_SLOW_CYCLES |
| 203 | +#define DELAY_SLOW_CYCLES 3 // Number of cycles for one iteration |
| 204 | +#endif |
| 205 | +static __forceinline void PIN_DELAY_SLOW (uint32_t delay) { |
| 206 | + int32_t count; |
| 207 | + |
| 208 | + count = delay; |
| 209 | + while (--count); |
| 210 | +} |
| 211 | + |
| 212 | +// Fixed delay for fast clock generation |
| 213 | +#ifndef DELAY_FAST_CYCLES |
| 214 | +#define DELAY_FAST_CYCLES 0 // Number of cycles: 0..3 |
| 215 | +#endif |
| 216 | +static __forceinline void PIN_DELAY_FAST (void) { |
| 217 | +#if (DELAY_FAST_CYCLES >= 1) |
| 218 | + __nop(); |
| 219 | +#endif |
| 220 | +#if (DELAY_FAST_CYCLES >= 2) |
| 221 | + __nop(); |
| 222 | +#endif |
| 223 | +#if (DELAY_FAST_CYCLES >= 3) |
| 224 | + __nop(); |
| 225 | +#endif |
| 226 | +} |
| 227 | + |
| 228 | + |
| 229 | +#endif /* __DAP_H__ */ |
0 commit comments