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vtr_flow/tasks/regression_tests/vtr_reg_strong
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+ #
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+ ############################################
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+ # Configuration file for running experiments
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+ ##############################################
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+
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+ # Path to directory of circuits to use
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+ circuits_dir=benchmarks/verilog
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+
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+ # Path to directory of architectures to use
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+ archs_dir=arch/timing
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+
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+ # Add circuits to list to sweep
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+ # circuit_list_add=arm_core.v
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+ circuit_list_add=boundtop_nolatches.v
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+ circuit_list_add=ch_intrinsics_nolatches.v
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+ circuit_list_add=diffeq1.v
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+ circuit_list_add=diffeq2.v
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+ # circuit_list_add=or1200.v
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+ circuit_list_add=raygentop_nolatches.v
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+ circuit_list_add=stereovision3.v
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+
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+ # Add architectures to list to sweep
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+ arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
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+
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+ # Parse info and how to parse
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+ parse_file=vpr_fixed_chan_width.txt
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+
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+ # How to parse QoR info
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+ qor_parse_file=qor_fixed_chan_width.txt
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+
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+ # Pass requirements
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+ pass_requirements_file=pass_requirements_fixed_chan_width.txt
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+
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+ #Script parameters
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+ script_params=-track_memory_usage -crit_path_router_iterations 100 -parser slang --route_chan_width 128
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+
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